1# ========================================================================== 2# Building 3# ========================================================================== 4 5src := $(obj) 6 7PHONY := __build 8__build: 9 10# Read .config if it exist, otherwise ignore 11-include .config 12 13include scripts/Kbuild.include 14 15# The filename Kbuild has precedence over Makefile 16# bbox: we also try to include Kbuild file in obj tree first 17kbuild-dir := $(if $(filter /%,$(src)),$(src),$(srctree)/$(src)) 18include $(if $(wildcard $(src)/Kbuild), $(src)/Kbuild, \ 19 $(if $(wildcard $(kbuild-dir)/Kbuild), $(kbuild-dir)/Kbuild, \ 20 $(kbuild-dir)/Makefile \ 21 ) \ 22 ) 23 24include scripts/Makefile.lib 25 26ifdef host-progs 27ifneq ($(hostprogs-y),$(host-progs)) 28$(warning kbuild: $(obj)/Makefile - Usage of host-progs is deprecated. Please replace with hostprogs-y!) 29hostprogs-y += $(host-progs) 30endif 31endif 32 33# Do not include host rules unles needed 34ifneq ($(hostprogs-y)$(hostprogs-m),) 35include scripts/Makefile.host 36endif 37 38ifneq ($(KBUILD_SRC),) 39# Create output directory if not already present 40_dummy := $(shell [ -d $(obj) ] || mkdir -p $(obj)) 41 42# Create directories for object files if directory does not exist 43# Needed when obj-y := dir/file.o syntax is used 44_dummy := $(foreach d,$(obj-dirs), $(shell [ -d $(d) ] || mkdir -p $(d))) 45endif 46 47 48ifdef EXTRA_TARGETS 49$(warning kbuild: $(obj)/Makefile - Usage of EXTRA_TARGETS is obsolete in 2.6. Please fix!) 50endif 51 52ifdef build-targets 53$(warning kbuild: $(obj)/Makefile - Usage of build-targets is obsolete in 2.6. Please fix!) 54endif 55 56ifdef export-objs 57$(warning kbuild: $(obj)/Makefile - Usage of export-objs is obsolete in 2.6. Please fix!) 58endif 59 60ifdef O_TARGET 61$(warning kbuild: $(obj)/Makefile - Usage of O_TARGET := $(O_TARGET) is obsolete in 2.6. Please fix!) 62endif 63 64ifdef L_TARGET 65$(error kbuild: $(obj)/Makefile - Use of L_TARGET is replaced by lib-y in 2.6. Please fix!) 66endif 67 68ifdef list-multi 69$(warning kbuild: $(obj)/Makefile - list-multi := $(list-multi) is obsolete in 2.6. Please fix!) 70endif 71 72ifndef obj 73$(warning kbuild: Makefile.build is included improperly) 74endif 75 76# =========================================================================== 77 78ifneq ($(strip $(lib-y) $(lib-m) $(lib-n) $(lib-)),) 79lib-target := $(obj)/lib.a 80endif 81 82ifneq ($(strip $(obj-y) $(obj-m) $(obj-n) $(obj-) $(lib-target)),) 83builtin-target := $(obj)/built-in.o 84endif 85 86# We keep a list of all modules in $(MODVERDIR) 87 88__build: $(if $(KBUILD_BUILTIN),$(builtin-target) $(lib-target) $(extra-y)) \ 89 $(if $(KBUILD_MODULES),$(obj-m)) \ 90 $(subdir-ym) $(always) 91 @: 92 93# Linus' kernel sanity checking tool 94ifneq ($(KBUILD_CHECKSRC),0) 95 ifeq ($(KBUILD_CHECKSRC),2) 96 quiet_cmd_force_checksrc = CHECK $< 97 cmd_force_checksrc = $(CHECK) $(CHECKFLAGS) $(c_flags) $< ; 98 else 99 quiet_cmd_checksrc = CHECK $< 100 cmd_checksrc = $(CHECK) $(CHECKFLAGS) $(c_flags) $< ; 101 endif 102endif 103 104 105# Compile C sources (.c) 106# --------------------------------------------------------------------------- 107 108# Default is built-in, unless we know otherwise 109modkern_cflags := $(CFLAGS_KERNEL) 110quiet_modtag := $(empty) $(empty) 111 112$(real-objs-m) : modkern_cflags := $(CFLAGS_MODULE) 113$(real-objs-m:.o=.i) : modkern_cflags := $(CFLAGS_MODULE) 114$(real-objs-m:.o=.s) : modkern_cflags := $(CFLAGS_MODULE) 115$(real-objs-m:.o=.lst): modkern_cflags := $(CFLAGS_MODULE) 116 117$(real-objs-m) : quiet_modtag := [M] 118$(real-objs-m:.o=.i) : quiet_modtag := [M] 119$(real-objs-m:.o=.s) : quiet_modtag := [M] 120$(real-objs-m:.o=.lst): quiet_modtag := [M] 121 122$(obj-m) : quiet_modtag := [M] 123 124# Default for not multi-part modules 125modname = $(*F) 126 127$(multi-objs-m) : modname = $(modname-multi) 128$(multi-objs-m:.o=.i) : modname = $(modname-multi) 129$(multi-objs-m:.o=.s) : modname = $(modname-multi) 130$(multi-objs-m:.o=.lst) : modname = $(modname-multi) 131$(multi-objs-y) : modname = $(modname-multi) 132$(multi-objs-y:.o=.i) : modname = $(modname-multi) 133$(multi-objs-y:.o=.s) : modname = $(modname-multi) 134$(multi-objs-y:.o=.lst) : modname = $(modname-multi) 135 136quiet_cmd_cc_s_c = CC $(quiet_modtag) $@ 137cmd_cc_s_c = $(CC) $(c_flags) -fverbose-asm -S -o $@ $< 138 139%.s: %.c FORCE 140 $(call if_changed_dep,cc_s_c) 141 142quiet_cmd_cc_i_c = CPP $(quiet_modtag) $@ 143cmd_cc_i_c = $(CPP) $(c_flags) -o $@ $< 144 145%.i: %.c FORCE 146 $(call if_changed_dep,cc_i_c) 147 148# C (.c) files 149# The C file is compiled and updated dependency information is generated. 150# (See cmd_cc_o_c + relevant part of rule_cc_o_c) 151 152quiet_cmd_cc_o_c = CC $(quiet_modtag) $@ 153 154ifndef CONFIG_MODVERSIONS 155cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $< 156 157else 158# When module versioning is enabled the following steps are executed: 159# o compile a .tmp_<file>.o from <file>.c 160# o if .tmp_<file>.o doesn't contain a __ksymtab version, i.e. does 161# not export symbols, we just rename .tmp_<file>.o to <file>.o and 162# are done. 163# o otherwise, we calculate symbol versions using the good old 164# genksyms on the preprocessed source and postprocess them in a way 165# that they are usable as a linker script 166# o generate <file>.o from .tmp_<file>.o using the linker to 167# replace the unresolved symbols __crc_exported_symbol with 168# the actual value of the checksum generated by genksyms 169 170cmd_cc_o_c = $(CC) $(c_flags) -c -o $(@D)/.tmp_$(@F) $< 171cmd_modversions = \ 172 if $(OBJDUMP) -h $(@D)/.tmp_$(@F) | grep -q __ksymtab; then \ 173 $(CPP) -D__GENKSYMS__ $(c_flags) $< \ 174 | $(GENKSYMS) -a $(ARCH) \ 175 > $(@D)/.tmp_$(@F:.o=.ver); \ 176 \ 177 $(LD) $(LDFLAGS) -r -o $@ $(@D)/.tmp_$(@F) \ 178 -T $(@D)/.tmp_$(@F:.o=.ver); \ 179 rm -f $(@D)/.tmp_$(@F) $(@D)/.tmp_$(@F:.o=.ver); \ 180 else \ 181 mv -f $(@D)/.tmp_$(@F) $@; \ 182 fi; 183endif 184 185define rule_cc_o_c 186 $(call echo-cmd,checksrc) $(cmd_checksrc) \ 187 $(call echo-cmd,cc_o_c) $(cmd_cc_o_c); \ 188 $(cmd_modversions) \ 189 scripts/basic/fixdep $(depfile) $@ '$(call make-cmd,cc_o_c)' > $(@D)/.$(@F).tmp; \ 190 rm -f $(depfile); \ 191 mv -f $(@D)/.$(@F).tmp $(@D)/.$(@F).cmd 192endef 193 194# Built-in and composite module parts 195 196%.o: %.c FORCE 197 $(call cmd,force_checksrc) 198 $(call if_changed_rule,cc_o_c) 199 200# Single-part modules are special since we need to mark them in $(MODVERDIR) 201 202$(single-used-m): %.o: %.c FORCE 203 $(call cmd,force_checksrc) 204 $(call if_changed_rule,cc_o_c) 205 @{ echo $(@:.o=.ko); echo $@; } > $(MODVERDIR)/$(@F:.o=.mod) 206 207quiet_cmd_cc_lst_c = MKLST $@ 208 cmd_cc_lst_c = $(CC) $(c_flags) -g -c -o $*.o $< && \ 209 $(CONFIG_SHELL) $(srctree)/scripts/makelst $*.o \ 210 System.map $(OBJDUMP) > $@ 211 212%.lst: %.c FORCE 213 $(call if_changed_dep,cc_lst_c) 214 215# Compile assembler sources (.S) 216# --------------------------------------------------------------------------- 217 218modkern_aflags := $(AFLAGS_KERNEL) 219 220$(real-objs-m) : modkern_aflags := $(AFLAGS_MODULE) 221$(real-objs-m:.o=.s): modkern_aflags := $(AFLAGS_MODULE) 222 223quiet_cmd_as_s_S = CPP $(quiet_modtag) $@ 224cmd_as_s_S = $(CPP) $(a_flags) -o $@ $< 225 226%.s: %.S FORCE 227 $(call if_changed_dep,as_s_S) 228 229quiet_cmd_as_o_S = AS $(quiet_modtag) $@ 230cmd_as_o_S = $(CC) $(a_flags) -c -o $@ $< 231 232%.o: %.S FORCE 233 $(call if_changed_dep,as_o_S) 234 235targets += $(real-objs-y) $(real-objs-m) $(lib-y) 236targets += $(extra-y) $(MAKECMDGOALS) $(always) 237 238# Linker scripts preprocessor (.lds.S -> .lds) 239# --------------------------------------------------------------------------- 240quiet_cmd_cpp_lds_S = LDS $@ 241 cmd_cpp_lds_S = $(CPP) $(cpp_flags) -D__ASSEMBLY__ -o $@ $< 242 243%.lds: %.lds.S FORCE 244 $(call if_changed_dep,cpp_lds_S) 245 246# Build the compiled-in targets 247# --------------------------------------------------------------------------- 248 249# To build objects in subdirs, we need to descend into the directories 250$(sort $(subdir-obj-y)): $(subdir-ym) ; 251 252# 253# Rule to compile a set of .o files into one .o file 254# 255ifdef builtin-target 256quiet_cmd_link_o_target = LD $@ 257# If the list of objects to link is empty, just create an empty built-in.o 258# -nostdlib is added to make "make LD=gcc ..." work (some people use that) 259cmd_link_o_target = $(if $(strip $(obj-y)),\ 260 $(LD) -nostdlib $(ld_flags) -r -o $@ $(filter $(obj-y), $^),\ 261 rm -f $@; $(AR) rcs $@) 262 263$(builtin-target): $(obj-y) FORCE 264 $(call if_changed,link_o_target) 265 266targets += $(builtin-target) 267endif # builtin-target 268 269# 270# Rule to compile a set of .o files into one .a file 271# 272ifdef lib-target 273quiet_cmd_link_l_target = AR $@ 274cmd_link_l_target = rm -f $@; $(AR) $(EXTRA_ARFLAGS) rcs $@ $(lib-y) 275 276$(lib-target): $(lib-y) FORCE 277 $(call if_changed,link_l_target) 278 279targets += $(lib-target) 280endif 281 282# 283# Rule to link composite objects 284# 285# Composite objects are specified in kbuild makefile as follows: 286# <composite-object>-objs := <list of .o files> 287# or 288# <composite-object>-y := <list of .o files> 289link_multi_deps = \ 290$(filter $(addprefix $(obj)/, \ 291$($(subst $(obj)/,,$(@:.o=-objs))) \ 292$($(subst $(obj)/,,$(@:.o=-y)))), $^) 293 294quiet_cmd_link_multi-y = LD $@ 295cmd_link_multi-y = $(LD) $(ld_flags) -r -o $@ $(link_multi_deps) 296 297quiet_cmd_link_multi-m = LD [M] $@ 298cmd_link_multi-m = $(LD) $(ld_flags) $(LDFLAGS_MODULE) -o $@ $(link_multi_deps) 299 300# We would rather have a list of rules like 301# foo.o: $(foo-objs) 302# but that's not so easy, so we rather make all composite objects depend 303# on the set of all their parts 304$(multi-used-y) : %.o: $(multi-objs-y) FORCE 305 $(call if_changed,link_multi-y) 306 307$(multi-used-m) : %.o: $(multi-objs-m) FORCE 308 $(call if_changed,link_multi-m) 309 @{ echo $(@:.o=.ko); echo $(link_multi_deps); } > $(MODVERDIR)/$(@F:.o=.mod) 310 311targets += $(multi-used-y) $(multi-used-m) 312 313 314# Descending 315# --------------------------------------------------------------------------- 316 317PHONY += $(subdir-ym) 318$(subdir-ym): 319 $(Q)$(MAKE) $(build)=$@ 320 321# Add FORCE to the prequisites of a target to force it to be always rebuilt. 322# --------------------------------------------------------------------------- 323 324PHONY += FORCE 325 326FORCE: 327 328# Read all saved command lines and dependencies for the $(targets) we 329# may be building above, using $(if_changed{,_dep}). As an 330# optimization, we don't need to read them if the target does not 331# exist, we will rebuild anyway in that case. 332 333targets := $(wildcard $(sort $(targets))) 334cmd_files := $(wildcard $(foreach f,$(targets),$(dir $(f)).$(notdir $(f)).cmd)) 335 336ifneq ($(cmd_files),) 337 include $(cmd_files) 338endif 339 340 341# Declare the contents of the .PHONY variable as phony. We keep that 342# information in a variable se we can use it in if_changed and friends. 343 344.PHONY: $(PHONY) 345