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4
5#ifndef _E1000_DEFINES_H_
6#define _E1000_DEFINES_H_
7
8
9#define REQ_TX_DESCRIPTOR_MULTIPLE 8
10#define REQ_RX_DESCRIPTOR_MULTIPLE 8
11
12
13
14#define E1000_WUC_APME 0x00000001
15#define E1000_WUC_PME_EN 0x00000002
16#define E1000_WUC_PME_STATUS 0x00000004
17#define E1000_WUC_APMPME 0x00000008
18#define E1000_WUC_PHY_WAKE 0x00000100
19
20
21#define E1000_WUFC_LNKC 0x00000001
22#define E1000_WUFC_MAG 0x00000002
23#define E1000_WUFC_EX 0x00000004
24#define E1000_WUFC_MC 0x00000008
25#define E1000_WUFC_BC 0x00000010
26#define E1000_WUFC_ARP 0x00000020
27#define E1000_WUFC_IPV4 0x00000040
28#define E1000_WUFC_FLX0 0x00010000
29
30
31#define E1000_WUS_LNKC E1000_WUFC_LNKC
32#define E1000_WUS_MAG E1000_WUFC_MAG
33#define E1000_WUS_EX E1000_WUFC_EX
34#define E1000_WUS_MC E1000_WUFC_MC
35#define E1000_WUS_BC E1000_WUFC_BC
36
37
38#define E1000_CTRL_EXT_LPCD 0x00000004
39#define E1000_CTRL_EXT_SDP4_DATA 0x00000010
40#define E1000_CTRL_EXT_SDP6_DATA 0x00000040
41#define E1000_CTRL_EXT_SDP3_DATA 0x00000080
42
43#define E1000_CTRL_EXT_SDP4_DIR 0x00000100
44#define E1000_CTRL_EXT_SDP6_DIR 0x00000400
45#define E1000_CTRL_EXT_SDP3_DIR 0x00000800
46#define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800
47#define E1000_CTRL_EXT_EE_RST 0x00002000
48
49#define E1000_CTRL_EXT_PFRSTD 0x00004000
50#define E1000_CTRL_EXT_SDLPE 0X00040000
51#define E1000_CTRL_EXT_SPD_BYPS 0x00008000
52#define E1000_CTRL_EXT_RO_DIS 0x00020000
53#define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000
54#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
55
56#define E1000_CTRL_EXT_LINK_MODE_OFFSET 22
57#define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000
58#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
59#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
60#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
61#define E1000_CTRL_EXT_EIAME 0x01000000
62#define E1000_CTRL_EXT_IRCA 0x00000001
63#define E1000_CTRL_EXT_DRV_LOAD 0x10000000
64#define E1000_CTRL_EXT_IAME 0x08000000
65#define E1000_CTRL_EXT_PBA_CLR 0x80000000
66#define E1000_CTRL_EXT_LSECCK 0x00001000
67#define E1000_CTRL_EXT_PHYPDEN 0x00100000
68#define E1000_I2CCMD_REG_ADDR_SHIFT 16
69#define E1000_I2CCMD_PHY_ADDR_SHIFT 24
70#define E1000_I2CCMD_OPCODE_READ 0x08000000
71#define E1000_I2CCMD_OPCODE_WRITE 0x00000000
72#define E1000_I2CCMD_READY 0x20000000
73#define E1000_I2CCMD_ERROR 0x80000000
74#define E1000_I2CCMD_SFP_DATA_ADDR(a) (0x0000 + (a))
75#define E1000_I2CCMD_SFP_DIAG_ADDR(a) (0x0100 + (a))
76#define E1000_MAX_SGMII_PHY_REG_ADDR 255
77#define E1000_I2CCMD_PHY_TIMEOUT 200
78#define E1000_IVAR_VALID 0x80
79#define E1000_GPIE_NSICR 0x00000001
80#define E1000_GPIE_MSIX_MODE 0x00000010
81#define E1000_GPIE_EIAME 0x40000000
82#define E1000_GPIE_PBA 0x80000000
83
84
85#define E1000_RXD_STAT_DD 0x01
86#define E1000_RXD_STAT_EOP 0x02
87#define E1000_RXD_STAT_IXSM 0x04
88#define E1000_RXD_STAT_VP 0x08
89#define E1000_RXD_STAT_UDPCS 0x10
90#define E1000_RXD_STAT_TCPCS 0x20
91#define E1000_RXD_STAT_IPCS 0x40
92#define E1000_RXD_STAT_PIF 0x80
93#define E1000_RXD_STAT_IPIDV 0x200
94#define E1000_RXD_STAT_UDPV 0x400
95#define E1000_RXD_STAT_DYNINT 0x800
96#define E1000_RXD_ERR_CE 0x01
97#define E1000_RXD_ERR_SE 0x02
98#define E1000_RXD_ERR_SEQ 0x04
99#define E1000_RXD_ERR_CXE 0x10
100#define E1000_RXD_ERR_TCPE 0x20
101#define E1000_RXD_ERR_IPE 0x40
102#define E1000_RXD_ERR_RXE 0x80
103#define E1000_RXD_SPC_VLAN_MASK 0x0FFF
104
105#define E1000_RXDEXT_STATERR_TST 0x00000100
106#define E1000_RXDEXT_STATERR_LB 0x00040000
107#define E1000_RXDEXT_STATERR_CE 0x01000000
108#define E1000_RXDEXT_STATERR_SE 0x02000000
109#define E1000_RXDEXT_STATERR_SEQ 0x04000000
110#define E1000_RXDEXT_STATERR_CXE 0x10000000
111#define E1000_RXDEXT_STATERR_TCPE 0x20000000
112#define E1000_RXDEXT_STATERR_IPE 0x40000000
113#define E1000_RXDEXT_STATERR_RXE 0x80000000
114
115
116#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
117 E1000_RXD_ERR_CE | \
118 E1000_RXD_ERR_SE | \
119 E1000_RXD_ERR_SEQ | \
120 E1000_RXD_ERR_CXE | \
121 E1000_RXD_ERR_RXE)
122
123
124#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
125 E1000_RXDEXT_STATERR_CE | \
126 E1000_RXDEXT_STATERR_SE | \
127 E1000_RXDEXT_STATERR_SEQ | \
128 E1000_RXDEXT_STATERR_CXE | \
129 E1000_RXDEXT_STATERR_RXE)
130
131#define E1000_MRQC_ENABLE_RSS_2Q 0x00000001
132#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
133#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
134#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
135#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
136#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
137#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
138
139#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
140
141
142#define E1000_MANC_SMBUS_EN 0x00000001
143#define E1000_MANC_ASF_EN 0x00000002
144#define E1000_MANC_ARP_EN 0x00002000
145#define E1000_MANC_RCV_TCO_EN 0x00020000
146#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000
147
148#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
149
150#define E1000_MANC_EN_MNG2HOST 0x00200000
151
152#define E1000_MANC2H_PORT_623 0x00000020
153#define E1000_MANC2H_PORT_664 0x00000040
154#define E1000_MDEF_PORT_623 0x00000800
155#define E1000_MDEF_PORT_664 0x00000400
156
157
158#define E1000_RCTL_RST 0x00000001
159#define E1000_RCTL_EN 0x00000002
160#define E1000_RCTL_SBP 0x00000004
161#define E1000_RCTL_UPE 0x00000008
162#define E1000_RCTL_MPE 0x00000010
163#define E1000_RCTL_LPE 0x00000020
164#define E1000_RCTL_LBM_NO 0x00000000
165#define E1000_RCTL_LBM_MAC 0x00000040
166#define E1000_RCTL_LBM_TCVR 0x000000C0
167#define E1000_RCTL_DTYP_PS 0x00000400
168#define E1000_RCTL_RDMTS_HALF 0x00000000
169#define E1000_RCTL_RDMTS_HEX 0x00010000
170#define E1000_RCTL_RDMTS1_HEX E1000_RCTL_RDMTS_HEX
171#define E1000_RCTL_MO_SHIFT 12
172#define E1000_RCTL_MO_3 0x00003000
173#define E1000_RCTL_BAM 0x00008000
174
175#define E1000_RCTL_SZ_2048 0x00000000
176#define E1000_RCTL_SZ_1024 0x00010000
177#define E1000_RCTL_SZ_512 0x00020000
178#define E1000_RCTL_SZ_256 0x00030000
179
180#define E1000_RCTL_SZ_16384 0x00010000
181#define E1000_RCTL_SZ_8192 0x00020000
182#define E1000_RCTL_SZ_4096 0x00030000
183#define E1000_RCTL_VFE 0x00040000
184#define E1000_RCTL_CFIEN 0x00080000
185#define E1000_RCTL_CFI 0x00100000
186#define E1000_RCTL_DPF 0x00400000
187#define E1000_RCTL_PMCF 0x00800000
188#define E1000_RCTL_BSEX 0x02000000
189#define E1000_RCTL_SECRC 0x04000000
190
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204
205
206
207#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
208#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
209#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
210#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
211
212#define E1000_PSRCTL_BSIZE0_SHIFT 7
213#define E1000_PSRCTL_BSIZE1_SHIFT 2
214#define E1000_PSRCTL_BSIZE2_SHIFT 6
215#define E1000_PSRCTL_BSIZE3_SHIFT 14
216
217
218#define E1000_SWFW_EEP_SM 0x01
219#define E1000_SWFW_PHY0_SM 0x02
220#define E1000_SWFW_PHY1_SM 0x04
221#define E1000_SWFW_CSR_SM 0x08
222#define E1000_SWFW_PHY2_SM 0x20
223#define E1000_SWFW_PHY3_SM 0x40
224#define E1000_SWFW_SW_MNG_SM 0x400
225
226
227#define E1000_CTRL_FD 0x00000001
228#define E1000_CTRL_PRIOR 0x00000004
229#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004
230#define E1000_CTRL_LRST 0x00000008
231#define E1000_CTRL_ASDE 0x00000020
232#define E1000_CTRL_SLU 0x00000040
233#define E1000_CTRL_ILOS 0x00000080
234#define E1000_CTRL_SPD_SEL 0x00000300
235#define E1000_CTRL_SPD_10 0x00000000
236#define E1000_CTRL_SPD_100 0x00000100
237#define E1000_CTRL_SPD_1000 0x00000200
238#define E1000_CTRL_FRCSPD 0x00000800
239#define E1000_CTRL_FRCDPX 0x00001000
240#define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000
241#define E1000_CTRL_LANPHYPC_VALUE 0x00020000
242#define E1000_CTRL_MEHE 0x00080000
243#define E1000_CTRL_SWDPIN0 0x00040000
244#define E1000_CTRL_SWDPIN1 0x00080000
245#define E1000_CTRL_SWDPIN2 0x00100000
246#define E1000_CTRL_ADVD3WUC 0x00100000
247#define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
248#define E1000_CTRL_SWDPIN3 0x00200000
249#define E1000_CTRL_SWDPIO0 0x00400000
250#define E1000_CTRL_SWDPIO2 0x01000000
251#define E1000_CTRL_SWDPIO3 0x02000000
252#define E1000_CTRL_DEV_RST 0x20000000
253#define E1000_CTRL_RST 0x04000000
254#define E1000_CTRL_RFCE 0x08000000
255#define E1000_CTRL_TFCE 0x10000000
256#define E1000_CTRL_VME 0x40000000
257#define E1000_CTRL_PHY_RST 0x80000000
258#define E1000_CTRL_I2C_ENA 0x02000000
259
260#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
261#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
262#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
263#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
264
265#define E1000_CONNSW_ENRGSRC 0x4
266#define E1000_CONNSW_PHYSD 0x400
267#define E1000_CONNSW_PHY_PDN 0x800
268#define E1000_CONNSW_SERDESD 0x200
269#define E1000_CONNSW_AUTOSENSE_CONF 0x2
270#define E1000_CONNSW_AUTOSENSE_EN 0x1
271#define E1000_PCS_CFG_PCS_EN 8
272#define E1000_PCS_LCTL_FLV_LINK_UP 1
273#define E1000_PCS_LCTL_FSV_10 0
274#define E1000_PCS_LCTL_FSV_100 2
275#define E1000_PCS_LCTL_FSV_1000 4
276#define E1000_PCS_LCTL_FDV_FULL 8
277#define E1000_PCS_LCTL_FSD 0x10
278#define E1000_PCS_LCTL_FORCE_LINK 0x20
279#define E1000_PCS_LCTL_FORCE_FCTRL 0x80
280#define E1000_PCS_LCTL_AN_ENABLE 0x10000
281#define E1000_PCS_LCTL_AN_RESTART 0x20000
282#define E1000_PCS_LCTL_AN_TIMEOUT 0x40000
283#define E1000_ENABLE_SERDES_LOOPBACK 0x0410
284
285#define E1000_PCS_LSTS_LINK_OK 1
286#define E1000_PCS_LSTS_SPEED_100 2
287#define E1000_PCS_LSTS_SPEED_1000 4
288#define E1000_PCS_LSTS_DUPLEX_FULL 8
289#define E1000_PCS_LSTS_SYNK_OK 0x10
290#define E1000_PCS_LSTS_AN_COMPLETE 0x10000
291
292
293#define E1000_STATUS_FD 0x00000001
294#define E1000_STATUS_LU 0x00000002
295#define E1000_STATUS_FUNC_MASK 0x0000000C
296#define E1000_STATUS_FUNC_SHIFT 2
297#define E1000_STATUS_FUNC_1 0x00000004
298#define E1000_STATUS_TXOFF 0x00000010
299#define E1000_STATUS_SPEED_MASK 0x000000C0
300#define E1000_STATUS_SPEED_10 0x00000000
301#define E1000_STATUS_SPEED_100 0x00000040
302#define E1000_STATUS_SPEED_1000 0x00000080
303#define E1000_STATUS_LAN_INIT_DONE 0x00000200
304#define E1000_STATUS_PHYRA 0x00000400
305#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000
306#define E1000_STATUS_PCI66 0x00000800
307#define E1000_STATUS_BUS64 0x00001000
308#define E1000_STATUS_2P5_SKU 0x00001000
309#define E1000_STATUS_2P5_SKU_OVER 0x00002000
310#define E1000_STATUS_PCIX_MODE 0x00002000
311#define E1000_STATUS_PCIX_SPEED 0x0000C000
312
313
314#define E1000_STATUS_PCIX_SPEED_66 0x00000000
315#define E1000_STATUS_PCIX_SPEED_100 0x00004000
316#define E1000_STATUS_PCIX_SPEED_133 0x00008000
317#define E1000_STATUS_PCIM_STATE 0x40000000
318
319#define SPEED_10 10
320#define SPEED_100 100
321#define SPEED_1000 1000
322#define SPEED_2500 2500
323#define HALF_DUPLEX 1
324#define FULL_DUPLEX 2
325
326#define PHY_FORCE_TIME 20
327
328#define ADVERTISE_10_HALF 0x0001
329#define ADVERTISE_10_FULL 0x0002
330#define ADVERTISE_100_HALF 0x0004
331#define ADVERTISE_100_FULL 0x0008
332#define ADVERTISE_1000_HALF 0x0010
333#define ADVERTISE_1000_FULL 0x0020
334
335
336#define E1000_ALL_SPEED_DUPLEX ( \
337 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
338 ADVERTISE_100_FULL | ADVERTISE_1000_FULL)
339#define E1000_ALL_NOT_GIG ( \
340 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
341 ADVERTISE_100_FULL)
342#define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
343#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
344#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
345
346#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
347
348
349#define E1000_PHY_LED0_MODE_MASK 0x00000007
350#define E1000_PHY_LED0_IVRT 0x00000008
351#define E1000_PHY_LED0_MASK 0x0000001F
352
353#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
354#define E1000_LEDCTL_LED0_MODE_SHIFT 0
355#define E1000_LEDCTL_LED0_IVRT 0x00000040
356#define E1000_LEDCTL_LED0_BLINK 0x00000080
357
358#define E1000_LEDCTL_MODE_LINK_UP 0x2
359#define E1000_LEDCTL_MODE_LED_ON 0xE
360#define E1000_LEDCTL_MODE_LED_OFF 0xF
361
362
363#define E1000_TXD_DTYP_D 0x00100000
364#define E1000_TXD_DTYP_C 0x00000000
365#define E1000_TXD_POPTS_IXSM 0x01
366#define E1000_TXD_POPTS_TXSM 0x02
367#define E1000_TXD_CMD_EOP 0x01000000
368#define E1000_TXD_CMD_IFCS 0x02000000
369#define E1000_TXD_CMD_IC 0x04000000
370#define E1000_TXD_CMD_RS 0x08000000
371#define E1000_TXD_CMD_RPS 0x10000000
372#define E1000_TXD_CMD_DEXT 0x20000000
373#define E1000_TXD_CMD_VLE 0x40000000
374#define E1000_TXD_CMD_IDE 0x80000000
375#define E1000_TXD_STAT_DD 0x00000001
376#define E1000_TXD_STAT_EC 0x00000002
377#define E1000_TXD_STAT_LC 0x00000004
378#define E1000_TXD_STAT_TU 0x00000008
379#define E1000_TXD_CMD_TCP 0x01000000
380#define E1000_TXD_CMD_IP 0x02000000
381#define E1000_TXD_CMD_TSE 0x04000000
382#define E1000_TXD_STAT_TC 0x00000004
383#define E1000_TXD_EXTCMD_TSTAMP 0x00000010
384
385
386#define E1000_TCTL_EN 0x00000002
387#define E1000_TCTL_PSP 0x00000008
388#define E1000_TCTL_CT 0x00000ff0
389#define E1000_TCTL_COLD 0x003ff000
390#define E1000_TCTL_RTLC 0x01000000
391#define E1000_TCTL_MULR 0x10000000
392
393
394#define E1000_TARC0_ENABLE 0x00000400
395
396
397#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
398#define E1000_SCTL_ENABLE_SERDES_LOOPBACK 0x0410
399
400
401#define E1000_RXCSUM_IPOFL 0x00000100
402#define E1000_RXCSUM_TUOFL 0x00000200
403#define E1000_RXCSUM_CRCOFL 0x00000800
404#define E1000_RXCSUM_IPPCSE 0x00001000
405#define E1000_RXCSUM_PCSD 0x00002000
406
407
408#define E1000_RFCTL_NFSW_DIS 0x00000040
409#define E1000_RFCTL_NFSR_DIS 0x00000080
410#define E1000_RFCTL_ACK_DIS 0x00001000
411#define E1000_RFCTL_EXTEN 0x00008000
412#define E1000_RFCTL_IPV6_EX_DIS 0x00010000
413#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
414#define E1000_RFCTL_LEF 0x00040000
415
416
417#define E1000_CT_SHIFT 4
418#define E1000_COLLISION_THRESHOLD 15
419#define E1000_COLLISION_DISTANCE 63
420#define E1000_COLD_SHIFT 12
421
422
423#define DEFAULT_82542_TIPG_IPGT 10
424#define DEFAULT_82543_TIPG_IPGT_FIBER 9
425#define DEFAULT_82543_TIPG_IPGT_COPPER 8
426
427#define E1000_TIPG_IPGT_MASK 0x000003FF
428
429#define DEFAULT_82542_TIPG_IPGR1 2
430#define DEFAULT_82543_TIPG_IPGR1 8
431#define E1000_TIPG_IPGR1_SHIFT 10
432
433#define DEFAULT_82542_TIPG_IPGR2 10
434#define DEFAULT_82543_TIPG_IPGR2 6
435#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
436#define E1000_TIPG_IPGR2_SHIFT 20
437
438
439#define ETHERNET_IEEE_VLAN_TYPE 0x8100
440
441#define ETHERNET_FCS_SIZE 4
442#define MAX_JUMBO_FRAME_SIZE 0x3F00
443
444#define MAX_RX_JUMBO_FRAME_SIZE 0x2600
445#define E1000_TX_PTR_GAP 0x1F
446
447
448#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
449#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
450#define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008
451#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
452#define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080
453#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000
454#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16
455#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000
456#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16
457
458#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
459#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
460#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
461#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
462
463#define E1000_KABGTXD_BGSQLBIAS 0x00050000
464
465
466#define E1000_LPIC_LPIET_SHIFT 24
467
468
469#define E1000_PBA_8K 0x0008
470#define E1000_PBA_10K 0x000A
471#define E1000_PBA_12K 0x000C
472#define E1000_PBA_14K 0x000E
473#define E1000_PBA_16K 0x0010
474#define E1000_PBA_18K 0x0012
475#define E1000_PBA_20K 0x0014
476#define E1000_PBA_22K 0x0016
477#define E1000_PBA_24K 0x0018
478#define E1000_PBA_26K 0x001A
479#define E1000_PBA_30K 0x001E
480#define E1000_PBA_32K 0x0020
481#define E1000_PBA_34K 0x0022
482#define E1000_PBA_35K 0x0023
483#define E1000_PBA_38K 0x0026
484#define E1000_PBA_40K 0x0028
485#define E1000_PBA_48K 0x0030
486#define E1000_PBA_64K 0x0040
487
488#define E1000_PBA_RXA_MASK 0xFFFF
489
490#define E1000_PBS_16K E1000_PBA_16K
491
492
493#define E1000_PBECCSTS_CORR_ERR_CNT_MASK 0x000000FF
494#define E1000_PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000FF00
495#define E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT 8
496#define E1000_PBECCSTS_ECC_ENABLE 0x00010000
497
498#define IFS_MAX 80
499#define IFS_MIN 40
500#define IFS_RATIO 4
501#define IFS_STEP 10
502#define MIN_NUM_XMITS 1000
503
504
505#define E1000_SWSM_SMBI 0x00000001
506#define E1000_SWSM_SWESMBI 0x00000002
507#define E1000_SWSM_DRV_LOAD 0x00000008
508
509#define E1000_SWSM2_LOCK 0x00000002
510
511
512#define E1000_ICR_TXDW 0x00000001
513#define E1000_ICR_TXQE 0x00000002
514#define E1000_ICR_LSC 0x00000004
515#define E1000_ICR_RXSEQ 0x00000008
516#define E1000_ICR_RXDMT0 0x00000010
517#define E1000_ICR_RXO 0x00000040
518#define E1000_ICR_RXT0 0x00000080
519#define E1000_ICR_VMMB 0x00000100
520#define E1000_ICR_RXCFG 0x00000400
521#define E1000_ICR_GPI_EN0 0x00000800
522#define E1000_ICR_GPI_EN1 0x00001000
523#define E1000_ICR_GPI_EN2 0x00002000
524#define E1000_ICR_GPI_EN3 0x00004000
525#define E1000_ICR_TXD_LOW 0x00008000
526#define E1000_ICR_MNG 0x00040000
527#define E1000_ICR_ECCER 0x00400000
528#define E1000_ICR_TS 0x00080000
529#define E1000_ICR_DRSTA 0x40000000
530
531#define E1000_ICR_INT_ASSERTED 0x80000000
532#define E1000_ICR_DOUTSYNC 0x10000000
533#define E1000_ICR_RXQ0 0x00100000
534#define E1000_ICR_RXQ1 0x00200000
535#define E1000_ICR_TXQ0 0x00400000
536#define E1000_ICR_TXQ1 0x00800000
537#define E1000_ICR_OTHER 0x01000000
538#define E1000_ICR_FER 0x00400000
539
540#define E1000_ICR_THS 0x00800000
541#define E1000_ICR_MDDET 0x10000000
542
543
544#define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000
545#define E1000_PBA_ECC_COUNTER_SHIFT 20
546#define E1000_PBA_ECC_CORR_EN 0x00000001
547#define E1000_PBA_ECC_STAT_CLR 0x00000002
548#define E1000_PBA_ECC_INT_EN 0x00000004
549
550
551#define E1000_EICR_RX_QUEUE0 0x00000001
552#define E1000_EICR_RX_QUEUE1 0x00000002
553#define E1000_EICR_RX_QUEUE2 0x00000004
554#define E1000_EICR_RX_QUEUE3 0x00000008
555#define E1000_EICR_TX_QUEUE0 0x00000100
556#define E1000_EICR_TX_QUEUE1 0x00000200
557#define E1000_EICR_TX_QUEUE2 0x00000400
558#define E1000_EICR_TX_QUEUE3 0x00000800
559#define E1000_EICR_TCP_TIMER 0x40000000
560#define E1000_EICR_OTHER 0x80000000
561
562#define E1000_TCPTIMER_KS 0x00000100
563#define E1000_TCPTIMER_COUNT_ENABLE 0x00000200
564#define E1000_TCPTIMER_COUNT_FINISH 0x00000400
565#define E1000_TCPTIMER_LOOP 0x00000800
566
567
568
569
570
571
572
573
574
575#define IMS_ENABLE_MASK ( \
576 E1000_IMS_RXT0 | \
577 E1000_IMS_TXDW | \
578 E1000_IMS_RXDMT0 | \
579 E1000_IMS_RXSEQ | \
580 E1000_IMS_LSC)
581
582
583#define E1000_IMS_TXDW E1000_ICR_TXDW
584#define E1000_IMS_TXQE E1000_ICR_TXQE
585#define E1000_IMS_LSC E1000_ICR_LSC
586#define E1000_IMS_VMMB E1000_ICR_VMMB
587#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ
588#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0
589#define E1000_IMS_RXO E1000_ICR_RXO
590#define E1000_IMS_RXT0 E1000_ICR_RXT0
591#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
592#define E1000_IMS_ECCER E1000_ICR_ECCER
593#define E1000_IMS_TS E1000_ICR_TS
594#define E1000_IMS_DRSTA E1000_ICR_DRSTA
595#define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC
596#define E1000_IMS_RXQ0 E1000_ICR_RXQ0
597#define E1000_IMS_RXQ1 E1000_ICR_RXQ1
598#define E1000_IMS_TXQ0 E1000_ICR_TXQ0
599#define E1000_IMS_TXQ1 E1000_ICR_TXQ1
600#define E1000_IMS_OTHER E1000_ICR_OTHER
601#define E1000_IMS_FER E1000_ICR_FER
602
603#define E1000_IMS_THS E1000_ICR_THS
604#define E1000_IMS_MDDET E1000_ICR_MDDET
605
606#define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0
607#define E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1
608#define E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2
609#define E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3
610#define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0
611#define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1
612#define E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2
613#define E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3
614#define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER
615#define E1000_EIMS_OTHER E1000_EICR_OTHER
616
617
618#define E1000_ICS_LSC E1000_ICR_LSC
619#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ
620#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0
621
622
623#define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0
624#define E1000_EICS_RX_QUEUE1 E1000_EICR_RX_QUEUE1
625#define E1000_EICS_RX_QUEUE2 E1000_EICR_RX_QUEUE2
626#define E1000_EICS_RX_QUEUE3 E1000_EICR_RX_QUEUE3
627#define E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0
628#define E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1
629#define E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2
630#define E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3
631#define E1000_EICS_TCP_TIMER E1000_EICR_TCP_TIMER
632#define E1000_EICS_OTHER E1000_EICR_OTHER
633
634#define E1000_EITR_ITR_INT_MASK 0x0000FFFF
635
636#define E1000_EITR_CNT_IGNR 0x80000000
637#define E1000_EITR_INTERVAL 0x00007FFC
638
639
640#define E1000_TXDCTL_PTHRESH 0x0000003F
641#define E1000_TXDCTL_HTHRESH 0x00003F00
642#define E1000_TXDCTL_WTHRESH 0x003F0000
643#define E1000_TXDCTL_GRAN 0x01000000
644#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000
645#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F
646
647#define E1000_TXDCTL_COUNT_DESC 0x00400000
648
649
650#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
651#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
652#define FLOW_CONTROL_TYPE 0x8808
653
654
655#define VLAN_TAG_SIZE 4
656#define E1000_VLAN_FILTER_TBL_SIZE 128
657
658
659
660
661
662
663
664
665#define E1000_RAR_ENTRIES 15
666#define E1000_RAH_AV 0x80000000
667#define E1000_RAL_MAC_ADDR_LEN 4
668#define E1000_RAH_MAC_ADDR_LEN 2
669#define E1000_RAH_QUEUE_MASK_82575 0x000C0000
670#define E1000_RAH_POOL_1 0x00040000
671
672
673#define E1000_SUCCESS 0
674#define E1000_ERR_NVM 1
675#define E1000_ERR_PHY 2
676#define E1000_ERR_CONFIG 3
677#define E1000_ERR_PARAM 4
678#define E1000_ERR_MAC_INIT 5
679#define E1000_ERR_PHY_TYPE 6
680#define E1000_ERR_RESET 9
681#define E1000_ERR_MASTER_REQUESTS_PENDING 10
682#define E1000_ERR_HOST_INTERFACE_COMMAND 11
683#define E1000_BLK_PHY_RESET 12
684#define E1000_ERR_SWFW_SYNC 13
685#define E1000_NOT_IMPLEMENTED 14
686#define E1000_ERR_MBX 15
687#define E1000_ERR_INVALID_ARGUMENT 16
688#define E1000_ERR_NO_SPACE 17
689#define E1000_ERR_NVM_PBA_SECTION 18
690#define E1000_ERR_I2C 19
691#define E1000_ERR_INVM_VALUE_NOT_FOUND 20
692
693
694#define FIBER_LINK_UP_LIMIT 50
695#define COPPER_LINK_UP_LIMIT 10
696#define PHY_AUTO_NEG_LIMIT 45
697#define PHY_FORCE_LIMIT 20
698
699#define MASTER_DISABLE_TIMEOUT 800
700
701#define PHY_CFG_TIMEOUT 100
702
703#define MDIO_OWNERSHIP_TIMEOUT 10
704
705#define AUTO_READ_DONE_TIMEOUT 10
706
707
708#define E1000_FCRTH_RTH 0x0000FFF8
709#define E1000_FCRTL_RTL 0x0000FFF8
710#define E1000_FCRTL_XONE 0x80000000
711
712
713#define E1000_TXCW_FD 0x00000020
714#define E1000_TXCW_PAUSE 0x00000080
715#define E1000_TXCW_ASM_DIR 0x00000100
716#define E1000_TXCW_PAUSE_MASK 0x00000180
717#define E1000_TXCW_ANE 0x80000000
718
719
720#define E1000_RXCW_CW 0x0000ffff
721#define E1000_RXCW_IV 0x08000000
722#define E1000_RXCW_C 0x20000000
723#define E1000_RXCW_SYNCH 0x40000000
724
725#define E1000_TSYNCTXCTL_VALID 0x00000001
726#define E1000_TSYNCTXCTL_ENABLED 0x00000010
727
728
729#define E1000_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK 0x0000F000
730#define E1000_TSYNCTXCTL_SYNC_COMP_ERR 0x20000000
731#define E1000_TSYNCTXCTL_SYNC_COMP 0x40000000
732#define E1000_TSYNCTXCTL_START_SYNC 0x80000000
733
734#define E1000_TSYNCRXCTL_VALID 0x00000001
735#define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E
736#define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00
737#define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02
738#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
739#define E1000_TSYNCRXCTL_TYPE_ALL 0x08
740#define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
741#define E1000_TSYNCRXCTL_ENABLED 0x00000010
742#define E1000_TSYNCRXCTL_SYSCFI 0x00000020
743
744#define E1000_RXMTRL_PTP_V1_SYNC_MESSAGE 0x00000000
745#define E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE 0x00010000
746
747#define E1000_RXMTRL_PTP_V2_SYNC_MESSAGE 0x00000000
748#define E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE 0x01000000
749
750#define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF
751#define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00
752#define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01
753#define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02
754#define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03
755#define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04
756
757#define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00
758#define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000
759#define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100
760#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200
761#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300
762#define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800
763#define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900
764#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00
765#define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00
766#define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00
767#define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00
768
769#define E1000_TIMINCA_16NS_SHIFT 24
770#define E1000_TIMINCA_INCPERIOD_SHIFT 24
771#define E1000_TIMINCA_INCVALUE_MASK 0x00FFFFFF
772
773
774#define E1000_ETQF_1588 (1 << 30)
775#define E1000_FTQF_VF_BP 0x00008000
776#define E1000_FTQF_1588_TIME_STAMP 0x08000000
777#define E1000_FTQF_MASK 0xF0000000
778#define E1000_FTQF_MASK_PROTO_BP 0x10000000
779
780#define E1000_IMIREXT_CTRL_BP 0x00080000
781#define E1000_IMIREXT_SIZE_BP 0x00001000
782
783#define E1000_RXDADV_STAT_TSIP 0x08000
784#define E1000_TSICR_TXTS 0x00000002
785#define E1000_TSIM_TXTS 0x00000002
786
787#define E1000_TTQF_DISABLE_MASK 0xF0008000
788#define E1000_TTQF_QUEUE_ENABLE 0x100
789#define E1000_TTQF_PROTOCOL_MASK 0xFF
790
791#define E1000_TTQF_PROTOCOL_TCP 0x0
792
793#define E1000_TTQF_PROTOCOL_UDP 0x1
794
795#define E1000_TTQF_PROTOCOL_SCTP 0x2
796#define E1000_TTQF_PROTOCOL_SHIFT 5
797#define E1000_TTQF_QUEUE_SHIFT 16
798#define E1000_TTQF_RX_QUEUE_MASK 0x70000
799#define E1000_TTQF_MASK_ENABLE 0x10000000
800#define E1000_IMIR_CLEAR_MASK 0xF001FFFF
801#define E1000_IMIR_PORT_BYPASS 0x20000
802#define E1000_IMIR_PRIORITY_SHIFT 29
803#define E1000_IMIREXT_CLEAR_MASK 0x7FFFF
804
805#define E1000_MDICNFG_EXT_MDIO 0x80000000
806#define E1000_MDICNFG_COM_MDIO 0x40000000
807#define E1000_MDICNFG_PHY_MASK 0x03E00000
808#define E1000_MDICNFG_PHY_SHIFT 21
809
810#define E1000_MEDIA_PORT_COPPER 1
811#define E1000_MEDIA_PORT_OTHER 2
812#define E1000_M88E1112_AUTO_COPPER_SGMII 0x2
813#define E1000_M88E1112_AUTO_COPPER_BASEX 0x3
814#define E1000_M88E1112_STATUS_LINK 0x0004
815#define E1000_M88E1112_MAC_CTRL_1 0x10
816#define E1000_M88E1112_MAC_CTRL_1_MODE_MASK 0x0380
817#define E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT 7
818#define E1000_M88E1112_PAGE_ADDR 0x16
819#define E1000_M88E1112_STATUS 0x01
820
821#define E1000_THSTAT_LOW_EVENT 0x20000000
822#define E1000_THSTAT_MID_EVENT 0x00200000
823#define E1000_THSTAT_HIGH_EVENT 0x00002000
824#define E1000_THSTAT_PWR_DOWN 0x00000001
825#define E1000_THSTAT_LINK_THROTTLE 0x00000002
826
827
828#define E1000_IPCNFG_EEE_1G_AN 0x00000008
829#define E1000_IPCNFG_EEE_100M_AN 0x00000004
830#define E1000_EEER_TX_LPI_EN 0x00010000
831#define E1000_EEER_RX_LPI_EN 0x00020000
832#define E1000_EEER_LPI_FC 0x00040000
833
834#define E1000_EEER_EEE_NEG 0x20000000
835#define E1000_EEER_RX_LPI_STATUS 0x40000000
836#define E1000_EEER_TX_LPI_STATUS 0x80000000
837#define E1000_EEE_LP_ADV_ADDR_I350 0x040F
838#define E1000_M88E1543_PAGE_ADDR 0x16
839#define E1000_M88E1543_EEE_CTRL_1 0x0
840#define E1000_M88E1543_EEE_CTRL_1_MS 0x0001
841#define E1000_M88E1543_FIBER_CTRL 0x0
842#define E1000_EEE_ADV_DEV_I354 7
843#define E1000_EEE_ADV_ADDR_I354 60
844#define E1000_EEE_ADV_100_SUPPORTED (1 << 1)
845#define E1000_EEE_ADV_1000_SUPPORTED (1 << 2)
846#define E1000_PCS_STATUS_DEV_I354 3
847#define E1000_PCS_STATUS_ADDR_I354 1
848#define E1000_PCS_STATUS_RX_LPI_RCVD 0x0400
849#define E1000_PCS_STATUS_TX_LPI_RCVD 0x0800
850#define E1000_M88E1512_CFG_REG_1 0x0010
851#define E1000_M88E1512_CFG_REG_2 0x0011
852#define E1000_M88E1512_CFG_REG_3 0x0007
853#define E1000_M88E1512_MODE 0x0014
854#define E1000_EEE_SU_LPI_CLK_STP 0x00800000
855#define E1000_EEE_LP_ADV_DEV_I210 7
856#define E1000_EEE_LP_ADV_ADDR_I210 61
857
858#define E1000_GCR_RXD_NO_SNOOP 0x00000001
859#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
860#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
861#define E1000_GCR_TXD_NO_SNOOP 0x00000008
862#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
863#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
864#define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000
865#define E1000_GCR_CMPL_TMOUT_10ms 0x00001000
866#define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000
867#define E1000_GCR_CAP_VER2 0x00040000
868
869#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
870 E1000_GCR_RXDSCW_NO_SNOOP | \
871 E1000_GCR_RXDSCR_NO_SNOOP | \
872 E1000_GCR_TXD_NO_SNOOP | \
873 E1000_GCR_TXDSCW_NO_SNOOP | \
874 E1000_GCR_TXDSCR_NO_SNOOP)
875
876#define E1000_MMDAC_FUNC_DATA 0x4000
877
878
879#define E1000_MPHY_ADDR_CTL 0x0024
880#define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000
881#define E1000_MPHY_DATA 0x0E10
882
883
884#define E1000_MPHY_PCS_CLK_REG_OFFSET 0x0004
885
886#define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10
887
888
889#define MII_CR_SPEED_SELECT_MSB 0x0040
890#define MII_CR_COLL_TEST_ENABLE 0x0080
891#define MII_CR_FULL_DUPLEX 0x0100
892#define MII_CR_RESTART_AUTO_NEG 0x0200
893#define MII_CR_ISOLATE 0x0400
894#define MII_CR_POWER_DOWN 0x0800
895#define MII_CR_AUTO_NEG_EN 0x1000
896#define MII_CR_SPEED_SELECT_LSB 0x2000
897#define MII_CR_LOOPBACK 0x4000
898#define MII_CR_RESET 0x8000
899#define MII_CR_SPEED_1000 0x0040
900#define MII_CR_SPEED_100 0x2000
901#define MII_CR_SPEED_10 0x0000
902
903
904#define MII_SR_EXTENDED_CAPS 0x0001
905#define MII_SR_JABBER_DETECT 0x0002
906#define MII_SR_LINK_STATUS 0x0004
907#define MII_SR_AUTONEG_CAPS 0x0008
908#define MII_SR_REMOTE_FAULT 0x0010
909#define MII_SR_AUTONEG_COMPLETE 0x0020
910#define MII_SR_PREAMBLE_SUPPRESS 0x0040
911#define MII_SR_EXTENDED_STATUS 0x0100
912#define MII_SR_100T2_HD_CAPS 0x0200
913#define MII_SR_100T2_FD_CAPS 0x0400
914#define MII_SR_10T_HD_CAPS 0x0800
915#define MII_SR_10T_FD_CAPS 0x1000
916#define MII_SR_100X_HD_CAPS 0x2000
917#define MII_SR_100X_FD_CAPS 0x4000
918#define MII_SR_100T4_CAPS 0x8000
919
920
921#define NWAY_AR_SELECTOR_FIELD 0x0001
922#define NWAY_AR_10T_HD_CAPS 0x0020
923#define NWAY_AR_10T_FD_CAPS 0x0040
924#define NWAY_AR_100TX_HD_CAPS 0x0080
925#define NWAY_AR_100TX_FD_CAPS 0x0100
926#define NWAY_AR_100T4_CAPS 0x0200
927#define NWAY_AR_PAUSE 0x0400
928#define NWAY_AR_ASM_DIR 0x0800
929#define NWAY_AR_REMOTE_FAULT 0x2000
930#define NWAY_AR_NEXT_PAGE 0x8000
931
932
933#define NWAY_LPAR_SELECTOR_FIELD 0x0000
934#define NWAY_LPAR_10T_HD_CAPS 0x0020
935#define NWAY_LPAR_10T_FD_CAPS 0x0040
936#define NWAY_LPAR_100TX_HD_CAPS 0x0080
937#define NWAY_LPAR_100TX_FD_CAPS 0x0100
938#define NWAY_LPAR_100T4_CAPS 0x0200
939#define NWAY_LPAR_PAUSE 0x0400
940#define NWAY_LPAR_ASM_DIR 0x0800
941#define NWAY_LPAR_REMOTE_FAULT 0x2000
942#define NWAY_LPAR_ACKNOWLEDGE 0x4000
943#define NWAY_LPAR_NEXT_PAGE 0x8000
944
945
946#define NWAY_ER_LP_NWAY_CAPS 0x0001
947#define NWAY_ER_PAGE_RXD 0x0002
948#define NWAY_ER_NEXT_PAGE_CAPS 0x0004
949#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008
950#define NWAY_ER_PAR_DETECT_FAULT 0x0010
951
952
953#define CR_1000T_ASYM_PAUSE 0x0080
954#define CR_1000T_HD_CAPS 0x0100
955#define CR_1000T_FD_CAPS 0x0200
956
957#define CR_1000T_REPEATER_DTE 0x0400
958
959#define CR_1000T_MS_VALUE 0x0800
960
961#define CR_1000T_MS_ENABLE 0x1000
962#define CR_1000T_TEST_MODE_NORMAL 0x0000
963#define CR_1000T_TEST_MODE_1 0x2000
964#define CR_1000T_TEST_MODE_2 0x4000
965#define CR_1000T_TEST_MODE_3 0x6000
966#define CR_1000T_TEST_MODE_4 0x8000
967
968
969#define SR_1000T_IDLE_ERROR_CNT 0x00FF
970#define SR_1000T_ASYM_PAUSE_DIR 0x0100
971#define SR_1000T_LP_HD_CAPS 0x0400
972#define SR_1000T_LP_FD_CAPS 0x0800
973#define SR_1000T_REMOTE_RX_STATUS 0x1000
974#define SR_1000T_LOCAL_RX_STATUS 0x2000
975#define SR_1000T_MS_CONFIG_RES 0x4000
976#define SR_1000T_MS_CONFIG_FAULT 0x8000
977
978#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
979
980
981
982#define PHY_CONTROL 0x00
983#define PHY_STATUS 0x01
984#define PHY_ID1 0x02
985#define PHY_ID2 0x03
986#define PHY_AUTONEG_ADV 0x04
987#define PHY_LP_ABILITY 0x05
988#define PHY_AUTONEG_EXP 0x06
989#define PHY_NEXT_PAGE_TX 0x07
990#define PHY_LP_NEXT_PAGE 0x08
991#define PHY_1000T_CTRL 0x09
992#define PHY_1000T_STATUS 0x0A
993#define PHY_EXT_STATUS 0x0F
994
995#define PHY_CONTROL_LB 0x4000
996
997
998#define E1000_EECD_SK 0x00000001
999#define E1000_EECD_CS 0x00000002
1000#define E1000_EECD_DI 0x00000004
1001#define E1000_EECD_DO 0x00000008
1002#define E1000_EECD_REQ 0x00000040
1003#define E1000_EECD_GNT 0x00000080
1004#define E1000_EECD_PRES 0x00000100
1005#define E1000_EECD_SIZE 0x00000200
1006#define E1000_EECD_BLOCKED 0x00008000
1007#define E1000_EECD_ABORT 0x00010000
1008#define E1000_EECD_TIMEOUT 0x00020000
1009#define E1000_EECD_ERROR_CLR 0x00040000
1010
1011#define E1000_EECD_ADDR_BITS 0x00000400
1012#define E1000_EECD_TYPE 0x00002000
1013#ifndef E1000_NVM_GRANT_ATTEMPTS
1014#define E1000_NVM_GRANT_ATTEMPTS 1000
1015#endif
1016#define E1000_EECD_AUTO_RD 0x00000200
1017#define E1000_EECD_SIZE_EX_MASK 0x00007800
1018#define E1000_EECD_SIZE_EX_SHIFT 11
1019#define E1000_EECD_FLUPD 0x00080000
1020#define E1000_EECD_AUPDEN 0x00100000
1021#define E1000_EECD_SEC1VAL 0x00400000
1022#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
1023#define E1000_EECD_FLUPD_I210 0x00800000
1024#define E1000_EECD_FLUDONE_I210 0x04000000
1025#define E1000_EECD_FLASH_DETECTED_I210 0x00080000
1026#define E1000_EECD_SEC1VAL_I210 0x02000000
1027#define E1000_FLUDONE_ATTEMPTS 20000
1028#define E1000_EERD_EEWR_MAX_COUNT 512
1029#define E1000_I210_FIFO_SEL_RX 0x00
1030#define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i))
1031#define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0)
1032#define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06
1033#define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01
1034
1035#define E1000_I210_FLASH_SECTOR_SIZE 0x1000
1036
1037#define E1000_I210_FW_PTR_MASK 0x7FFF
1038
1039#define E1000_I210_FW_VER_OFFSET 328
1040
1041#define E1000_NVM_RW_REG_DATA 16
1042#define E1000_NVM_RW_REG_DONE 2
1043#define E1000_NVM_RW_REG_START 1
1044#define E1000_NVM_RW_ADDR_SHIFT 2
1045#define E1000_NVM_POLL_WRITE 1
1046#define E1000_NVM_POLL_READ 0
1047#define E1000_FLASH_UPDATES 2000
1048
1049
1050#define NVM_COMPAT 0x0003
1051#define NVM_ID_LED_SETTINGS 0x0004
1052#define NVM_VERSION 0x0005
1053#define NVM_SERDES_AMPLITUDE 0x0006
1054#define NVM_PHY_CLASS_WORD 0x0007
1055#define E1000_I210_NVM_FW_MODULE_PTR 0x0010
1056#define E1000_I350_NVM_FW_MODULE_PTR 0x0051
1057#define NVM_FUTURE_INIT_WORD1 0x0019
1058#define NVM_ETRACK_WORD 0x0042
1059#define NVM_ETRACK_HIWORD 0x0043
1060#define NVM_COMB_VER_OFF 0x0083
1061#define NVM_COMB_VER_PTR 0x003d
1062
1063
1064#define NVM_MAJOR_MASK 0xF000
1065#define NVM_MINOR_MASK 0x0FF0
1066#define NVM_IMAGE_ID_MASK 0x000F
1067#define NVM_COMB_VER_MASK 0x00FF
1068#define NVM_MAJOR_SHIFT 12
1069#define NVM_MINOR_SHIFT 4
1070#define NVM_COMB_VER_SHFT 8
1071#define NVM_VER_INVALID 0xFFFF
1072#define NVM_ETRACK_SHIFT 16
1073#define NVM_ETRACK_VALID 0x8000
1074#define NVM_NEW_DEC_MASK 0x0F00
1075#define NVM_HEX_CONV 16
1076#define NVM_HEX_TENS 10
1077
1078
1079
1080#define E1000_I350_NVM_FW_LOADER_PATCH_PTR_OFFSET 0x01
1081
1082#define E1000_I350_NVM_FW_VER_WORD1_OFFSET 0x04
1083
1084#define E1000_I350_NVM_FW_VER_WORD2_OFFSET 0x05
1085
1086#define E1000_I350_NVM_FW_VER_WORD3_OFFSET 0x06
1087
1088#define E1000_I350_NVM_FW_VER_WORD4_OFFSET 0x07
1089
1090#define NVM_MAC_ADDR 0x0000
1091#define NVM_SUB_DEV_ID 0x000B
1092#define NVM_SUB_VEN_ID 0x000C
1093#define NVM_DEV_ID 0x000D
1094#define NVM_VEN_ID 0x000E
1095#define NVM_INIT_CTRL_2 0x000F
1096#define NVM_INIT_CTRL_4 0x0013
1097#define NVM_LED_1_CFG 0x001C
1098#define NVM_LED_0_2_CFG 0x001F
1099
1100#define NVM_COMPAT_VALID_CSUM 0x0001
1101#define NVM_FUTURE_INIT_WORD1_VALID_CSUM 0x0040
1102
1103#define NVM_INIT_CONTROL2_REG 0x000F
1104#define NVM_INIT_CONTROL3_PORT_B 0x0014
1105#define NVM_INIT_3GIO_3 0x001A
1106#define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020
1107#define NVM_INIT_CONTROL3_PORT_A 0x0024
1108#define NVM_CFG 0x0012
1109#define NVM_ALT_MAC_ADDR_PTR 0x0037
1110#define NVM_CHECKSUM_REG 0x003F
1111#define NVM_COMPATIBILITY_REG_3 0x0003
1112#define NVM_COMPATIBILITY_BIT_MASK 0x8000
1113
1114#define E1000_NVM_CFG_DONE_PORT_0 0x040000
1115#define E1000_NVM_CFG_DONE_PORT_1 0x080000
1116#define E1000_NVM_CFG_DONE_PORT_2 0x100000
1117#define E1000_NVM_CFG_DONE_PORT_3 0x200000
1118
1119#define NVM_82580_LAN_FUNC_OFFSET(a) ((a) ? (0x40 + (0x40 * (a))) : 0)
1120
1121
1122#define NVM_WORD24_COM_MDIO 0x0008
1123#define NVM_WORD24_EXT_MDIO 0x0004
1124
1125#define NVM_WORD24_LNK_MODE_OFFSET 8
1126
1127#define NVM_WORD24_82580_LNK_MODE_OFFSET 4
1128
1129
1130
1131#define NVM_WORD0F_PAUSE_MASK 0x3000
1132#define NVM_WORD0F_PAUSE 0x1000
1133#define NVM_WORD0F_ASM_DIR 0x2000
1134#define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0
1135
1136
1137#define NVM_WORD1A_ASPM_MASK 0x000C
1138
1139
1140#define NVM_COMPAT_LOM 0x0800
1141
1142
1143#define E1000_PBANUM_LENGTH 11
1144
1145
1146#define NVM_SUM 0xBABA
1147
1148
1149#define NVM_PBA_OFFSET_0 8
1150#define NVM_PBA_OFFSET_1 9
1151#define NVM_PBA_PTR_GUARD 0xFAFA
1152#define NVM_RESERVED_WORD 0xFFFF
1153#define NVM_PHY_CLASS_A 0x8000
1154#define NVM_SERDES_AMPLITUDE_MASK 0x000F
1155#define NVM_SIZE_MASK 0x1C00
1156#define NVM_SIZE_SHIFT 10
1157#define NVM_WORD_SIZE_BASE_SHIFT 6
1158#define NVM_SWDPIO_EXT_SHIFT 4
1159
1160
1161#define NVM_READ_OPCODE_MICROWIRE 0x6
1162#define NVM_WRITE_OPCODE_MICROWIRE 0x5
1163#define NVM_ERASE_OPCODE_MICROWIRE 0x7
1164#define NVM_EWEN_OPCODE_MICROWIRE 0x13
1165#define NVM_EWDS_OPCODE_MICROWIRE 0x10
1166
1167
1168#define NVM_MAX_RETRY_SPI 5000
1169#define NVM_READ_OPCODE_SPI 0x03
1170#define NVM_WRITE_OPCODE_SPI 0x02
1171#define NVM_A8_OPCODE_SPI 0x08
1172#define NVM_WREN_OPCODE_SPI 0x06
1173#define NVM_RDSR_OPCODE_SPI 0x05
1174
1175
1176#define NVM_STATUS_RDY_SPI 0x01
1177
1178
1179#define ID_LED_RESERVED_0000 0x0000
1180#define ID_LED_RESERVED_FFFF 0xFFFF
1181#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
1182 (ID_LED_OFF1_OFF2 << 8) | \
1183 (ID_LED_DEF1_DEF2 << 4) | \
1184 (ID_LED_DEF1_DEF2))
1185#define ID_LED_DEF1_DEF2 0x1
1186#define ID_LED_DEF1_ON2 0x2
1187#define ID_LED_DEF1_OFF2 0x3
1188#define ID_LED_ON1_DEF2 0x4
1189#define ID_LED_ON1_ON2 0x5
1190#define ID_LED_ON1_OFF2 0x6
1191#define ID_LED_OFF1_DEF2 0x7
1192#define ID_LED_OFF1_ON2 0x8
1193#define ID_LED_OFF1_OFF2 0x9
1194
1195#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
1196#define IGP_ACTIVITY_LED_ENABLE 0x0300
1197#define IGP_LED3_MODE 0x07000000
1198
1199
1200#define PCIX_COMMAND_REGISTER 0xE6
1201#define PCIX_STATUS_REGISTER_LO 0xE8
1202#define PCIX_STATUS_REGISTER_HI 0xEA
1203#define PCI_HEADER_TYPE_REGISTER 0x0E
1204#define PCIE_LINK_STATUS 0x12
1205#define PCIE_DEVICE_CONTROL2 0x28
1206
1207#define PCIX_COMMAND_MMRBC_MASK 0x000C
1208#define PCIX_COMMAND_MMRBC_SHIFT 0x2
1209#define PCIX_STATUS_HI_MMRBC_MASK 0x0060
1210#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
1211#define PCIX_STATUS_HI_MMRBC_4K 0x3
1212#define PCIX_STATUS_HI_MMRBC_2K 0x2
1213#define PCIX_STATUS_LO_FUNC_MASK 0x7
1214#define PCI_HEADER_TYPE_MULTIFUNC 0x80
1215#define PCIE_LINK_WIDTH_MASK 0x3F0
1216#define PCIE_LINK_WIDTH_SHIFT 4
1217#define PCIE_LINK_SPEED_MASK 0x0F
1218#define PCIE_LINK_SPEED_2500 0x01
1219#define PCIE_LINK_SPEED_5000 0x02
1220#define PCIE_DEVICE_CONTROL2_16ms 0x0005
1221
1222#define ETH_ADDR_LEN 6
1223
1224#define PHY_REVISION_MASK 0xFFFFFFF0
1225#define MAX_PHY_REG_ADDRESS 0x1F
1226#define MAX_PHY_MULTI_PAGE_REG 0xF
1227
1228
1229
1230
1231
1232#define M88E1000_E_PHY_ID 0x01410C50
1233#define M88E1000_I_PHY_ID 0x01410C30
1234#define M88E1011_I_PHY_ID 0x01410C20
1235#define IGP01E1000_I_PHY_ID 0x02A80380
1236#define M88E1111_I_PHY_ID 0x01410CC0
1237#define M88E1543_E_PHY_ID 0x01410EA0
1238#define M88E1512_E_PHY_ID 0x01410DD0
1239#define M88E1112_E_PHY_ID 0x01410C90
1240#define I347AT4_E_PHY_ID 0x01410DC0
1241#define M88E1340M_E_PHY_ID 0x01410DF0
1242#define GG82563_E_PHY_ID 0x01410CA0
1243#define IGP03E1000_E_PHY_ID 0x02A80390
1244#define IFE_E_PHY_ID 0x02A80330
1245#define IFE_PLUS_E_PHY_ID 0x02A80320
1246#define IFE_C_E_PHY_ID 0x02A80310
1247#define BME1000_E_PHY_ID 0x01410CB0
1248#define BME1000_E_PHY_ID_R2 0x01410CB1
1249#define I82577_E_PHY_ID 0x01540050
1250#define I82578_E_PHY_ID 0x004DD040
1251#define I82579_E_PHY_ID 0x01540090
1252#define I217_E_PHY_ID 0x015400A0
1253#define I82580_I_PHY_ID 0x015403A0
1254#define I350_I_PHY_ID 0x015403B0
1255#define I210_I_PHY_ID 0x01410C00
1256#define IGP04E1000_E_PHY_ID 0x02A80391
1257#define BCM54616_E_PHY_ID 0x03625D10
1258#define M88_VENDOR 0x0141
1259
1260
1261#define M88E1000_PHY_SPEC_CTRL 0x10
1262#define M88E1000_PHY_SPEC_STATUS 0x11
1263#define M88E1000_EXT_PHY_SPEC_CTRL 0x14
1264#define M88E1000_RX_ERR_CNTR 0x15
1265
1266#define M88E1000_PHY_EXT_CTRL 0x1A
1267#define M88E1000_PHY_PAGE_SELECT 0x1D
1268#define M88E1000_PHY_GEN_CONTROL 0x1E
1269#define M88E1000_PHY_VCO_REG_BIT8 0x100
1270#define M88E1000_PHY_VCO_REG_BIT11 0x800
1271
1272
1273#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002
1274
1275#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000
1276#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020
1277
1278#define M88E1000_PSCR_AUTO_X_1000T 0x0040
1279
1280#define M88E1000_PSCR_AUTO_X_MODE 0x0060
1281#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800
1282
1283
1284#define M88E1000_PSSR_REV_POLARITY 0x0002
1285#define M88E1000_PSSR_DOWNSHIFT 0x0020
1286#define M88E1000_PSSR_MDIX 0x0040
1287
1288
1289
1290
1291
1292
1293#define M88E1000_PSSR_CABLE_LENGTH 0x0380
1294#define M88E1000_PSSR_LINK 0x0400
1295#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800
1296#define M88E1000_PSSR_DPLX 0x2000
1297#define M88E1000_PSSR_SPEED 0xC000
1298#define M88E1000_PSSR_100MBS 0x4000
1299#define M88E1000_PSSR_1000MBS 0x8000
1300
1301#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
1302
1303
1304
1305
1306#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
1307#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
1308
1309
1310
1311#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
1312#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
1313#define M88E1000_EPSCR_TX_CLK_25 0x0070
1314
1315
1316#define I347AT4_PCDL 0x10
1317#define I347AT4_PCDC 0x15
1318#define I347AT4_PAGE_SELECT 0x16
1319
1320
1321
1322
1323
1324
1325#define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800
1326#define I347AT4_PSCR_DOWNSHIFT_MASK 0x7000
1327#define I347AT4_PSCR_DOWNSHIFT_1X 0x0000
1328#define I347AT4_PSCR_DOWNSHIFT_2X 0x1000
1329#define I347AT4_PSCR_DOWNSHIFT_3X 0x2000
1330#define I347AT4_PSCR_DOWNSHIFT_4X 0x3000
1331#define I347AT4_PSCR_DOWNSHIFT_5X 0x4000
1332#define I347AT4_PSCR_DOWNSHIFT_6X 0x5000
1333#define I347AT4_PSCR_DOWNSHIFT_7X 0x6000
1334#define I347AT4_PSCR_DOWNSHIFT_8X 0x7000
1335
1336
1337#define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400
1338
1339
1340#define M88E1112_VCT_DSP_DISTANCE 0x001A
1341
1342
1343#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
1344#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
1345
1346#define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020
1347#define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C
1348
1349
1350#define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800
1351
1352
1353
1354
1355
1356#define GG82563_PAGE_SHIFT 5
1357#define GG82563_REG(page, reg) \
1358 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
1359#define GG82563_MIN_ALT_REG 30
1360
1361
1362#define GG82563_PHY_SPEC_CTRL GG82563_REG(0, 16)
1363#define GG82563_PHY_PAGE_SELECT GG82563_REG(0, 22)
1364#define GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26)
1365#define GG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29)
1366
1367
1368#define GG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21)
1369
1370#define GG82563_PHY_DSP_DISTANCE GG82563_REG(5, 26)
1371
1372
1373
1374#define GG82563_PHY_KMRN_MODE_CTRL GG82563_REG(193, 16)
1375#define GG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20)
1376
1377
1378#define GG82563_PHY_INBAND_CTRL GG82563_REG(194, 18)
1379
1380
1381#define E1000_MDIC_REG_MASK 0x001F0000
1382#define E1000_MDIC_REG_SHIFT 16
1383#define E1000_MDIC_PHY_MASK 0x03E00000
1384#define E1000_MDIC_PHY_SHIFT 21
1385#define E1000_MDIC_OP_WRITE 0x04000000
1386#define E1000_MDIC_OP_READ 0x08000000
1387#define E1000_MDIC_READY 0x10000000
1388#define E1000_MDIC_ERROR 0x40000000
1389#define E1000_MDIC_DEST 0x80000000
1390
1391#define E1000_VFTA_BLOCK_SIZE 8
1392
1393#define E1000_GEN_CTL_READY 0x80000000
1394#define E1000_GEN_CTL_ADDRESS_SHIFT 8
1395#define E1000_GEN_POLL_TIMEOUT 640
1396
1397
1398#define E1000_LSECTXCAP_SUM_MASK 0x00FF0000
1399#define E1000_LSECTXCAP_SUM_SHIFT 16
1400#define E1000_LSECRXCAP_SUM_MASK 0x00FF0000
1401#define E1000_LSECRXCAP_SUM_SHIFT 16
1402
1403#define E1000_LSECTXCTRL_EN_MASK 0x00000003
1404#define E1000_LSECTXCTRL_DISABLE 0x0
1405#define E1000_LSECTXCTRL_AUTH 0x1
1406#define E1000_LSECTXCTRL_AUTH_ENCRYPT 0x2
1407#define E1000_LSECTXCTRL_AISCI 0x00000020
1408#define E1000_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00
1409#define E1000_LSECTXCTRL_RSV_MASK 0x000000D8
1410
1411#define E1000_LSECRXCTRL_EN_MASK 0x0000000C
1412#define E1000_LSECRXCTRL_EN_SHIFT 2
1413#define E1000_LSECRXCTRL_DISABLE 0x0
1414#define E1000_LSECRXCTRL_CHECK 0x1
1415#define E1000_LSECRXCTRL_STRICT 0x2
1416#define E1000_LSECRXCTRL_DROP 0x3
1417#define E1000_LSECRXCTRL_PLSH 0x00000040
1418#define E1000_LSECRXCTRL_RP 0x00000080
1419#define E1000_LSECRXCTRL_RSV_MASK 0xFFFFFF33
1420
1421
1422#define E1000_RTTBCNRC_RS_ENA 0x80000000
1423#define E1000_RTTBCNRC_RF_DEC_MASK 0x00003FFF
1424#define E1000_RTTBCNRC_RF_INT_SHIFT 14
1425#define E1000_RTTBCNRC_RF_INT_MASK \
1426 (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT)
1427
1428
1429
1430#define E1000_DMACR_DMACWT_MASK 0x00003FFF
1431
1432#define E1000_DMACR_DMACTHR_MASK 0x00FF0000
1433#define E1000_DMACR_DMACTHR_SHIFT 16
1434
1435#define E1000_DMACR_DMAC_LX_MASK 0x30000000
1436#define E1000_DMACR_DMAC_LX_SHIFT 28
1437#define E1000_DMACR_DMAC_EN 0x80000000
1438
1439#define E1000_DMACR_DC_BMC2OSW_EN 0x00008000
1440
1441
1442#define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF
1443
1444#define E1000_DMCTLX_TTLX_MASK 0x00000FFF
1445
1446
1447#define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF
1448
1449#define E1000_DMCRTRH_LRPRCW 0x80000000
1450
1451
1452#define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF
1453
1454
1455#define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0
1456#define E1000_FCRTC_RTH_COAL_SHIFT 4
1457
1458#define E1000_PCIEMISC_LX_DECISION 0x00000080
1459
1460#define E1000_RXPBS_CFG_TS_EN 0x80000000
1461#define E1000_RXPBS_SIZE_I210_MASK 0x0000003F
1462#define E1000_TXPB0S_SIZE_I210_MASK 0x0000003F
1463#define I210_RXPBSIZE_DEFAULT 0x000000A2
1464#define I210_TXPBSIZE_DEFAULT 0x04000014
1465
1466
1467
1468#define E1000_PROXYFC_D0 0x00000001
1469#define E1000_PROXYFC_EX 0x00000004
1470#define E1000_PROXYFC_MC 0x00000008
1471#define E1000_PROXYFC_BC 0x00000010
1472#define E1000_PROXYFC_ARP_DIRECTED 0x00000020
1473#define E1000_PROXYFC_IPV4 0x00000040
1474#define E1000_PROXYFC_IPV6 0x00000080
1475#define E1000_PROXYFC_NS 0x00000200
1476#define E1000_PROXYFC_ARP 0x00000800
1477
1478#define E1000_PROXYS_CLEAR 0xFFFFFFFF
1479
1480
1481#define E1000_FWSTS_FWRI 0x80000000
1482
1483#define E1000_VTCTRL_RST 0x04000000
1484
1485#define E1000_STATUS_LAN_ID_MASK 0x00000000C
1486
1487#define E1000_STATUS_LAN_ID_OFFSET 2
1488#define E1000_VFTA_ENTRIES 128
1489
1490#define E1000_UNUSEDARG
1491#define ERROR_REPORT(fmt) do { } while (0)
1492#endif
1493