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4#ifndef _IONIC_IF_H_
5#define _IONIC_IF_H_
6
7#define IONIC_DEV_INFO_SIGNATURE 0x44455649
8#define IONIC_DEV_INFO_VERSION 1
9#define IONIC_IFNAMSIZ 16
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12
13
14enum ionic_cmd_opcode {
15 IONIC_CMD_NOP = 0,
16
17
18 IONIC_CMD_IDENTIFY = 1,
19 IONIC_CMD_INIT = 2,
20 IONIC_CMD_RESET = 3,
21 IONIC_CMD_GETATTR = 4,
22 IONIC_CMD_SETATTR = 5,
23
24
25 IONIC_CMD_PORT_IDENTIFY = 10,
26 IONIC_CMD_PORT_INIT = 11,
27 IONIC_CMD_PORT_RESET = 12,
28 IONIC_CMD_PORT_GETATTR = 13,
29 IONIC_CMD_PORT_SETATTR = 14,
30
31
32 IONIC_CMD_LIF_IDENTIFY = 20,
33 IONIC_CMD_LIF_INIT = 21,
34 IONIC_CMD_LIF_RESET = 22,
35 IONIC_CMD_LIF_GETATTR = 23,
36 IONIC_CMD_LIF_SETATTR = 24,
37
38 IONIC_CMD_RX_MODE_SET = 30,
39 IONIC_CMD_RX_FILTER_ADD = 31,
40 IONIC_CMD_RX_FILTER_DEL = 32,
41
42
43 IONIC_CMD_Q_IDENTIFY = 39,
44 IONIC_CMD_Q_INIT = 40,
45 IONIC_CMD_Q_CONTROL = 41,
46
47
48 IONIC_CMD_RDMA_RESET_LIF = 50,
49 IONIC_CMD_RDMA_CREATE_EQ = 51,
50 IONIC_CMD_RDMA_CREATE_CQ = 52,
51 IONIC_CMD_RDMA_CREATE_ADMINQ = 53,
52
53
54 IONIC_CMD_VF_GETATTR = 60,
55 IONIC_CMD_VF_SETATTR = 61,
56
57
58 IONIC_CMD_QOS_CLASS_IDENTIFY = 240,
59 IONIC_CMD_QOS_CLASS_INIT = 241,
60 IONIC_CMD_QOS_CLASS_RESET = 242,
61 IONIC_CMD_QOS_CLASS_UPDATE = 243,
62 IONIC_CMD_QOS_CLEAR_STATS = 244,
63 IONIC_CMD_QOS_RESET = 245,
64
65
66 IONIC_CMD_FW_DOWNLOAD = 254,
67 IONIC_CMD_FW_CONTROL = 255,
68};
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71
72
73enum ionic_status_code {
74 IONIC_RC_SUCCESS = 0,
75 IONIC_RC_EVERSION = 1,
76 IONIC_RC_EOPCODE = 2,
77 IONIC_RC_EIO = 3,
78 IONIC_RC_EPERM = 4,
79 IONIC_RC_EQID = 5,
80 IONIC_RC_EQTYPE = 6,
81 IONIC_RC_ENOENT = 7,
82 IONIC_RC_EINTR = 8,
83 IONIC_RC_EAGAIN = 9,
84 IONIC_RC_ENOMEM = 10,
85 IONIC_RC_EFAULT = 11,
86 IONIC_RC_EBUSY = 12,
87 IONIC_RC_EEXIST = 13,
88 IONIC_RC_EINVAL = 14,
89 IONIC_RC_ENOSPC = 15,
90 IONIC_RC_ERANGE = 16,
91 IONIC_RC_BAD_ADDR = 17,
92 IONIC_RC_DEV_CMD = 18,
93 IONIC_RC_ENOSUPP = 19,
94 IONIC_RC_ERROR = 29,
95 IONIC_RC_ERDMA = 30,
96 IONIC_RC_EVFID = 31,
97};
98
99enum ionic_notifyq_opcode {
100 IONIC_EVENT_LINK_CHANGE = 1,
101 IONIC_EVENT_RESET = 2,
102 IONIC_EVENT_HEARTBEAT = 3,
103 IONIC_EVENT_LOG = 4,
104 IONIC_EVENT_XCVR = 5,
105};
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113struct ionic_admin_cmd {
114 u8 opcode;
115 u8 rsvd;
116 __le16 lif_index;
117 u8 cmd_data[60];
118};
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128struct ionic_admin_comp {
129 u8 status;
130 u8 rsvd;
131 __le16 comp_index;
132 u8 cmd_data[11];
133 u8 color;
134#define IONIC_COMP_COLOR_MASK 0x80
135};
136
137static inline u8 color_match(u8 color, u8 done_color)
138{
139 return (!!(color & IONIC_COMP_COLOR_MASK)) == done_color;
140}
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145
146struct ionic_nop_cmd {
147 u8 opcode;
148 u8 rsvd[63];
149};
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155struct ionic_nop_comp {
156 u8 status;
157 u8 rsvd[15];
158};
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165struct ionic_dev_init_cmd {
166 u8 opcode;
167 u8 type;
168 u8 rsvd[62];
169};
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175struct ionic_dev_init_comp {
176 u8 status;
177 u8 rsvd[15];
178};
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184struct ionic_dev_reset_cmd {
185 u8 opcode;
186 u8 rsvd[63];
187};
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193struct ionic_dev_reset_comp {
194 u8 status;
195 u8 rsvd[15];
196};
197
198#define IONIC_IDENTITY_VERSION_1 1
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205struct ionic_dev_identify_cmd {
206 u8 opcode;
207 u8 ver;
208 u8 rsvd[62];
209};
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216struct ionic_dev_identify_comp {
217 u8 status;
218 u8 ver;
219 u8 rsvd[14];
220};
221
222enum ionic_os_type {
223 IONIC_OS_TYPE_LINUX = 1,
224 IONIC_OS_TYPE_WIN = 2,
225 IONIC_OS_TYPE_DPDK = 3,
226 IONIC_OS_TYPE_FREEBSD = 4,
227 IONIC_OS_TYPE_IPXE = 5,
228 IONIC_OS_TYPE_ESXI = 6,
229};
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239
240union ionic_drv_identity {
241 struct {
242 __le32 os_type;
243 __le32 os_dist;
244 char os_dist_str[128];
245 __le32 kernel_ver;
246 char kernel_ver_str[32];
247 char driver_ver_str[32];
248 };
249 __le32 words[478];
250};
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270union ionic_dev_identity {
271 struct {
272 u8 version;
273 u8 type;
274 u8 rsvd[2];
275 u8 nports;
276 u8 rsvd2[3];
277 __le32 nlifs;
278 __le32 nintrs;
279 __le32 ndbpgs_per_lif;
280 __le32 intr_coal_mult;
281 __le32 intr_coal_div;
282 __le32 eq_count;
283 };
284 __le32 words[478];
285};
286
287enum ionic_lif_type {
288 IONIC_LIF_TYPE_CLASSIC = 0,
289 IONIC_LIF_TYPE_MACVLAN = 1,
290 IONIC_LIF_TYPE_NETQUEUE = 2,
291};
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299struct ionic_lif_identify_cmd {
300 u8 opcode;
301 u8 type;
302 u8 ver;
303 u8 rsvd[61];
304};
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311struct ionic_lif_identify_comp {
312 u8 status;
313 u8 ver;
314 u8 rsvd2[14];
315};
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322enum ionic_lif_capability {
323 IONIC_LIF_CAP_ETH = BIT(0),
324 IONIC_LIF_CAP_RDMA = BIT(1),
325};
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336enum ionic_logical_qtype {
337 IONIC_QTYPE_ADMINQ = 0,
338 IONIC_QTYPE_NOTIFYQ = 1,
339 IONIC_QTYPE_RXQ = 2,
340 IONIC_QTYPE_TXQ = 3,
341 IONIC_QTYPE_EQ = 4,
342 IONIC_QTYPE_MAX = 16,
343};
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351struct ionic_lif_logical_qtype {
352 u8 qtype;
353 u8 rsvd[3];
354 __le32 qid_count;
355 __le32 qid_base;
356};
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363
364enum ionic_lif_state {
365 IONIC_LIF_QUIESCE = 0,
366 IONIC_LIF_ENABLE = 1,
367 IONIC_LIF_DISABLE = 2,
368};
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380union ionic_lif_config {
381 struct {
382 u8 state;
383 u8 rsvd[3];
384 char name[IONIC_IFNAMSIZ];
385 __le32 mtu;
386 u8 mac[6];
387 __le16 vlan;
388 __le64 features;
389 __le32 queue_count[IONIC_QTYPE_MAX];
390 } __rte_packed;
391 __le32 words[64];
392};
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426union ionic_lif_identity {
427 struct {
428 __le64 capabilities;
429
430 struct {
431 u8 version;
432 u8 rsvd[3];
433 __le32 max_ucast_filters;
434 __le32 max_mcast_filters;
435 __le16 rss_ind_tbl_sz;
436 __le32 min_frame_size;
437 __le32 max_frame_size;
438 u8 rsvd2[106];
439 union ionic_lif_config config;
440 } __rte_packed eth;
441
442 struct {
443 u8 version;
444 u8 qp_opcodes;
445 u8 admin_opcodes;
446 u8 rsvd;
447 __le32 npts_per_lif;
448 __le32 nmrs_per_lif;
449 __le32 nahs_per_lif;
450 u8 max_stride;
451 u8 cl_stride;
452 u8 pte_stride;
453 u8 rrq_stride;
454 u8 rsq_stride;
455 u8 dcqcn_profiles;
456 u8 rsvd_dimensions[10];
457 struct ionic_lif_logical_qtype aq_qtype;
458 struct ionic_lif_logical_qtype sq_qtype;
459 struct ionic_lif_logical_qtype rq_qtype;
460 struct ionic_lif_logical_qtype cq_qtype;
461 struct ionic_lif_logical_qtype eq_qtype;
462 } __rte_packed rdma;
463 } __rte_packed;
464 __le32 words[478];
465};
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473
474struct ionic_lif_init_cmd {
475 u8 opcode;
476 u8 type;
477 __le16 index;
478 __le32 rsvd;
479 __le64 info_pa;
480 u8 rsvd2[48];
481};
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488struct ionic_lif_init_comp {
489 u8 status;
490 u8 rsvd;
491 __le16 hw_index;
492 u8 rsvd2[12];
493};
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502struct ionic_q_identify_cmd {
503 u8 opcode;
504 u8 rsvd;
505 __le16 lif_type;
506 u8 type;
507 u8 ver;
508 u8 rsvd2[58];
509};
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517struct ionic_q_identify_comp {
518 u8 status;
519 u8 rsvd;
520 __le16 comp_index;
521 u8 ver;
522 u8 rsvd2[11];
523};
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536union ionic_q_identity {
537 struct {
538 u8 version;
539 u8 supported;
540 u8 rsvd[6];
541#define IONIC_QIDENT_F_CQ 0x01
542#define IONIC_QIDENT_F_SG 0x02
543#define IONIC_QIDENT_F_EQ 0x04
544#define IONIC_QIDENT_F_CMB 0x08
545 __le64 features;
546 __le16 desc_sz;
547 __le16 comp_sz;
548 __le16 sg_desc_sz;
549 __le16 max_sg_elems;
550 __le16 sg_desc_stride;
551 };
552 __le32 words[478];
553};
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586struct ionic_q_init_cmd {
587 u8 opcode;
588 u8 rsvd;
589 __le16 lif_index;
590 u8 type;
591 u8 ver;
592 u8 rsvd1[2];
593 __le32 index;
594 __le16 pid;
595 __le16 intr_index;
596 __le16 flags;
597#define IONIC_QINIT_F_IRQ 0x01
598#define IONIC_QINIT_F_ENA 0x02
599#define IONIC_QINIT_F_SG 0x04
600#define IONIC_QINIT_F_EQ 0x08
601#define IONIC_QINIT_F_CMB 0x10
602#define IONIC_QINIT_F_DEBUG 0x80
603 u8 cos;
604 u8 ring_size;
605 __le64 ring_base;
606 __le64 cq_ring_base;
607 __le64 sg_ring_base;
608 u8 rsvd2[20];
609} __rte_packed;
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619struct ionic_q_init_comp {
620 u8 status;
621 u8 rsvd;
622 __le16 comp_index;
623 __le32 hw_index;
624 u8 hw_type;
625 u8 rsvd2[6];
626 u8 color;
627};
628
629
630#define IONIC_ADDR_LEN 52
631#define IONIC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1)
632
633enum ionic_txq_desc_opcode {
634 IONIC_TXQ_DESC_OPCODE_CSUM_NONE = 0,
635 IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL = 1,
636 IONIC_TXQ_DESC_OPCODE_CSUM_HW = 2,
637 IONIC_TXQ_DESC_OPCODE_TSO = 3,
638};
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751struct ionic_txq_desc {
752 __le64 cmd;
753#define IONIC_TXQ_DESC_OPCODE_MASK 0xf
754#define IONIC_TXQ_DESC_OPCODE_SHIFT 4
755#define IONIC_TXQ_DESC_FLAGS_MASK 0xf
756#define IONIC_TXQ_DESC_FLAGS_SHIFT 0
757#define IONIC_TXQ_DESC_NSGE_MASK 0xf
758#define IONIC_TXQ_DESC_NSGE_SHIFT 8
759#define IONIC_TXQ_DESC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1)
760#define IONIC_TXQ_DESC_ADDR_SHIFT 12
761
762
763#define IONIC_TXQ_DESC_FLAG_VLAN 0x1
764#define IONIC_TXQ_DESC_FLAG_ENCAP 0x2
765
766
767#define IONIC_TXQ_DESC_FLAG_CSUM_L3 0x4
768#define IONIC_TXQ_DESC_FLAG_CSUM_L4 0x8
769
770
771#define IONIC_TXQ_DESC_FLAG_TSO_SOT 0x4
772#define IONIC_TXQ_DESC_FLAG_TSO_EOT 0x8
773
774 __le16 len;
775 union {
776 __le16 vlan_tci;
777 __le16 hword0;
778 };
779 union {
780 __le16 csum_start;
781 __le16 hdr_len;
782 __le16 hword1;
783 };
784 union {
785 __le16 csum_offset;
786 __le16 mss;
787 __le16 hword2;
788 };
789};
790
791static inline u64 encode_txq_desc_cmd(u8 opcode, u8 flags,
792 u8 nsge, u64 addr)
793{
794 u64 cmd;
795
796 cmd = (opcode & IONIC_TXQ_DESC_OPCODE_MASK) <<
797 IONIC_TXQ_DESC_OPCODE_SHIFT;
798 cmd |= (flags & IONIC_TXQ_DESC_FLAGS_MASK) <<
799 IONIC_TXQ_DESC_FLAGS_SHIFT;
800 cmd |= (nsge & IONIC_TXQ_DESC_NSGE_MASK) <<
801 IONIC_TXQ_DESC_NSGE_SHIFT;
802 cmd |= (addr & IONIC_TXQ_DESC_ADDR_MASK) <<
803 IONIC_TXQ_DESC_ADDR_SHIFT;
804
805 return cmd;
806};
807
808static inline void
809decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags,
810 u8 *nsge, u64 *addr)
811{
812 *opcode = (cmd >> IONIC_TXQ_DESC_OPCODE_SHIFT) &
813 IONIC_TXQ_DESC_OPCODE_MASK;
814 *flags = (cmd >> IONIC_TXQ_DESC_FLAGS_SHIFT) &
815 IONIC_TXQ_DESC_FLAGS_MASK;
816 *nsge = (cmd >> IONIC_TXQ_DESC_NSGE_SHIFT) &
817 IONIC_TXQ_DESC_NSGE_MASK;
818 *addr = (cmd >> IONIC_TXQ_DESC_ADDR_SHIFT) &
819 IONIC_TXQ_DESC_ADDR_MASK;
820};
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827struct ionic_txq_sg_elem {
828 __le64 addr;
829 __le16 len;
830 __le16 rsvd[3];
831};
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837struct ionic_txq_sg_desc {
838#define IONIC_TX_MAX_SG_ELEMS 8
839#define IONIC_TX_SG_DESC_STRIDE 8
840 struct ionic_txq_sg_elem elems[IONIC_TX_MAX_SG_ELEMS];
841};
842
843struct ionic_txq_sg_desc_v1 {
844#define IONIC_TX_MAX_SG_ELEMS_V1 15
845#define IONIC_TX_SG_DESC_STRIDE_V1 16
846 struct ionic_txq_sg_elem elems[IONIC_TX_SG_DESC_STRIDE_V1];
847};
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855struct ionic_txq_comp {
856 u8 status;
857 u8 rsvd;
858 __le16 comp_index;
859 u8 rsvd2[11];
860 u8 color;
861};
862
863enum ionic_rxq_desc_opcode {
864 IONIC_RXQ_DESC_OPCODE_SIMPLE = 0,
865 IONIC_RXQ_DESC_OPCODE_SG = 1,
866};
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881struct ionic_rxq_desc {
882 u8 opcode;
883 u8 rsvd[5];
884 __le16 len;
885 __le64 addr;
886};
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893struct ionic_rxq_sg_elem {
894 __le64 addr;
895 __le16 len;
896 __le16 rsvd[3];
897};
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903struct ionic_rxq_sg_desc {
904#define IONIC_RX_MAX_SG_ELEMS 8
905#define IONIC_RX_SG_DESC_STRIDE 8
906 struct ionic_rxq_sg_elem elems[IONIC_RX_SG_DESC_STRIDE];
907};
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969struct ionic_rxq_comp {
970 u8 status;
971 u8 num_sg_elems;
972 __le16 comp_index;
973 __le32 rss_hash;
974 __le16 csum;
975 __le16 vlan_tci;
976 __le16 len;
977 u8 csum_flags;
978#define IONIC_RXQ_COMP_CSUM_F_TCP_OK 0x01
979#define IONIC_RXQ_COMP_CSUM_F_TCP_BAD 0x02
980#define IONIC_RXQ_COMP_CSUM_F_UDP_OK 0x04
981#define IONIC_RXQ_COMP_CSUM_F_UDP_BAD 0x08
982#define IONIC_RXQ_COMP_CSUM_F_IP_OK 0x10
983#define IONIC_RXQ_COMP_CSUM_F_IP_BAD 0x20
984#define IONIC_RXQ_COMP_CSUM_F_VLAN 0x40
985#define IONIC_RXQ_COMP_CSUM_F_CALC 0x80
986 u8 pkt_type_color;
987#define IONIC_RXQ_COMP_PKT_TYPE_MASK 0x7f
988};
989
990enum ionic_pkt_type {
991 IONIC_PKT_TYPE_NON_IP = 0x00,
992 IONIC_PKT_TYPE_IPV4 = 0x01,
993 IONIC_PKT_TYPE_IPV4_TCP = 0x03,
994 IONIC_PKT_TYPE_IPV4_UDP = 0x05,
995 IONIC_PKT_TYPE_IPV6 = 0x08,
996 IONIC_PKT_TYPE_IPV6_TCP = 0x18,
997 IONIC_PKT_TYPE_IPV6_UDP = 0x28,
998
999 IONIC_PKT_TYPE_ENCAP_NON_IP = 0x40,
1000 IONIC_PKT_TYPE_ENCAP_IPV4 = 0x41,
1001 IONIC_PKT_TYPE_ENCAP_IPV4_TCP = 0x43,
1002 IONIC_PKT_TYPE_ENCAP_IPV4_UDP = 0x45,
1003 IONIC_PKT_TYPE_ENCAP_IPV6 = 0x48,
1004 IONIC_PKT_TYPE_ENCAP_IPV6_TCP = 0x58,
1005 IONIC_PKT_TYPE_ENCAP_IPV6_UDP = 0x68,
1006};
1007
1008enum ionic_eth_hw_features {
1009 IONIC_ETH_HW_VLAN_TX_TAG = BIT(0),
1010 IONIC_ETH_HW_VLAN_RX_STRIP = BIT(1),
1011 IONIC_ETH_HW_VLAN_RX_FILTER = BIT(2),
1012 IONIC_ETH_HW_RX_HASH = BIT(3),
1013 IONIC_ETH_HW_RX_CSUM = BIT(4),
1014 IONIC_ETH_HW_TX_SG = BIT(5),
1015 IONIC_ETH_HW_RX_SG = BIT(6),
1016 IONIC_ETH_HW_TX_CSUM = BIT(7),
1017 IONIC_ETH_HW_TSO = BIT(8),
1018 IONIC_ETH_HW_TSO_IPV6 = BIT(9),
1019 IONIC_ETH_HW_TSO_ECN = BIT(10),
1020 IONIC_ETH_HW_TSO_GRE = BIT(11),
1021 IONIC_ETH_HW_TSO_GRE_CSUM = BIT(12),
1022 IONIC_ETH_HW_TSO_IPXIP4 = BIT(13),
1023 IONIC_ETH_HW_TSO_IPXIP6 = BIT(14),
1024 IONIC_ETH_HW_TSO_UDP = BIT(15),
1025 IONIC_ETH_HW_TSO_UDP_CSUM = BIT(16),
1026 IONIC_ETH_HW_RX_CSUM_GENEVE = BIT(17),
1027 IONIC_ETH_HW_TX_CSUM_GENEVE = BIT(18),
1028 IONIC_ETH_HW_TSO_GENEVE = BIT(19)
1029};
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1038
1039struct ionic_q_control_cmd {
1040 u8 opcode;
1041 u8 type;
1042 __le16 lif_index;
1043 __le32 index;
1044 u8 oper;
1045 u8 rsvd[55];
1046};
1047
1048typedef struct ionic_admin_comp ionic_q_control_comp;
1049
1050enum ionic_q_control_oper {
1051 IONIC_Q_DISABLE = 0,
1052 IONIC_Q_ENABLE = 1,
1053 IONIC_Q_HANG_RESET = 2,
1054};
1055
1056
1057
1058
1059
1060
1061
1062enum ionic_phy_type {
1063 IONIC_PHY_TYPE_NONE = 0,
1064 IONIC_PHY_TYPE_COPPER = 1,
1065 IONIC_PHY_TYPE_FIBER = 2,
1066};
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076enum ionic_xcvr_state {
1077 IONIC_XCVR_STATE_REMOVED = 0,
1078 IONIC_XCVR_STATE_INSERTED = 1,
1079 IONIC_XCVR_STATE_PENDING = 2,
1080 IONIC_XCVR_STATE_SPROM_READ = 3,
1081 IONIC_XCVR_STATE_SPROM_READ_ERR = 4,
1082};
1083
1084
1085
1086
1087enum ionic_xcvr_pid {
1088 IONIC_XCVR_PID_UNKNOWN = 0,
1089
1090
1091 IONIC_XCVR_PID_QSFP_100G_CR4 = 1,
1092 IONIC_XCVR_PID_QSFP_40GBASE_CR4 = 2,
1093 IONIC_XCVR_PID_SFP_25GBASE_CR_S = 3,
1094 IONIC_XCVR_PID_SFP_25GBASE_CR_L = 4,
1095 IONIC_XCVR_PID_SFP_25GBASE_CR_N = 5,
1096
1097
1098 IONIC_XCVR_PID_QSFP_100G_AOC = 50,
1099 IONIC_XCVR_PID_QSFP_100G_ACC = 51,
1100 IONIC_XCVR_PID_QSFP_100G_SR4 = 52,
1101 IONIC_XCVR_PID_QSFP_100G_LR4 = 53,
1102 IONIC_XCVR_PID_QSFP_100G_ER4 = 54,
1103 IONIC_XCVR_PID_QSFP_40GBASE_ER4 = 55,
1104 IONIC_XCVR_PID_QSFP_40GBASE_SR4 = 56,
1105 IONIC_XCVR_PID_QSFP_40GBASE_LR4 = 57,
1106 IONIC_XCVR_PID_QSFP_40GBASE_AOC = 58,
1107 IONIC_XCVR_PID_SFP_25GBASE_SR = 59,
1108 IONIC_XCVR_PID_SFP_25GBASE_LR = 60,
1109 IONIC_XCVR_PID_SFP_25GBASE_ER = 61,
1110 IONIC_XCVR_PID_SFP_25GBASE_AOC = 62,
1111 IONIC_XCVR_PID_SFP_10GBASE_SR = 63,
1112 IONIC_XCVR_PID_SFP_10GBASE_LR = 64,
1113 IONIC_XCVR_PID_SFP_10GBASE_LRM = 65,
1114 IONIC_XCVR_PID_SFP_10GBASE_ER = 66,
1115 IONIC_XCVR_PID_SFP_10GBASE_AOC = 67,
1116 IONIC_XCVR_PID_SFP_10GBASE_CU = 68,
1117 IONIC_XCVR_PID_QSFP_100G_CWDM4 = 69,
1118 IONIC_XCVR_PID_QSFP_100G_PSM4 = 70,
1119 IONIC_XCVR_PID_SFP_25GBASE_ACC = 71,
1120};
1121
1122
1123
1124
1125
1126
1127
1128enum ionic_port_admin_state {
1129 IONIC_PORT_ADMIN_STATE_NONE = 0,
1130 IONIC_PORT_ADMIN_STATE_DOWN = 1,
1131 IONIC_PORT_ADMIN_STATE_UP = 2,
1132};
1133
1134
1135
1136
1137
1138
1139
1140enum ionic_port_oper_status {
1141 IONIC_PORT_OPER_STATUS_NONE = 0,
1142 IONIC_PORT_OPER_STATUS_UP = 1,
1143 IONIC_PORT_OPER_STATUS_DOWN = 2,
1144};
1145
1146
1147
1148
1149
1150
1151
1152enum ionic_port_fec_type {
1153 IONIC_PORT_FEC_TYPE_NONE = 0,
1154 IONIC_PORT_FEC_TYPE_FC = 1,
1155 IONIC_PORT_FEC_TYPE_RS = 2,
1156};
1157
1158
1159
1160
1161
1162
1163
1164enum ionic_port_pause_type {
1165 IONIC_PORT_PAUSE_TYPE_NONE = 0,
1166 IONIC_PORT_PAUSE_TYPE_LINK = 1,
1167 IONIC_PORT_PAUSE_TYPE_PFC = 2,
1168};
1169
1170
1171
1172
1173
1174
1175
1176enum ionic_port_loopback_mode {
1177 IONIC_PORT_LOOPBACK_MODE_NONE = 0,
1178 IONIC_PORT_LOOPBACK_MODE_MAC = 1,
1179 IONIC_PORT_LOOPBACK_MODE_PHY = 2,
1180};
1181
1182
1183
1184
1185
1186
1187
1188
1189struct ionic_xcvr_status {
1190 u8 state;
1191 u8 phy;
1192 __le16 pid;
1193 u8 sprom[256];
1194};
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206union ionic_port_config {
1207 struct {
1208#define IONIC_SPEED_100G 100000
1209#define IONIC_SPEED_50G 50000
1210#define IONIC_SPEED_40G 40000
1211#define IONIC_SPEED_25G 25000
1212#define IONIC_SPEED_10G 10000
1213#define IONIC_SPEED_1G 1000
1214 __le32 speed;
1215 __le32 mtu;
1216 u8 state;
1217 u8 an_enable;
1218 u8 fec_type;
1219#define IONIC_PAUSE_TYPE_MASK 0x0f
1220#define IONIC_PAUSE_FLAGS_MASK 0xf0
1221#define IONIC_PAUSE_F_TX 0x10
1222#define IONIC_PAUSE_F_RX 0x20
1223 u8 pause_type;
1224 u8 loopback_mode;
1225 };
1226 __le32 words[64];
1227};
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238struct ionic_port_status {
1239 __le32 id;
1240 __le32 speed;
1241 u8 status;
1242 __le16 link_down_count;
1243 u8 fec_type;
1244 u8 rsvd[48];
1245 struct ionic_xcvr_status xcvr;
1246} __rte_packed;
1247
1248
1249
1250
1251
1252
1253
1254struct ionic_port_identify_cmd {
1255 u8 opcode;
1256 u8 index;
1257 u8 ver;
1258 u8 rsvd[61];
1259};
1260
1261
1262
1263
1264
1265
1266struct ionic_port_identify_comp {
1267 u8 status;
1268 u8 ver;
1269 u8 rsvd[14];
1270};
1271
1272
1273
1274
1275
1276
1277
1278struct ionic_port_init_cmd {
1279 u8 opcode;
1280 u8 index;
1281 u8 rsvd[6];
1282 __le64 info_pa;
1283 u8 rsvd2[48];
1284};
1285
1286
1287
1288
1289
1290struct ionic_port_init_comp {
1291 u8 status;
1292 u8 rsvd[15];
1293};
1294
1295
1296
1297
1298
1299
1300struct ionic_port_reset_cmd {
1301 u8 opcode;
1302 u8 index;
1303 u8 rsvd[62];
1304};
1305
1306
1307
1308
1309
1310struct ionic_port_reset_comp {
1311 u8 status;
1312 u8 rsvd[15];
1313};
1314
1315
1316
1317
1318
1319enum ionic_stats_ctl_cmd {
1320 IONIC_STATS_CTL_RESET = 0,
1321};
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334enum ionic_port_attr {
1335 IONIC_PORT_ATTR_STATE = 0,
1336 IONIC_PORT_ATTR_SPEED = 1,
1337 IONIC_PORT_ATTR_MTU = 2,
1338 IONIC_PORT_ATTR_AUTONEG = 3,
1339 IONIC_PORT_ATTR_FEC = 4,
1340 IONIC_PORT_ATTR_PAUSE = 5,
1341 IONIC_PORT_ATTR_LOOPBACK = 6,
1342 IONIC_PORT_ATTR_STATS_CTRL = 7,
1343};
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359struct ionic_port_setattr_cmd {
1360 u8 opcode;
1361 u8 index;
1362 u8 attr;
1363 u8 rsvd;
1364 union {
1365 u8 state;
1366 __le32 speed;
1367 __le32 mtu;
1368 u8 an_enable;
1369 u8 fec_type;
1370 u8 pause_type;
1371 u8 loopback_mode;
1372 u8 stats_ctl;
1373 u8 rsvd2[60];
1374 };
1375};
1376
1377
1378
1379
1380
1381
1382struct ionic_port_setattr_comp {
1383 u8 status;
1384 u8 rsvd[14];
1385 u8 color;
1386};
1387
1388
1389
1390
1391
1392
1393
1394struct ionic_port_getattr_cmd {
1395 u8 opcode;
1396 u8 index;
1397 u8 attr;
1398 u8 rsvd[61];
1399};
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413struct ionic_port_getattr_comp {
1414 u8 status;
1415 u8 rsvd[3];
1416 union {
1417 u8 state;
1418 __le32 speed;
1419 __le32 mtu;
1420 u8 an_enable;
1421 u8 fec_type;
1422 u8 pause_type;
1423 u8 loopback_mode;
1424 u8 rsvd2[11];
1425 } __rte_packed;
1426 u8 color;
1427};
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437struct ionic_lif_status {
1438 __le64 eid;
1439 u8 port_num;
1440 u8 rsvd;
1441 __le16 link_status;
1442 __le32 link_speed;
1443 __le16 link_down_count;
1444 u8 rsvd2[46];
1445};
1446
1447
1448
1449
1450
1451
1452struct ionic_lif_reset_cmd {
1453 u8 opcode;
1454 u8 rsvd;
1455 __le16 index;
1456 __le32 rsvd2[15];
1457};
1458
1459typedef struct ionic_admin_comp ionic_lif_reset_comp;
1460
1461enum ionic_dev_state {
1462 IONIC_DEV_DISABLE = 0,
1463 IONIC_DEV_ENABLE = 1,
1464 IONIC_DEV_HANG_RESET = 2,
1465};
1466
1467
1468
1469
1470
1471
1472
1473enum ionic_dev_attr {
1474 IONIC_DEV_ATTR_STATE = 0,
1475 IONIC_DEV_ATTR_NAME = 1,
1476 IONIC_DEV_ATTR_FEATURES = 2,
1477};
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487struct ionic_dev_setattr_cmd {
1488 u8 opcode;
1489 u8 attr;
1490 __le16 rsvd;
1491 union {
1492 u8 state;
1493 char name[IONIC_IFNAMSIZ];
1494 __le64 features;
1495 u8 rsvd2[60];
1496 } __rte_packed;
1497};
1498
1499
1500
1501
1502
1503
1504
1505struct ionic_dev_setattr_comp {
1506 u8 status;
1507 u8 rsvd[3];
1508 union {
1509 __le64 features;
1510 u8 rsvd2[11];
1511 } __rte_packed;
1512 u8 color;
1513};
1514
1515
1516
1517
1518
1519
1520struct ionic_dev_getattr_cmd {
1521 u8 opcode;
1522 u8 attr;
1523 u8 rsvd[62];
1524};
1525
1526
1527
1528
1529
1530
1531
1532struct ionic_dev_getattr_comp {
1533 u8 status;
1534 u8 rsvd[3];
1535 union {
1536 __le64 features;
1537 u8 rsvd2[11];
1538 } __rte_packed;
1539 u8 color;
1540};
1541
1542
1543
1544
1545#define IONIC_RSS_HASH_KEY_SIZE 40
1546
1547enum ionic_rss_hash_types {
1548 IONIC_RSS_TYPE_IPV4 = BIT(0),
1549 IONIC_RSS_TYPE_IPV4_TCP = BIT(1),
1550 IONIC_RSS_TYPE_IPV4_UDP = BIT(2),
1551 IONIC_RSS_TYPE_IPV6 = BIT(3),
1552 IONIC_RSS_TYPE_IPV6_TCP = BIT(4),
1553 IONIC_RSS_TYPE_IPV6_UDP = BIT(5),
1554};
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566enum ionic_lif_attr {
1567 IONIC_LIF_ATTR_STATE = 0,
1568 IONIC_LIF_ATTR_NAME = 1,
1569 IONIC_LIF_ATTR_MTU = 2,
1570 IONIC_LIF_ATTR_MAC = 3,
1571 IONIC_LIF_ATTR_FEATURES = 4,
1572 IONIC_LIF_ATTR_RSS = 5,
1573 IONIC_LIF_ATTR_STATS_CTRL = 6,
1574};
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592struct ionic_lif_setattr_cmd {
1593 u8 opcode;
1594 u8 attr;
1595 __le16 index;
1596 union {
1597 u8 state;
1598 char name[IONIC_IFNAMSIZ];
1599 __le32 mtu;
1600 u8 mac[6];
1601 __le64 features;
1602 struct {
1603 __le16 types;
1604 u8 key[IONIC_RSS_HASH_KEY_SIZE];
1605 u8 rsvd[6];
1606 __le64 addr;
1607 } rss;
1608 u8 stats_ctl;
1609 u8 rsvd[60];
1610 } __rte_packed;
1611};
1612
1613
1614
1615
1616
1617
1618
1619
1620struct ionic_lif_setattr_comp {
1621 u8 status;
1622 u8 rsvd;
1623 __le16 comp_index;
1624 union {
1625 __le64 features;
1626 u8 rsvd2[11];
1627 } __rte_packed;
1628 u8 color;
1629};
1630
1631
1632
1633
1634
1635
1636
1637struct ionic_lif_getattr_cmd {
1638 u8 opcode;
1639 u8 attr;
1640 __le16 index;
1641 u8 rsvd[60];
1642};
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655struct ionic_lif_getattr_comp {
1656 u8 status;
1657 u8 rsvd;
1658 __le16 comp_index;
1659 union {
1660 u8 state;
1661 __le32 mtu;
1662 u8 mac[6];
1663 __le64 features;
1664 u8 rsvd2[11];
1665 } __rte_packed;
1666 u8 color;
1667};
1668
1669enum ionic_rx_mode {
1670 IONIC_RX_MODE_F_UNICAST = BIT(0),
1671 IONIC_RX_MODE_F_MULTICAST = BIT(1),
1672 IONIC_RX_MODE_F_BROADCAST = BIT(2),
1673 IONIC_RX_MODE_F_PROMISC = BIT(3),
1674 IONIC_RX_MODE_F_ALLMULTI = BIT(4),
1675 IONIC_RX_MODE_F_RDMA_SNIFFER = BIT(5),
1676};
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690struct ionic_rx_mode_set_cmd {
1691 u8 opcode;
1692 u8 rsvd;
1693 __le16 lif_index;
1694 __le16 rx_mode;
1695 __le16 rsvd2[29];
1696};
1697
1698typedef struct ionic_admin_comp ionic_rx_mode_set_comp;
1699
1700enum ionic_rx_filter_match_type {
1701 IONIC_RX_FILTER_MATCH_VLAN = 0,
1702 IONIC_RX_FILTER_MATCH_MAC,
1703 IONIC_RX_FILTER_MATCH_MAC_VLAN,
1704};
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721struct ionic_rx_filter_add_cmd {
1722 u8 opcode;
1723 u8 qtype;
1724 __le16 lif_index;
1725 __le32 qid;
1726 __le16 match;
1727 union {
1728 struct {
1729 __le16 vlan;
1730 } vlan;
1731 struct {
1732 u8 addr[6];
1733 } mac;
1734 struct {
1735 __le16 vlan;
1736 u8 addr[6];
1737 } mac_vlan;
1738 u8 rsvd[54];
1739 };
1740};
1741
1742
1743
1744
1745
1746
1747
1748
1749struct ionic_rx_filter_add_comp {
1750 u8 status;
1751 u8 rsvd;
1752 __le16 comp_index;
1753 __le32 filter_id;
1754 u8 rsvd2[7];
1755 u8 color;
1756};
1757
1758
1759
1760
1761
1762
1763
1764struct ionic_rx_filter_del_cmd {
1765 u8 opcode;
1766 u8 rsvd;
1767 __le16 lif_index;
1768 __le32 filter_id;
1769 u8 rsvd2[56];
1770};
1771
1772typedef struct ionic_admin_comp ionic_rx_filter_del_comp;
1773
1774enum ionic_vf_attr {
1775 IONIC_VF_ATTR_SPOOFCHK = 1,
1776 IONIC_VF_ATTR_TRUST = 2,
1777 IONIC_VF_ATTR_MAC = 3,
1778 IONIC_VF_ATTR_LINKSTATE = 4,
1779 IONIC_VF_ATTR_VLAN = 5,
1780 IONIC_VF_ATTR_RATE = 6,
1781 IONIC_VF_ATTR_STATSADDR = 7,
1782};
1783
1784
1785
1786
1787
1788
1789
1790enum ionic_vf_link_status {
1791 IONIC_VF_LINK_STATUS_AUTO = 0,
1792 IONIC_VF_LINK_STATUS_UP = 1,
1793 IONIC_VF_LINK_STATUS_DOWN = 2,
1794};
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809struct ionic_vf_setattr_cmd {
1810 u8 opcode;
1811 u8 attr;
1812 __le16 vf_index;
1813 union {
1814 u8 macaddr[6];
1815 __le16 vlanid;
1816 __le32 maxrate;
1817 u8 spoofchk;
1818 u8 trust;
1819 u8 linkstate;
1820 __le64 stats_pa;
1821 u8 pad[60];
1822 } __rte_packed;
1823};
1824
1825struct ionic_vf_setattr_comp {
1826 u8 status;
1827 u8 attr;
1828 __le16 vf_index;
1829 __le16 comp_index;
1830 u8 rsvd[9];
1831 u8 color;
1832};
1833
1834
1835
1836
1837
1838
1839
1840struct ionic_vf_getattr_cmd {
1841 u8 opcode;
1842 u8 attr;
1843 __le16 vf_index;
1844 u8 rsvd[60];
1845};
1846
1847struct ionic_vf_getattr_comp {
1848 u8 status;
1849 u8 attr;
1850 __le16 vf_index;
1851 union {
1852 u8 macaddr[6];
1853 __le16 vlanid;
1854 __le32 maxrate;
1855 u8 spoofchk;
1856 u8 trust;
1857 u8 linkstate;
1858 __le64 stats_pa;
1859 u8 pad[11];
1860 } __rte_packed;
1861 u8 color;
1862};
1863
1864
1865
1866
1867
1868
1869
1870struct ionic_qos_identify_cmd {
1871 u8 opcode;
1872 u8 ver;
1873 u8 rsvd[62];
1874};
1875
1876
1877
1878
1879
1880
1881struct ionic_qos_identify_comp {
1882 u8 status;
1883 u8 ver;
1884 u8 rsvd[14];
1885};
1886
1887#define IONIC_QOS_TC_MAX 8
1888#define IONIC_QOS_ALL_TC 0xFF
1889
1890#define IONIC_QOS_CLASS_MAX 7
1891#define IONIC_QOS_PCP_MAX 8
1892#define IONIC_QOS_CLASS_NAME_SZ 32
1893#define IONIC_QOS_DSCP_MAX 64
1894#define IONIC_QOS_ALL_PCP 0xFF
1895#define IONIC_DSCP_BLOCK_SIZE 8
1896
1897
1898
1899
1900enum ionic_qos_class {
1901 IONIC_QOS_CLASS_DEFAULT = 0,
1902 IONIC_QOS_CLASS_USER_DEFINED_1 = 1,
1903 IONIC_QOS_CLASS_USER_DEFINED_2 = 2,
1904 IONIC_QOS_CLASS_USER_DEFINED_3 = 3,
1905 IONIC_QOS_CLASS_USER_DEFINED_4 = 4,
1906 IONIC_QOS_CLASS_USER_DEFINED_5 = 5,
1907 IONIC_QOS_CLASS_USER_DEFINED_6 = 6,
1908};
1909
1910
1911
1912
1913
1914
1915
1916enum ionic_qos_class_type {
1917 IONIC_QOS_CLASS_TYPE_NONE = 0,
1918 IONIC_QOS_CLASS_TYPE_PCP = 1,
1919 IONIC_QOS_CLASS_TYPE_DSCP = 2,
1920};
1921
1922
1923
1924
1925
1926
1927enum ionic_qos_sched_type {
1928 IONIC_QOS_SCHED_TYPE_STRICT = 0,
1929 IONIC_QOS_SCHED_TYPE_DWRR = 1,
1930};
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954union ionic_qos_config {
1955 struct {
1956#define IONIC_QOS_CONFIG_F_ENABLE BIT(0)
1957#define IONIC_QOS_CONFIG_F_NO_DROP BIT(1)
1958
1959#define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP BIT(2)
1960#define IONIC_QOS_CONFIG_F_RW_IP_DSCP BIT(3)
1961
1962#define IONIC_QOS_CONFIG_F_NON_DISRUPTIVE BIT(4)
1963 u8 flags;
1964 u8 sched_type;
1965 u8 class_type;
1966 u8 pause_type;
1967 char name[IONIC_QOS_CLASS_NAME_SZ];
1968 __le32 mtu;
1969
1970 u8 pfc_cos;
1971
1972 union {
1973 u8 dwrr_weight;
1974 __le64 strict_rlmt;
1975 };
1976
1977
1978 union {
1979 u8 rw_dot1q_pcp;
1980 u8 rw_ip_dscp;
1981 };
1982
1983 union {
1984 u8 dot1q_pcp;
1985 struct {
1986 u8 ndscp;
1987 u8 ip_dscp[IONIC_QOS_DSCP_MAX];
1988 };
1989 };
1990 } __rte_packed;
1991 __le32 words[64];
1992};
1993
1994
1995
1996
1997
1998
1999
2000
2001union ionic_qos_identity {
2002 struct {
2003 u8 version;
2004 u8 type;
2005 u8 rsvd[62];
2006 union ionic_qos_config config[IONIC_QOS_CLASS_MAX];
2007 };
2008 __le32 words[478];
2009};
2010
2011
2012
2013
2014
2015
2016
2017struct ionic_qos_init_cmd {
2018 u8 opcode;
2019 u8 group;
2020 u8 rsvd[6];
2021 __le64 info_pa;
2022 u8 rsvd1[48];
2023};
2024
2025typedef struct ionic_admin_comp ionic_qos_init_comp;
2026
2027
2028
2029
2030
2031
2032struct ionic_qos_reset_cmd {
2033 u8 opcode;
2034 u8 group;
2035 u8 rsvd[62];
2036};
2037
2038
2039
2040
2041
2042struct ionic_qos_clear_stats_cmd {
2043 u8 opcode;
2044 u8 group_bitmap;
2045 u8 rsvd[62];
2046};
2047
2048typedef struct ionic_admin_comp ionic_qos_reset_comp;
2049
2050
2051
2052
2053
2054
2055
2056
2057struct ionic_fw_download_cmd {
2058 u8 opcode;
2059 u8 rsvd[3];
2060 __le32 offset;
2061 __le64 addr;
2062 __le32 length;
2063};
2064
2065typedef struct ionic_admin_comp ionic_fw_download_comp;
2066
2067
2068
2069
2070
2071
2072
2073enum ionic_fw_control_oper {
2074 IONIC_FW_RESET = 0,
2075 IONIC_FW_INSTALL = 1,
2076 IONIC_FW_ACTIVATE = 2,
2077};
2078
2079
2080
2081
2082
2083
2084
2085struct ionic_fw_control_cmd {
2086 u8 opcode;
2087 u8 rsvd[3];
2088 u8 oper;
2089 u8 slot;
2090 u8 rsvd1[58];
2091};
2092
2093
2094
2095
2096
2097
2098
2099
2100struct ionic_fw_control_comp {
2101 u8 status;
2102 u8 rsvd;
2103 __le16 comp_index;
2104 u8 slot;
2105 u8 rsvd1[10];
2106 u8 color;
2107};
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122struct ionic_rdma_reset_cmd {
2123 u8 opcode;
2124 u8 rsvd;
2125 __le16 lif_index;
2126 u8 rsvd2[60];
2127};
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157struct ionic_rdma_queue_cmd {
2158 u8 opcode;
2159 u8 rsvd;
2160 __le16 lif_index;
2161 __le32 qid_ver;
2162 __le32 cid;
2163 __le16 dbid;
2164 u8 depth_log2;
2165 u8 stride_log2;
2166 __le64 dma_addr;
2167 u8 rsvd2[40];
2168};
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183struct ionic_notifyq_event {
2184 __le64 eid;
2185 __le16 ecode;
2186 u8 data[54];
2187};
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198struct ionic_link_change_event {
2199 __le64 eid;
2200 __le16 ecode;
2201 __le16 link_status;
2202 __le32 link_speed;
2203 u8 rsvd[48];
2204};
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216struct ionic_reset_event {
2217 __le64 eid;
2218 __le16 ecode;
2219 u8 reset_code;
2220 u8 state;
2221 u8 rsvd[52];
2222};
2223
2224
2225
2226
2227
2228
2229struct ionic_heartbeat_event {
2230 __le64 eid;
2231 __le16 ecode;
2232 u8 rsvd[54];
2233};
2234
2235
2236
2237
2238
2239
2240
2241struct ionic_log_event {
2242 __le64 eid;
2243 __le16 ecode;
2244 u8 data[54];
2245};
2246
2247
2248
2249
2250
2251
2252struct ionic_xcvr_event {
2253 __le64 eid;
2254 __le16 ecode;
2255 u8 rsvd[54];
2256};
2257
2258
2259
2260
2261struct ionic_port_stats {
2262 __le64 frames_rx_ok;
2263 __le64 frames_rx_all;
2264 __le64 frames_rx_bad_fcs;
2265 __le64 frames_rx_bad_all;
2266 __le64 octets_rx_ok;
2267 __le64 octets_rx_all;
2268 __le64 frames_rx_unicast;
2269 __le64 frames_rx_multicast;
2270 __le64 frames_rx_broadcast;
2271 __le64 frames_rx_pause;
2272 __le64 frames_rx_bad_length;
2273 __le64 frames_rx_undersized;
2274 __le64 frames_rx_oversized;
2275 __le64 frames_rx_fragments;
2276 __le64 frames_rx_jabber;
2277 __le64 frames_rx_pripause;
2278 __le64 frames_rx_stomped_crc;
2279 __le64 frames_rx_too_long;
2280 __le64 frames_rx_vlan_good;
2281 __le64 frames_rx_dropped;
2282 __le64 frames_rx_less_than_64b;
2283 __le64 frames_rx_64b;
2284 __le64 frames_rx_65b_127b;
2285 __le64 frames_rx_128b_255b;
2286 __le64 frames_rx_256b_511b;
2287 __le64 frames_rx_512b_1023b;
2288 __le64 frames_rx_1024b_1518b;
2289 __le64 frames_rx_1519b_2047b;
2290 __le64 frames_rx_2048b_4095b;
2291 __le64 frames_rx_4096b_8191b;
2292 __le64 frames_rx_8192b_9215b;
2293 __le64 frames_rx_other;
2294 __le64 frames_tx_ok;
2295 __le64 frames_tx_all;
2296 __le64 frames_tx_bad;
2297 __le64 octets_tx_ok;
2298 __le64 octets_tx_total;
2299 __le64 frames_tx_unicast;
2300 __le64 frames_tx_multicast;
2301 __le64 frames_tx_broadcast;
2302 __le64 frames_tx_pause;
2303 __le64 frames_tx_pripause;
2304 __le64 frames_tx_vlan;
2305 __le64 frames_tx_less_than_64b;
2306 __le64 frames_tx_64b;
2307 __le64 frames_tx_65b_127b;
2308 __le64 frames_tx_128b_255b;
2309 __le64 frames_tx_256b_511b;
2310 __le64 frames_tx_512b_1023b;
2311 __le64 frames_tx_1024b_1518b;
2312 __le64 frames_tx_1519b_2047b;
2313 __le64 frames_tx_2048b_4095b;
2314 __le64 frames_tx_4096b_8191b;
2315 __le64 frames_tx_8192b_9215b;
2316 __le64 frames_tx_other;
2317 __le64 frames_tx_pri_0;
2318 __le64 frames_tx_pri_1;
2319 __le64 frames_tx_pri_2;
2320 __le64 frames_tx_pri_3;
2321 __le64 frames_tx_pri_4;
2322 __le64 frames_tx_pri_5;
2323 __le64 frames_tx_pri_6;
2324 __le64 frames_tx_pri_7;
2325 __le64 frames_rx_pri_0;
2326 __le64 frames_rx_pri_1;
2327 __le64 frames_rx_pri_2;
2328 __le64 frames_rx_pri_3;
2329 __le64 frames_rx_pri_4;
2330 __le64 frames_rx_pri_5;
2331 __le64 frames_rx_pri_6;
2332 __le64 frames_rx_pri_7;
2333 __le64 tx_pripause_0_1us_count;
2334 __le64 tx_pripause_1_1us_count;
2335 __le64 tx_pripause_2_1us_count;
2336 __le64 tx_pripause_3_1us_count;
2337 __le64 tx_pripause_4_1us_count;
2338 __le64 tx_pripause_5_1us_count;
2339 __le64 tx_pripause_6_1us_count;
2340 __le64 tx_pripause_7_1us_count;
2341 __le64 rx_pripause_0_1us_count;
2342 __le64 rx_pripause_1_1us_count;
2343 __le64 rx_pripause_2_1us_count;
2344 __le64 rx_pripause_3_1us_count;
2345 __le64 rx_pripause_4_1us_count;
2346 __le64 rx_pripause_5_1us_count;
2347 __le64 rx_pripause_6_1us_count;
2348 __le64 rx_pripause_7_1us_count;
2349 __le64 rx_pause_1us_count;
2350 __le64 frames_tx_truncated;
2351};
2352
2353struct ionic_mgmt_port_stats {
2354 __le64 frames_rx_ok;
2355 __le64 frames_rx_all;
2356 __le64 frames_rx_bad_fcs;
2357 __le64 frames_rx_bad_all;
2358 __le64 octets_rx_ok;
2359 __le64 octets_rx_all;
2360 __le64 frames_rx_unicast;
2361 __le64 frames_rx_multicast;
2362 __le64 frames_rx_broadcast;
2363 __le64 frames_rx_pause;
2364 __le64 frames_rx_bad_length;
2365 __le64 frames_rx_undersized;
2366 __le64 frames_rx_oversized;
2367 __le64 frames_rx_fragments;
2368 __le64 frames_rx_jabber;
2369 __le64 frames_rx_64b;
2370 __le64 frames_rx_65b_127b;
2371 __le64 frames_rx_128b_255b;
2372 __le64 frames_rx_256b_511b;
2373 __le64 frames_rx_512b_1023b;
2374 __le64 frames_rx_1024b_1518b;
2375 __le64 frames_rx_gt_1518b;
2376 __le64 frames_rx_fifo_full;
2377 __le64 frames_tx_ok;
2378 __le64 frames_tx_all;
2379 __le64 frames_tx_bad;
2380 __le64 octets_tx_ok;
2381 __le64 octets_tx_total;
2382 __le64 frames_tx_unicast;
2383 __le64 frames_tx_multicast;
2384 __le64 frames_tx_broadcast;
2385 __le64 frames_tx_pause;
2386};
2387
2388enum ionic_pb_buffer_drop_stats {
2389 IONIC_BUFFER_INTRINSIC_DROP = 0,
2390 IONIC_BUFFER_DISCARDED,
2391 IONIC_BUFFER_ADMITTED,
2392 IONIC_BUFFER_OUT_OF_CELLS_DROP,
2393 IONIC_BUFFER_OUT_OF_CELLS_DROP_2,
2394 IONIC_BUFFER_OUT_OF_CREDIT_DROP,
2395 IONIC_BUFFER_TRUNCATION_DROP,
2396 IONIC_BUFFER_PORT_DISABLED_DROP,
2397 IONIC_BUFFER_COPY_TO_CPU_TAIL_DROP,
2398 IONIC_BUFFER_SPAN_TAIL_DROP,
2399 IONIC_BUFFER_MIN_SIZE_VIOLATION_DROP,
2400 IONIC_BUFFER_ENQUEUE_ERROR_DROP,
2401 IONIC_BUFFER_INVALID_PORT_DROP,
2402 IONIC_BUFFER_INVALID_OUTPUT_QUEUE_DROP,
2403 IONIC_BUFFER_DROP_MAX,
2404};
2405
2406enum ionic_oflow_drop_stats {
2407 IONIC_OFLOW_OCCUPANCY_DROP,
2408 IONIC_OFLOW_EMERGENCY_STOP_DROP,
2409 IONIC_OFLOW_WRITE_BUFFER_ACK_FILL_UP_DROP,
2410 IONIC_OFLOW_WRITE_BUFFER_ACK_FULL_DROP,
2411 IONIC_OFLOW_WRITE_BUFFER_FULL_DROP,
2412 IONIC_OFLOW_CONTROL_FIFO_FULL_DROP,
2413 IONIC_OFLOW_DROP_MAX,
2414};
2415
2416
2417
2418
2419
2420struct ionic_port_pb_stats {
2421 __le64 sop_count_in;
2422 __le64 eop_count_in;
2423 __le64 sop_count_out;
2424 __le64 eop_count_out;
2425 __le64 drop_counts[IONIC_BUFFER_DROP_MAX];
2426 __le64 input_queue_buffer_occupancy[IONIC_QOS_TC_MAX];
2427 __le64 input_queue_port_monitor[IONIC_QOS_TC_MAX];
2428 __le64 output_queue_port_monitor[IONIC_QOS_TC_MAX];
2429 __le64 oflow_drop_counts[IONIC_OFLOW_DROP_MAX];
2430 __le64 input_queue_good_pkts_in[IONIC_QOS_TC_MAX];
2431 __le64 input_queue_good_pkts_out[IONIC_QOS_TC_MAX];
2432 __le64 input_queue_err_pkts_in[IONIC_QOS_TC_MAX];
2433 __le64 input_queue_fifo_depth[IONIC_QOS_TC_MAX];
2434 __le64 input_queue_max_fifo_depth[IONIC_QOS_TC_MAX];
2435 __le64 input_queue_peak_occupancy[IONIC_QOS_TC_MAX];
2436 __le64 output_queue_buffer_occupancy[IONIC_QOS_TC_MAX];
2437};
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451enum ionic_port_type {
2452 IONIC_ETH_UNKNOWN,
2453 IONIC_ETH_HOST,
2454 IONIC_ETH_HOST_MGMT,
2455 IONIC_ETH_MNIC_OOB_MGMT,
2456 IONIC_ETH_MNIC_INTERNAL_MGMT,
2457 IONIC_ETH_MNIC_INBAND_MGMT,
2458 IONIC_ETH_MNIC_CPU,
2459 IONIC_ETH_MNIC_LEARN,
2460 IONIC_ETH_MNIC_CONTROL,
2461};
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477union ionic_port_identity {
2478 struct {
2479 u8 version;
2480 u8 type;
2481 u8 num_lanes;
2482 u8 autoneg;
2483 __le32 min_frame_size;
2484 __le32 max_frame_size;
2485 u8 fec_type[4];
2486 u8 pause_type[2];
2487 u8 loopback_mode[2];
2488 __le32 speeds[16];
2489 u8 rsvd2[44];
2490 union ionic_port_config config;
2491 };
2492 __le32 words[478];
2493};
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503struct ionic_port_info {
2504 union ionic_port_config config;
2505 struct ionic_port_status status;
2506 union {
2507 struct ionic_port_stats stats;
2508 struct ionic_mgmt_port_stats mgmt_stats;
2509 };
2510
2511 u8 rsvd[760];
2512 struct ionic_port_pb_stats pb_stats;
2513};
2514
2515
2516
2517
2518struct ionic_lif_stats {
2519
2520 __le64 rx_ucast_bytes;
2521 __le64 rx_ucast_packets;
2522 __le64 rx_mcast_bytes;
2523 __le64 rx_mcast_packets;
2524 __le64 rx_bcast_bytes;
2525 __le64 rx_bcast_packets;
2526 __le64 rsvd0;
2527 __le64 rsvd1;
2528
2529 __le64 rx_ucast_drop_bytes;
2530 __le64 rx_ucast_drop_packets;
2531 __le64 rx_mcast_drop_bytes;
2532 __le64 rx_mcast_drop_packets;
2533 __le64 rx_bcast_drop_bytes;
2534 __le64 rx_bcast_drop_packets;
2535 __le64 rx_dma_error;
2536 __le64 rsvd2;
2537
2538 __le64 tx_ucast_bytes;
2539 __le64 tx_ucast_packets;
2540 __le64 tx_mcast_bytes;
2541 __le64 tx_mcast_packets;
2542 __le64 tx_bcast_bytes;
2543 __le64 tx_bcast_packets;
2544 __le64 rsvd3;
2545 __le64 rsvd4;
2546
2547 __le64 tx_ucast_drop_bytes;
2548 __le64 tx_ucast_drop_packets;
2549 __le64 tx_mcast_drop_bytes;
2550 __le64 tx_mcast_drop_packets;
2551 __le64 tx_bcast_drop_bytes;
2552 __le64 tx_bcast_drop_packets;
2553 __le64 tx_dma_error;
2554 __le64 rsvd5;
2555
2556 __le64 rx_queue_disabled;
2557 __le64 rx_queue_empty;
2558 __le64 rx_queue_error;
2559 __le64 rx_desc_fetch_error;
2560 __le64 rx_desc_data_error;
2561 __le64 rsvd6;
2562 __le64 rsvd7;
2563 __le64 rsvd8;
2564
2565 __le64 tx_queue_disabled;
2566 __le64 tx_queue_error;
2567 __le64 tx_desc_fetch_error;
2568 __le64 tx_desc_data_error;
2569 __le64 tx_queue_empty;
2570 __le64 rsvd10;
2571 __le64 rsvd11;
2572 __le64 rsvd12;
2573
2574
2575 __le64 tx_rdma_ucast_bytes;
2576 __le64 tx_rdma_ucast_packets;
2577 __le64 tx_rdma_mcast_bytes;
2578 __le64 tx_rdma_mcast_packets;
2579 __le64 tx_rdma_cnp_packets;
2580 __le64 rsvd13;
2581 __le64 rsvd14;
2582 __le64 rsvd15;
2583
2584
2585 __le64 rx_rdma_ucast_bytes;
2586 __le64 rx_rdma_ucast_packets;
2587 __le64 rx_rdma_mcast_bytes;
2588 __le64 rx_rdma_mcast_packets;
2589 __le64 rx_rdma_cnp_packets;
2590 __le64 rx_rdma_ecn_packets;
2591 __le64 rsvd16;
2592 __le64 rsvd17;
2593
2594 __le64 rsvd18;
2595 __le64 rsvd19;
2596 __le64 rsvd20;
2597 __le64 rsvd21;
2598 __le64 rsvd22;
2599 __le64 rsvd23;
2600 __le64 rsvd24;
2601 __le64 rsvd25;
2602
2603 __le64 rsvd26;
2604 __le64 rsvd27;
2605 __le64 rsvd28;
2606 __le64 rsvd29;
2607 __le64 rsvd30;
2608 __le64 rsvd31;
2609 __le64 rsvd32;
2610 __le64 rsvd33;
2611
2612 __le64 rsvd34;
2613 __le64 rsvd35;
2614 __le64 rsvd36;
2615 __le64 rsvd37;
2616 __le64 rsvd38;
2617 __le64 rsvd39;
2618 __le64 rsvd40;
2619 __le64 rsvd41;
2620
2621 __le64 rsvd42;
2622 __le64 rsvd43;
2623 __le64 rsvd44;
2624 __le64 rsvd45;
2625 __le64 rsvd46;
2626 __le64 rsvd47;
2627 __le64 rsvd48;
2628 __le64 rsvd49;
2629
2630
2631 __le64 rdma_req_rx_pkt_seq_err;
2632 __le64 rdma_req_rx_rnr_retry_err;
2633 __le64 rdma_req_rx_remote_access_err;
2634 __le64 rdma_req_rx_remote_inv_req_err;
2635 __le64 rdma_req_rx_remote_oper_err;
2636 __le64 rdma_req_rx_implied_nak_seq_err;
2637 __le64 rdma_req_rx_cqe_err;
2638 __le64 rdma_req_rx_cqe_flush_err;
2639
2640 __le64 rdma_req_rx_dup_responses;
2641 __le64 rdma_req_rx_invalid_packets;
2642 __le64 rdma_req_tx_local_access_err;
2643 __le64 rdma_req_tx_local_oper_err;
2644 __le64 rdma_req_tx_memory_mgmt_err;
2645 __le64 rsvd52;
2646 __le64 rsvd53;
2647 __le64 rsvd54;
2648
2649
2650 __le64 rdma_resp_rx_dup_requests;
2651 __le64 rdma_resp_rx_out_of_buffer;
2652 __le64 rdma_resp_rx_out_of_seq_pkts;
2653 __le64 rdma_resp_rx_cqe_err;
2654 __le64 rdma_resp_rx_cqe_flush_err;
2655 __le64 rdma_resp_rx_local_len_err;
2656 __le64 rdma_resp_rx_inv_request_err;
2657 __le64 rdma_resp_rx_local_qp_oper_err;
2658
2659 __le64 rdma_resp_rx_out_of_atomic_resource;
2660 __le64 rdma_resp_tx_pkt_seq_err;
2661 __le64 rdma_resp_tx_remote_inv_req_err;
2662 __le64 rdma_resp_tx_remote_access_err;
2663 __le64 rdma_resp_tx_remote_oper_err;
2664 __le64 rdma_resp_tx_rnr_retry_err;
2665 __le64 rsvd57;
2666 __le64 rsvd58;
2667};
2668
2669
2670
2671
2672
2673
2674
2675struct ionic_lif_info {
2676 union ionic_lif_config config;
2677 struct ionic_lif_status status;
2678 struct ionic_lif_stats stats;
2679};
2680
2681union ionic_dev_cmd {
2682 u32 words[16];
2683 struct ionic_admin_cmd cmd;
2684 struct ionic_nop_cmd nop;
2685
2686 struct ionic_dev_identify_cmd identify;
2687 struct ionic_dev_init_cmd init;
2688 struct ionic_dev_reset_cmd reset;
2689 struct ionic_dev_getattr_cmd getattr;
2690 struct ionic_dev_setattr_cmd setattr;
2691
2692 struct ionic_port_identify_cmd port_identify;
2693 struct ionic_port_init_cmd port_init;
2694 struct ionic_port_reset_cmd port_reset;
2695 struct ionic_port_getattr_cmd port_getattr;
2696 struct ionic_port_setattr_cmd port_setattr;
2697
2698 struct ionic_vf_setattr_cmd vf_setattr;
2699 struct ionic_vf_getattr_cmd vf_getattr;
2700
2701 struct ionic_lif_identify_cmd lif_identify;
2702 struct ionic_lif_init_cmd lif_init;
2703 struct ionic_lif_reset_cmd lif_reset;
2704
2705 struct ionic_qos_identify_cmd qos_identify;
2706 struct ionic_qos_init_cmd qos_init;
2707 struct ionic_qos_reset_cmd qos_reset;
2708 struct ionic_qos_clear_stats_cmd qos_clear_stats;
2709
2710 struct ionic_q_identify_cmd q_identify;
2711 struct ionic_q_init_cmd q_init;
2712 struct ionic_q_control_cmd q_control;
2713};
2714
2715union ionic_dev_cmd_comp {
2716 u32 words[4];
2717 u8 status;
2718 struct ionic_admin_comp comp;
2719 struct ionic_nop_comp nop;
2720
2721 struct ionic_dev_identify_comp identify;
2722 struct ionic_dev_init_comp init;
2723 struct ionic_dev_reset_comp reset;
2724 struct ionic_dev_getattr_comp getattr;
2725 struct ionic_dev_setattr_comp setattr;
2726
2727 struct ionic_port_identify_comp port_identify;
2728 struct ionic_port_init_comp port_init;
2729 struct ionic_port_reset_comp port_reset;
2730 struct ionic_port_getattr_comp port_getattr;
2731 struct ionic_port_setattr_comp port_setattr;
2732
2733 struct ionic_vf_setattr_comp vf_setattr;
2734 struct ionic_vf_getattr_comp vf_getattr;
2735
2736 struct ionic_lif_identify_comp lif_identify;
2737 struct ionic_lif_init_comp lif_init;
2738 ionic_lif_reset_comp lif_reset;
2739
2740 struct ionic_qos_identify_comp qos_identify;
2741 ionic_qos_init_comp qos_init;
2742 ionic_qos_reset_comp qos_reset;
2743
2744 struct ionic_q_identify_comp q_identify;
2745 struct ionic_q_init_comp q_init;
2746};
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759union ionic_dev_info_regs {
2760#define IONIC_DEVINFO_FWVERS_BUFLEN 32
2761#define IONIC_DEVINFO_SERIAL_BUFLEN 32
2762 struct {
2763 u32 signature;
2764 u8 version;
2765 u8 asic_type;
2766 u8 asic_rev;
2767#define IONIC_FW_STS_F_RUNNING 0x1
2768 u8 fw_status;
2769 u32 fw_heartbeat;
2770 char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN];
2771 char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN];
2772 };
2773 u32 words[512];
2774};
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2786union ionic_dev_cmd_regs {
2787 struct {
2788 u32 doorbell;
2789 u32 done;
2790 union ionic_dev_cmd cmd;
2791 union ionic_dev_cmd_comp comp;
2792 u8 rsvd[48];
2793 u32 data[478];
2794 } __rte_packed;
2795 u32 words[512];
2796};
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2803union ionic_dev_regs {
2804 struct {
2805 union ionic_dev_info_regs info;
2806 union ionic_dev_cmd_regs devcmd;
2807 } __rte_packed;
2808 __le32 words[1024];
2809};
2810
2811union ionic_adminq_cmd {
2812 struct ionic_admin_cmd cmd;
2813 struct ionic_nop_cmd nop;
2814 struct ionic_q_identify_cmd q_identify;
2815 struct ionic_q_init_cmd q_init;
2816 struct ionic_q_control_cmd q_control;
2817 struct ionic_lif_setattr_cmd lif_setattr;
2818 struct ionic_lif_getattr_cmd lif_getattr;
2819 struct ionic_rx_mode_set_cmd rx_mode_set;
2820 struct ionic_rx_filter_add_cmd rx_filter_add;
2821 struct ionic_rx_filter_del_cmd rx_filter_del;
2822 struct ionic_rdma_reset_cmd rdma_reset;
2823 struct ionic_rdma_queue_cmd rdma_queue;
2824 struct ionic_fw_download_cmd fw_download;
2825 struct ionic_fw_control_cmd fw_control;
2826};
2827
2828union ionic_adminq_comp {
2829 struct ionic_admin_comp comp;
2830 struct ionic_nop_comp nop;
2831 struct ionic_q_identify_comp q_identify;
2832 struct ionic_q_init_comp q_init;
2833 struct ionic_lif_setattr_comp lif_setattr;
2834 struct ionic_lif_getattr_comp lif_getattr;
2835 struct ionic_rx_filter_add_comp rx_filter_add;
2836 struct ionic_fw_control_comp fw_control;
2837};
2838
2839#define IONIC_BARS_MAX 6
2840#define IONIC_PCI_BAR_DBELL 1
2841
2842
2843#define IONIC_BAR0_SIZE 0x8000
2844
2845#define IONIC_BAR0_DEV_INFO_REGS_OFFSET 0x0000
2846#define IONIC_BAR0_DEV_CMD_REGS_OFFSET 0x0800
2847#define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET 0x0c00
2848#define IONIC_BAR0_INTR_STATUS_OFFSET 0x1000
2849#define IONIC_BAR0_INTR_CTRL_OFFSET 0x2000
2850#define IONIC_DEV_CMD_DONE 0x00000001
2851
2852#define IONIC_ASIC_TYPE_CAPRI 0
2853
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2866struct ionic_doorbell {
2867 __le16 p_index;
2868 u8 ring;
2869 u8 qid_lo;
2870 __le16 qid_hi;
2871 u16 rsvd2;
2872};
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2932struct ionic_intr_ctrl {
2933 u8 coalescing_init;
2934 u8 rsvd[3];
2935 u8 mask;
2936 u8 rsvd2[3];
2937 u16 int_credits;
2938 u16 flags;
2939#define INTR_F_UNMASK 0x0001
2940#define INTR_F_TIMER_RESET 0x0002
2941 u8 mask_on_assert;
2942 u8 rsvd3[3];
2943 u8 coalescing_curr;
2944 u8 rsvd4[3];
2945 u32 rsvd6[3];
2946};
2947
2948#define IONIC_INTR_CTRL_REGS_MAX 2048
2949#define IONIC_INTR_CTRL_COAL_MAX 0x3F
2950
2951#define intr_to_coal(intr_ctrl) \
2952 ((void __iomem *)&(intr_ctrl)->coalescing_init)
2953#define intr_to_mask(intr_ctrl) \
2954 ((void __iomem *)&(intr_ctrl)->mask)
2955#define intr_to_credits(intr_ctrl) \
2956 ((void __iomem *)&(intr_ctrl)->int_credits)
2957#define intr_to_mask_on_assert(intr_ctrl)\
2958 ((void __iomem *)&(intr_ctrl)->mask_on_assert)
2959
2960struct ionic_intr_status {
2961 u32 status[2];
2962};
2963
2964struct ionic_notifyq_cmd {
2965 __le32 data;
2966};
2967
2968union ionic_notifyq_comp {
2969 struct ionic_notifyq_event event;
2970 struct ionic_link_change_event link_change;
2971 struct ionic_reset_event reset;
2972 struct ionic_heartbeat_event heartbeat;
2973 struct ionic_log_event log;
2974};
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2984struct ionic_eq_comp {
2985 __le16 code;
2986 __le16 lif_index;
2987 __le32 qid;
2988 u8 rsvd[7];
2989 u8 gen_color;
2990};
2991
2992enum ionic_eq_comp_code {
2993 IONIC_EQ_COMP_CODE_NONE = 0,
2994 IONIC_EQ_COMP_CODE_RX_COMP = 1,
2995 IONIC_EQ_COMP_CODE_TX_COMP = 2,
2996};
2997
2998
2999struct ionic_identity {
3000 union ionic_drv_identity drv;
3001 union ionic_dev_identity dev;
3002 union ionic_lif_identity lif;
3003 union ionic_port_identity port;
3004 union ionic_qos_identity qos;
3005 union ionic_q_identity txq;
3006};
3007
3008#endif
3009