1
2
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4
5
6#include "ixgbe_api.h"
7#include "ixgbe_type.h"
8#include "ixgbe_vf.h"
9
10#define IXGBE_VFWRITE_REG IXGBE_WRITE_REG
11#define IXGBE_VFREAD_REG IXGBE_READ_REG
12
13
14
15
16
17
18
19
20
21
22s32 ixgbe_init_ops_vf(struct ixgbe_hw *hw)
23{
24
25 hw->mac.ops.init_hw = ixgbe_init_hw_vf;
26 hw->mac.ops.reset_hw = ixgbe_reset_hw_vf;
27 hw->mac.ops.start_hw = ixgbe_start_hw_vf;
28
29 hw->mac.ops.clear_hw_cntrs = NULL;
30 hw->mac.ops.get_media_type = NULL;
31 hw->mac.ops.get_mac_addr = ixgbe_get_mac_addr_vf;
32 hw->mac.ops.stop_adapter = ixgbe_stop_adapter_vf;
33 hw->mac.ops.get_bus_info = NULL;
34 hw->mac.ops.negotiate_api_version = ixgbevf_negotiate_api_version;
35
36
37 hw->mac.ops.setup_link = ixgbe_setup_mac_link_vf;
38 hw->mac.ops.check_link = ixgbe_check_mac_link_vf;
39 hw->mac.ops.get_link_capabilities = NULL;
40
41
42 hw->mac.ops.set_rar = ixgbe_set_rar_vf;
43 hw->mac.ops.set_uc_addr = ixgbevf_set_uc_addr_vf;
44 hw->mac.ops.init_rx_addrs = NULL;
45 hw->mac.ops.update_mc_addr_list = ixgbe_update_mc_addr_list_vf;
46 hw->mac.ops.update_xcast_mode = ixgbevf_update_xcast_mode;
47 hw->mac.ops.enable_mc = NULL;
48 hw->mac.ops.disable_mc = NULL;
49 hw->mac.ops.clear_vfta = NULL;
50 hw->mac.ops.set_vfta = ixgbe_set_vfta_vf;
51 hw->mac.ops.set_rlpml = ixgbevf_rlpml_set_vf;
52
53 hw->mac.max_tx_queues = 1;
54 hw->mac.max_rx_queues = 1;
55
56 hw->mbx.ops.init_params = ixgbe_init_mbx_params_vf;
57
58 return IXGBE_SUCCESS;
59}
60
61
62
63
64static void ixgbe_virt_clr_reg(struct ixgbe_hw *hw)
65{
66 int i;
67 u32 vfsrrctl;
68 u32 vfdca_rxctrl;
69 u32 vfdca_txctrl;
70
71
72 vfsrrctl = 0x100 << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
73 vfsrrctl |= 0x800 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
74
75
76 vfdca_rxctrl = IXGBE_DCA_RXCTRL_DESC_RRO_EN |
77 IXGBE_DCA_RXCTRL_DATA_WRO_EN |
78 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
79
80
81 vfdca_txctrl = IXGBE_DCA_TXCTRL_DESC_RRO_EN |
82 IXGBE_DCA_TXCTRL_DESC_WRO_EN |
83 IXGBE_DCA_TXCTRL_DATA_RRO_EN;
84
85 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, 0);
86
87 for (i = 0; i < 8; i++) {
88 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
89 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
90 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), 0);
91 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), vfsrrctl);
92 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
93 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
94 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), 0);
95 IXGBE_WRITE_REG(hw, IXGBE_VFTDWBAH(i), 0);
96 IXGBE_WRITE_REG(hw, IXGBE_VFTDWBAL(i), 0);
97 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_RXCTRL(i), vfdca_rxctrl);
98 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i), vfdca_txctrl);
99 }
100
101 IXGBE_WRITE_FLUSH(hw);
102}
103
104
105
106
107
108
109
110
111
112
113s32 ixgbe_start_hw_vf(struct ixgbe_hw *hw)
114{
115
116 hw->adapter_stopped = false;
117
118 return IXGBE_SUCCESS;
119}
120
121
122
123
124
125
126
127
128s32 ixgbe_init_hw_vf(struct ixgbe_hw *hw)
129{
130 s32 status = hw->mac.ops.start_hw(hw);
131
132 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
133
134 return status;
135}
136
137
138
139
140
141
142
143
144s32 ixgbe_reset_hw_vf(struct ixgbe_hw *hw)
145{
146 struct ixgbe_mbx_info *mbx = &hw->mbx;
147 u32 timeout = IXGBE_VF_INIT_TIMEOUT;
148 s32 ret_val = IXGBE_ERR_INVALID_MAC_ADDR;
149 u32 msgbuf[IXGBE_VF_PERMADDR_MSG_LEN];
150 u8 *addr = (u8 *)(&msgbuf[1]);
151
152 DEBUGFUNC("ixgbevf_reset_hw_vf");
153
154
155 hw->mac.ops.stop_adapter(hw);
156
157
158 hw->api_version = ixgbe_mbox_api_10;
159
160 DEBUGOUT("Issuing a function level reset to MAC\n");
161
162 IXGBE_VFWRITE_REG(hw, IXGBE_VFCTRL, IXGBE_CTRL_RST);
163 IXGBE_WRITE_FLUSH(hw);
164
165 msec_delay(50);
166
167
168 while (!mbx->ops.check_for_rst(hw, 0) && timeout) {
169 timeout--;
170 usec_delay(5);
171 }
172
173 if (!timeout)
174 return IXGBE_ERR_RESET_FAILED;
175
176
177 ixgbe_virt_clr_reg(hw);
178
179
180 mbx->timeout = IXGBE_VF_MBX_INIT_TIMEOUT;
181
182 msgbuf[0] = IXGBE_VF_RESET;
183 mbx->ops.write_posted(hw, msgbuf, 1, 0);
184
185 msec_delay(10);
186
187
188
189
190
191
192 ret_val = mbx->ops.read_posted(hw, msgbuf,
193 IXGBE_VF_PERMADDR_MSG_LEN, 0);
194 if (ret_val)
195 return ret_val;
196
197 if (msgbuf[0] != (IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK) &&
198 msgbuf[0] != (IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_NACK))
199 return IXGBE_ERR_INVALID_MAC_ADDR;
200
201 if (msgbuf[0] == (IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK))
202 memcpy(hw->mac.perm_addr, addr, IXGBE_ETH_LENGTH_OF_ADDRESS);
203
204 hw->mac.mc_filter_type = msgbuf[IXGBE_VF_MC_TYPE_WORD];
205
206 return ret_val;
207}
208
209
210
211
212
213
214
215
216
217
218s32 ixgbe_stop_adapter_vf(struct ixgbe_hw *hw)
219{
220 u32 reg_val;
221 u16 i;
222
223
224
225
226
227 hw->adapter_stopped = true;
228
229
230 IXGBE_VFWRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
231
232
233 IXGBE_VFREAD_REG(hw, IXGBE_VTEICR);
234
235
236 for (i = 0; i < hw->mac.max_tx_queues; i++)
237 IXGBE_VFWRITE_REG(hw, IXGBE_VFTXDCTL(i), IXGBE_TXDCTL_SWFLSH);
238
239
240 for (i = 0; i < hw->mac.max_rx_queues; i++) {
241 reg_val = IXGBE_VFREAD_REG(hw, IXGBE_VFRXDCTL(i));
242 reg_val &= ~IXGBE_RXDCTL_ENABLE;
243 IXGBE_VFWRITE_REG(hw, IXGBE_VFRXDCTL(i), reg_val);
244 }
245
246 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, 0);
247
248
249 IXGBE_WRITE_FLUSH(hw);
250 msec_delay(2);
251
252 return IXGBE_SUCCESS;
253}
254
255
256
257
258
259
260
261
262
263
264
265
266
267STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
268{
269 u32 vector = 0;
270
271 switch (hw->mac.mc_filter_type) {
272 case 0:
273 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
274 break;
275 case 1:
276 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
277 break;
278 case 2:
279 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
280 break;
281 case 3:
282 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
283 break;
284 default:
285 DEBUGOUT("MC filter type param set incorrectly\n");
286 ASSERT(0);
287 break;
288 }
289
290
291 vector &= 0xFFF;
292 return vector;
293}
294
295STATIC s32 ixgbevf_write_msg_read_ack(struct ixgbe_hw *hw, u32 *msg,
296 u32 *retmsg, u16 size)
297{
298 struct ixgbe_mbx_info *mbx = &hw->mbx;
299 s32 retval = mbx->ops.write_posted(hw, msg, size, 0);
300
301 if (retval)
302 return retval;
303
304 return mbx->ops.read_posted(hw, retmsg, size, 0);
305}
306
307
308
309
310
311
312
313
314
315s32 ixgbe_set_rar_vf(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
316 u32 enable_addr)
317{
318 u32 msgbuf[3];
319 u8 *msg_addr = (u8 *)(&msgbuf[1]);
320 s32 ret_val;
321 UNREFERENCED_3PARAMETER(vmdq, enable_addr, index);
322
323 memset(msgbuf, 0, 12);
324 msgbuf[0] = IXGBE_VF_SET_MAC_ADDR;
325 memcpy(msg_addr, addr, 6);
326 ret_val = ixgbevf_write_msg_read_ack(hw, msgbuf, msgbuf, 3);
327
328 msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
329
330
331 if (!ret_val &&
332 (msgbuf[0] == (IXGBE_VF_SET_MAC_ADDR | IXGBE_VT_MSGTYPE_NACK))) {
333 ixgbe_get_mac_addr_vf(hw, hw->mac.addr);
334 return IXGBE_ERR_MBX;
335 }
336
337 return ret_val;
338}
339
340
341
342
343
344
345
346
347
348
349
350s32 ixgbe_update_mc_addr_list_vf(struct ixgbe_hw *hw, u8 *mc_addr_list,
351 u32 mc_addr_count, ixgbe_mc_addr_itr next,
352 bool clear)
353{
354 struct ixgbe_mbx_info *mbx = &hw->mbx;
355 u32 msgbuf[IXGBE_VFMAILBOX_SIZE];
356 u16 *vector_list = (u16 *)&msgbuf[1];
357 u32 vector;
358 u32 cnt, i;
359 u32 vmdq;
360
361 UNREFERENCED_1PARAMETER(clear);
362
363 DEBUGFUNC("ixgbe_update_mc_addr_list_vf");
364
365
366
367
368
369
370
371
372
373
374 DEBUGOUT1("MC Addr Count = %d\n", mc_addr_count);
375
376 cnt = (mc_addr_count > 30) ? 30 : mc_addr_count;
377 msgbuf[0] = IXGBE_VF_SET_MULTICAST;
378 msgbuf[0] |= cnt << IXGBE_VT_MSGINFO_SHIFT;
379
380 for (i = 0; i < cnt; i++) {
381 vector = ixgbe_mta_vector(hw, next(hw, &mc_addr_list, &vmdq));
382 DEBUGOUT1("Hash value = 0x%03X\n", vector);
383 vector_list[i] = (u16)vector;
384 }
385
386 return mbx->ops.write_posted(hw, msgbuf, IXGBE_VFMAILBOX_SIZE, 0);
387}
388
389
390
391
392
393
394
395
396s32 ixgbevf_update_xcast_mode(struct ixgbe_hw *hw, int xcast_mode)
397{
398 u32 msgbuf[2];
399 s32 err;
400
401 switch (hw->api_version) {
402 case ixgbe_mbox_api_12:
403
404 if (xcast_mode > IXGBEVF_XCAST_MODE_ALLMULTI)
405 return IXGBE_ERR_FEATURE_NOT_SUPPORTED;
406
407 case ixgbe_mbox_api_13:
408 break;
409 default:
410 return IXGBE_ERR_FEATURE_NOT_SUPPORTED;
411 }
412
413 msgbuf[0] = IXGBE_VF_UPDATE_XCAST_MODE;
414 msgbuf[1] = xcast_mode;
415
416 err = ixgbevf_write_msg_read_ack(hw, msgbuf, msgbuf, 2);
417 if (err)
418 return err;
419
420 msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
421 if (msgbuf[0] == (IXGBE_VF_UPDATE_XCAST_MODE | IXGBE_VT_MSGTYPE_NACK))
422 return IXGBE_ERR_FEATURE_NOT_SUPPORTED;
423 return IXGBE_SUCCESS;
424}
425
426
427
428
429
430
431
432
433
434
435
436s32 ixgbe_set_vfta_vf(struct ixgbe_hw *hw, u32 vlan, u32 vind,
437 bool vlan_on, bool vlvf_bypass)
438{
439 u32 msgbuf[2];
440 s32 ret_val;
441 UNREFERENCED_2PARAMETER(vind, vlvf_bypass);
442
443 msgbuf[0] = IXGBE_VF_SET_VLAN;
444 msgbuf[1] = vlan;
445
446 msgbuf[0] |= vlan_on << IXGBE_VT_MSGINFO_SHIFT;
447
448 ret_val = ixgbevf_write_msg_read_ack(hw, msgbuf, msgbuf, 2);
449 if (!ret_val && (msgbuf[0] & IXGBE_VT_MSGTYPE_ACK))
450 return IXGBE_SUCCESS;
451
452 return ret_val | (msgbuf[0] & IXGBE_VT_MSGTYPE_NACK);
453}
454
455
456
457
458
459
460
461u32 ixgbe_get_num_of_tx_queues_vf(struct ixgbe_hw *hw)
462{
463 UNREFERENCED_1PARAMETER(hw);
464 return IXGBE_VF_MAX_TX_QUEUES;
465}
466
467
468
469
470
471
472
473u32 ixgbe_get_num_of_rx_queues_vf(struct ixgbe_hw *hw)
474{
475 UNREFERENCED_1PARAMETER(hw);
476 return IXGBE_VF_MAX_RX_QUEUES;
477}
478
479
480
481
482
483
484s32 ixgbe_get_mac_addr_vf(struct ixgbe_hw *hw, u8 *mac_addr)
485{
486 int i;
487
488 for (i = 0; i < IXGBE_ETH_LENGTH_OF_ADDRESS; i++)
489 mac_addr[i] = hw->mac.perm_addr[i];
490
491 return IXGBE_SUCCESS;
492}
493
494s32 ixgbevf_set_uc_addr_vf(struct ixgbe_hw *hw, u32 index, u8 *addr)
495{
496 u32 msgbuf[3], msgbuf_chk;
497 u8 *msg_addr = (u8 *)(&msgbuf[1]);
498 s32 ret_val;
499
500 memset(msgbuf, 0, sizeof(msgbuf));
501
502
503
504
505
506
507 msgbuf[0] |= index << IXGBE_VT_MSGINFO_SHIFT;
508 msgbuf[0] |= IXGBE_VF_SET_MACVLAN;
509 msgbuf_chk = msgbuf[0];
510 if (addr)
511 memcpy(msg_addr, addr, 6);
512
513 ret_val = ixgbevf_write_msg_read_ack(hw, msgbuf, msgbuf, 3);
514 if (!ret_val) {
515 msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
516
517 if (msgbuf[0] == (msgbuf_chk | IXGBE_VT_MSGTYPE_NACK))
518 return IXGBE_ERR_OUT_OF_MEM;
519 }
520
521 return ret_val;
522}
523
524
525
526
527
528
529
530
531
532s32 ixgbe_setup_mac_link_vf(struct ixgbe_hw *hw, ixgbe_link_speed speed,
533 bool autoneg_wait_to_complete)
534{
535 UNREFERENCED_3PARAMETER(hw, speed, autoneg_wait_to_complete);
536 return IXGBE_SUCCESS;
537}
538
539
540
541
542
543
544
545
546
547
548s32 ixgbe_check_mac_link_vf(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
549 bool *link_up, bool autoneg_wait_to_complete)
550{
551 struct ixgbe_mbx_info *mbx = &hw->mbx;
552 struct ixgbe_mac_info *mac = &hw->mac;
553 s32 ret_val = IXGBE_SUCCESS;
554 u32 links_reg;
555 u32 in_msg = 0;
556 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
557
558
559 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
560 mac->get_link_status = true;
561
562 if (!mac->get_link_status)
563 goto out;
564
565
566 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
567 if (!(links_reg & IXGBE_LINKS_UP))
568 goto out;
569
570
571
572
573 if (mac->type == ixgbe_mac_82599_vf) {
574 int i;
575
576 for (i = 0; i < 5; i++) {
577 usec_delay(100);
578 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
579
580 if (!(links_reg & IXGBE_LINKS_UP))
581 goto out;
582 }
583 }
584
585 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
586 case IXGBE_LINKS_SPEED_10G_82599:
587 *speed = IXGBE_LINK_SPEED_10GB_FULL;
588 if (hw->mac.type >= ixgbe_mac_X550) {
589 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
590 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
591 }
592 break;
593 case IXGBE_LINKS_SPEED_1G_82599:
594 *speed = IXGBE_LINK_SPEED_1GB_FULL;
595 break;
596 case IXGBE_LINKS_SPEED_100_82599:
597 *speed = IXGBE_LINK_SPEED_100_FULL;
598 if (hw->mac.type == ixgbe_mac_X550) {
599 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
600 *speed = IXGBE_LINK_SPEED_5GB_FULL;
601 }
602 break;
603 case IXGBE_LINKS_SPEED_10_X550EM_A:
604 *speed = IXGBE_LINK_SPEED_UNKNOWN;
605
606 if (hw->mac.type >= ixgbe_mac_X550)
607 *speed = IXGBE_LINK_SPEED_10_FULL;
608 break;
609 default:
610 *speed = IXGBE_LINK_SPEED_UNKNOWN;
611 }
612
613
614
615
616 if (mbx->ops.read(hw, &in_msg, 1, 0))
617 goto out;
618
619 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
620
621 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
622 ret_val = -1;
623 goto out;
624 }
625
626
627 if (!mbx->timeout) {
628 ret_val = -1;
629 goto out;
630 }
631
632
633
634
635 mac->get_link_status = false;
636
637out:
638 *link_up = !mac->get_link_status;
639 return ret_val;
640}
641
642
643
644
645
646
647s32 ixgbevf_rlpml_set_vf(struct ixgbe_hw *hw, u16 max_size)
648{
649 u32 msgbuf[2];
650 s32 retval;
651
652 msgbuf[0] = IXGBE_VF_SET_LPE;
653 msgbuf[1] = max_size;
654
655 retval = ixgbevf_write_msg_read_ack(hw, msgbuf, msgbuf, 2);
656 if (retval)
657 return retval;
658 if ((msgbuf[0] & IXGBE_VF_SET_LPE) &&
659 (msgbuf[0] & IXGBE_VT_MSGTYPE_NACK))
660 return IXGBE_ERR_MBX;
661
662 return 0;
663}
664
665
666
667
668
669
670int ixgbevf_negotiate_api_version(struct ixgbe_hw *hw, int api)
671{
672 int err;
673 u32 msg[3];
674
675
676 msg[0] = IXGBE_VF_API_NEGOTIATE;
677 msg[1] = api;
678 msg[2] = 0;
679
680 err = ixgbevf_write_msg_read_ack(hw, msg, msg, 3);
681 if (!err) {
682 msg[0] &= ~IXGBE_VT_MSGTYPE_CTS;
683
684
685 if (msg[0] == (IXGBE_VF_API_NEGOTIATE | IXGBE_VT_MSGTYPE_ACK)) {
686 hw->api_version = api;
687 return 0;
688 }
689
690 err = IXGBE_ERR_INVALID_ARGUMENT;
691 }
692
693 return err;
694}
695
696int ixgbevf_get_queues(struct ixgbe_hw *hw, unsigned int *num_tcs,
697 unsigned int *default_tc)
698{
699 int err;
700 u32 msg[5];
701
702
703 switch (hw->api_version) {
704 case ixgbe_mbox_api_11:
705 case ixgbe_mbox_api_12:
706 case ixgbe_mbox_api_13:
707 break;
708 default:
709 return 0;
710 }
711
712
713 msg[0] = IXGBE_VF_GET_QUEUES;
714 msg[1] = msg[2] = msg[3] = msg[4] = 0;
715
716 err = ixgbevf_write_msg_read_ack(hw, msg, msg, 5);
717 if (!err) {
718 msg[0] &= ~IXGBE_VT_MSGTYPE_CTS;
719
720
721
722
723
724
725 if (msg[0] != (IXGBE_VF_GET_QUEUES | IXGBE_VT_MSGTYPE_ACK))
726 return IXGBE_ERR_MBX;
727
728
729 hw->mac.max_tx_queues = msg[IXGBE_VF_TX_QUEUES];
730 if (hw->mac.max_tx_queues == 0 ||
731 hw->mac.max_tx_queues > IXGBE_VF_MAX_TX_QUEUES)
732 hw->mac.max_tx_queues = IXGBE_VF_MAX_TX_QUEUES;
733
734 hw->mac.max_rx_queues = msg[IXGBE_VF_RX_QUEUES];
735 if (hw->mac.max_rx_queues == 0 ||
736 hw->mac.max_rx_queues > IXGBE_VF_MAX_RX_QUEUES)
737 hw->mac.max_rx_queues = IXGBE_VF_MAX_RX_QUEUES;
738
739 *num_tcs = msg[IXGBE_VF_TRANS_VLAN];
740
741 if (*num_tcs > hw->mac.max_rx_queues)
742 *num_tcs = 1;
743
744 *default_tc = msg[IXGBE_VF_DEF_QUEUE];
745
746 if (*default_tc >= hw->mac.max_tx_queues)
747 *default_tc = 0;
748 }
749
750 return err;
751}
752