LXR dpdk/drivers/common/iavf/iavf

   1/* SPDX-License-Identifier: BSD-3-Clause
   2 * Copyright(c) 2001-2021 Intel Corporation
   3 */
   4
   5#ifndef _IAVF_REGISTER_H_
   6#define _IAVF_REGISTER_H_
   7
   8#define IAVF_VF_ARQBAH1              0x00006000 /* Reset: EMPR */
   9#define IAVF_VF_ARQBAL1              0x00006C00 /* Reset: EMPR */
  10#define IAVF_VF_ARQH1            0x00007400 /* Reset: EMPR */
  11#define IAVF_VF_ARQH1_ARQH_SHIFT 0
  12#define IAVF_VF_ARQH1_ARQH_MASK  IAVF_MASK(0x3FF, IAVF_VF_ARQH1_ARQH_SHIFT)
  13#define IAVF_VF_ARQLEN1                 0x00008000 /* Reset: EMPR */
  14#define IAVF_VF_ARQLEN1_ARQVFE_SHIFT    28
  15#define IAVF_VF_ARQLEN1_ARQVFE_MASK     IAVF_MASK(1UL, IAVF_VF_ARQLEN1_ARQVFE_SHIFT)
  16#define IAVF_VF_ARQLEN1_ARQOVFL_SHIFT   29
  17#define IAVF_VF_ARQLEN1_ARQOVFL_MASK    IAVF_MASK(1UL, IAVF_VF_ARQLEN1_ARQOVFL_SHIFT)
  18#define IAVF_VF_ARQLEN1_ARQCRIT_SHIFT   30
  19#define IAVF_VF_ARQLEN1_ARQCRIT_MASK    IAVF_MASK(1UL, IAVF_VF_ARQLEN1_ARQCRIT_SHIFT)
  20#define IAVF_VF_ARQLEN1_ARQENABLE_SHIFT 31
  21#define IAVF_VF_ARQLEN1_ARQENABLE_MASK  IAVF_MASK(1UL, IAVF_VF_ARQLEN1_ARQENABLE_SHIFT)
  22#define IAVF_VF_ARQT1            0x00007000 /* Reset: EMPR */
  23#define IAVF_VF_ATQBAH1              0x00007800 /* Reset: EMPR */
  24#define IAVF_VF_ATQBAL1              0x00007C00 /* Reset: EMPR */
  25#define IAVF_VF_ATQH1            0x00006400 /* Reset: EMPR */
  26#define IAVF_VF_ATQLEN1                 0x00006800 /* Reset: EMPR */
  27#define IAVF_VF_ATQLEN1_ATQVFE_SHIFT    28
  28#define IAVF_VF_ATQLEN1_ATQVFE_MASK     IAVF_MASK(1UL, IAVF_VF_ATQLEN1_ATQVFE_SHIFT)
  29#define IAVF_VF_ATQLEN1_ATQOVFL_SHIFT   29
  30#define IAVF_VF_ATQLEN1_ATQOVFL_MASK    IAVF_MASK(1UL, IAVF_VF_ATQLEN1_ATQOVFL_SHIFT)
  31#define IAVF_VF_ATQLEN1_ATQCRIT_SHIFT   30
  32#define IAVF_VF_ATQLEN1_ATQCRIT_MASK    IAVF_MASK(1UL, IAVF_VF_ATQLEN1_ATQCRIT_SHIFT)
  33#define IAVF_VF_ATQLEN1_ATQENABLE_SHIFT 31
  34#define IAVF_VF_ATQLEN1_ATQENABLE_MASK  IAVF_MASK(1UL, IAVF_VF_ATQLEN1_ATQENABLE_SHIFT)
  35#define IAVF_VF_ATQT1            0x00008400 /* Reset: EMPR */
  36#define IAVF_VFGEN_RSTAT                 0x00008800 /* Reset: VFR */
  37#define IAVF_VFGEN_RSTAT_VFR_STATE_SHIFT 0
  38#define IAVF_VFGEN_RSTAT_VFR_STATE_MASK  IAVF_MASK(0x3, IAVF_VFGEN_RSTAT_VFR_STATE_SHIFT)
  39#define IAVF_VFINT_DYN_CTL01                       0x00005C00 /* Reset: VFR */
  40#define IAVF_VFINT_DYN_CTL01_INTENA_SHIFT          0
  41#define IAVF_VFINT_DYN_CTL01_INTENA_MASK           IAVF_MASK(1UL, IAVF_VFINT_DYN_CTL01_INTENA_SHIFT)
  42#define IAVF_VFINT_DYN_CTL01_CLEARPBA_SHIFT        1
  43#define IAVF_VFINT_DYN_CTL01_CLEARPBA_MASK         IAVF_MASK(1UL, IAVF_VFINT_DYN_CTL01_CLEARPBA_SHIFT)
  44#define IAVF_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT      2
  45#define IAVF_VFINT_DYN_CTL01_SWINT_TRIG_MASK       IAVF_MASK(1UL, IAVF_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT)
  46#define IAVF_VFINT_DYN_CTL01_ITR_INDX_SHIFT        3
  47#define IAVF_VFINT_DYN_CTL01_ITR_INDX_MASK         IAVF_MASK(0x3, IAVF_VFINT_DYN_CTL01_ITR_INDX_SHIFT)
  48#define IAVF_VFINT_DYN_CTL01_INTERVAL_SHIFT        5
  49#define IAVF_VFINT_DYN_CTL01_INTERVAL_MASK         IAVF_MASK(0xFFF, IAVF_VFINT_DYN_CTL01_INTERVAL_SHIFT)
  50#define IAVF_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT 24
  51#define IAVF_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_MASK  IAVF_MASK(1UL, IAVF_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT)
  52#define IAVF_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT     25
  53#define IAVF_VFINT_DYN_CTL01_SW_ITR_INDX_MASK      IAVF_MASK(0x3, IAVF_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT)
  54#define IAVF_VFINT_DYN_CTLN1(_INTVF)               (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */
  55#define IAVF_VFINT_DYN_CTLN1_INTENA_SHIFT          0
  56#define IAVF_VFINT_DYN_CTLN1_INTENA_MASK           IAVF_MASK(1UL, IAVF_VFINT_DYN_CTLN1_INTENA_SHIFT)
  57#define IAVF_VFINT_DYN_CTLN1_CLEARPBA_SHIFT        1
  58#define IAVF_VFINT_DYN_CTLN1_CLEARPBA_MASK         IAVF_MASK(1UL, IAVF_VFINT_DYN_CTLN1_CLEARPBA_SHIFT)
  59#define IAVF_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT      2
  60#define IAVF_VFINT_DYN_CTLN1_SWINT_TRIG_MASK       IAVF_MASK(1UL, IAVF_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT)
  61#define IAVF_VFINT_DYN_CTLN1_ITR_INDX_SHIFT        3
  62#define IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK         IAVF_MASK(0x3, IAVF_VFINT_DYN_CTLN1_ITR_INDX_SHIFT)
  63#define IAVF_VFINT_DYN_CTLN1_INTERVAL_SHIFT        5
  64#define IAVF_VFINT_DYN_CTLN1_INTERVAL_MASK         IAVF_MASK(0xFFF, IAVF_VFINT_DYN_CTLN1_INTERVAL_SHIFT)
  65#define IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24
  66#define IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK  IAVF_MASK(1UL, IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT)
  67#define IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT     25
  68#define IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_MASK      IAVF_MASK(0x3, IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT)
  69#define IAVF_VFINT_ICR0_ENA1                        0x00005000 /* Reset: CORER */
  70#define IAVF_VFINT_ICR0_ENA1_ADMINQ_SHIFT           30
  71#define IAVF_VFINT_ICR0_ENA1_ADMINQ_MASK            IAVF_MASK(1UL, IAVF_VFINT_ICR0_ENA1_ADMINQ_SHIFT)
  72#define IAVF_VFINT_ICR0_ENA1_RSVD_SHIFT             31
  73#define IAVF_VFINT_ICR01                        0x00004800 /* Reset: CORER */
  74#define IAVF_VFINT_ICR01_QUEUE_0_SHIFT          1
  75#define IAVF_VFINT_ICR01_QUEUE_0_MASK           IAVF_MASK(1UL, IAVF_VFINT_ICR01_QUEUE_0_SHIFT)
  76#define IAVF_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT 25
  77#define IAVF_VFINT_ICR01_LINK_STAT_CHANGE_MASK  IAVF_MASK(1UL, IAVF_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT)
  78#define IAVF_VFINT_ICR01_ADMINQ_SHIFT           30
  79#define IAVF_VFINT_ICR01_ADMINQ_MASK            IAVF_MASK(1UL, IAVF_VFINT_ICR01_ADMINQ_SHIFT)
  80#define IAVF_VFINT_ITR01(_i)            (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset: VFR */
  81#define IAVF_VFINT_ITRN1(_i, _INTVF)     (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */
  82#define IAVF_VFINT_STAT_CTL01                      0x00005400 /* Reset: CORER */
  83#define IAVF_QRX_TAIL1(_Q)        (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */
  84#define IAVF_QTX_TAIL1(_Q)        (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: PFR */
  85#define IAVF_VFQF_HENA(_i)             (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */
  86#define IAVF_VFQF_HKEY(_i)         (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */
  87#define IAVF_VFQF_HKEY_MAX_INDEX   12
  88#define IAVF_VFQF_HLUT(_i)        (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
  89#define IAVF_VFQF_HLUT_MAX_INDEX  15
  90#define IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT       30
  91#define IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK        IAVF_MASK(1UL, IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT)
  92
  93#endif /* _IAVF_REGISTER_H_ */
  94