1/* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2012-2019 Solarflare Communications Inc. 5 */ 6 7/* 8 * This is NOT the original source file. Do NOT edit it. 9 * To update the tlv layout, please edit the copy in 10 * the sfregistry repo and then, in that repo, 11 * "make tlv_headers" or "make export" to 12 * regenerate and export all types of headers. 13 */ 14 15/* These structures define the layouts for the TLV items stored in static and 16 * dynamic configuration partitions in NVRAM for EF10 (Huntington etc.). 17 * 18 * They contain the same sort of information that was kept in the 19 * siena_mc_static_config_hdr_t and siena_mc_dynamic_config_hdr_t structures 20 * (defined in <ci/mgmt/mc_flash_layout.h> and <ci/mgmt/mc_dynamic_cfg.h>) for 21 * Siena. 22 * 23 * These are used directly by the MC and should also be usable directly on host 24 * systems which are little-endian and do not do strange things with structure 25 * padding. (Big-endian host systems will require some byte-swapping.) 26 * 27 * ----- 28 * 29 * Please refer to SF-108797-SW for a general overview of the TLV partition 30 * format. 31 * 32 * ----- 33 * 34 * The current tag IDs have a general structure: with the exception of the 35 * special values defined in the document, they are of the form 0xLTTTNNNN, 36 * where: 37 * 38 * - L is a location, indicating where this tag is expected to be found: 39 * 0: static configuration 40 * 1: dynamic configuration 41 * 2: firmware internal use 42 * 3: license partition 43 * 4: tsa configuration 44 * 5: bundle update 45 * 46 * - TTT is a type, which is just a unique value. The same type value 47 * might appear in both locations, indicating a relationship between 48 * the items (e.g. static and dynamic VPD below). 49 * 50 * - NNNN is an index of some form. Some item types are per-port, some 51 * are per-PF, some are per-partition-type. 52 * 53 * ----- 54 * 55 * As with the previous Siena structures, each structure here is laid out 56 * carefully: values are aligned to their natural boundary, with explicit 57 * padding fields added where necessary. (No, technically this does not 58 * absolutely guarantee portability. But, in practice, compilers are generally 59 * sensible enough not to introduce completely pointless padding, and it works 60 * well enough.) 61 */ 62 63 64#ifndef CI_MGMT_TLV_LAYOUT_H 65#define CI_MGMT_TLV_LAYOUT_H 66 67 68/* ---------------------------------------------------------------------------- 69 * General structure (defined by SF-108797-SW) 70 * ---------------------------------------------------------------------------- 71 */ 72 73 74/* The "end" tag. 75 * 76 * (Note that this is *not* followed by length or value fields: anything after 77 * the tag itself is irrelevant.) 78 */ 79 80#define TLV_TAG_END (0xEEEEEEEE) 81 82 83/* Other special reserved tag values. 84 */ 85 86#define TLV_TAG_SKIP (0x00000000) 87#define TLV_TAG_INVALID (0xFFFFFFFF) 88 89 90/* TLV start. 91 * 92 * Marks the start of a TLV layout within a partition that may/may-not be 93 * a TLV partition. i.e. if a portion of data (at any offset) within a 94 * partition is expected to be in TLV format, then the first tag in this 95 * layout is expected to be TLV_TAG_START. 96 * 97 * This tag is not used in TLV layouts where the entire partition is TLV. 98 * Please continue using TLV_TAG_PARTITION_HEADER to indicate the start 99 * of TLV layout in such cases. 100 */ 101 102#define TLV_TAG_START (0xEF10BA5E) 103 104struct tlv_start { 105 uint32_t tag; 106 uint32_t length; 107 /* Length of the TLV structure following this tag - includes length of all tags 108 * within the TLV layout starting with this TLV_TAG_START. 109 * Includes TLV_TAG_END. Does not include TLV_TAG_START 110 */ 111 uint32_t tlv_layout_len; 112}; 113 114/* TLV partition header. 115 * 116 * In a TLV partition, this must be the first item in the sequence, at offset 117 * 0. 118 */ 119 120#define TLV_TAG_PARTITION_HEADER (0xEF10DA7A) 121 122struct tlv_partition_header { 123 uint32_t tag; 124 uint32_t length; 125 uint16_t type_id; 126/* 0 indicates the default segment (always located at offset 0), while other values 127 * are for RFID-selectable presets that should immediately follow the default segment. 128 * The default segment may also have preset > 0, which means that it is a preset 129 * selected through an RFID command and copied by FW to the location at offset 0. */ 130 uint16_t preset; 131 uint32_t generation; 132 uint32_t total_length; 133}; 134 135 136/* TLV partition trailer. 137 * 138 * In a TLV partition, this must be the last item in the sequence, immediately 139 * preceding the TLV_TAG_END word. 140 */ 141 142#define TLV_TAG_PARTITION_TRAILER (0xEF101A57) 143 144struct tlv_partition_trailer { 145 uint32_t tag; 146 uint32_t length; 147 uint32_t generation; 148 uint32_t checksum; 149}; 150 151 152/* Appendable TLV partition header. 153 * 154 * In an appendable TLV partition, this must be the first item in the sequence, 155 * at offset 0. (Note that, unlike the configuration partitions, there is no 156 * trailer before the TLV_TAG_END word.) 157 */ 158 159#define TLV_TAG_APPENDABLE_PARTITION_HEADER (0xEF10ADA7) 160 161struct tlv_appendable_partition_header { 162 uint32_t tag; 163 uint32_t length; 164 uint16_t type_id; 165 uint16_t reserved; 166}; 167 168 169/* ---------------------------------------------------------------------------- 170 * Configuration items 171 * ---------------------------------------------------------------------------- 172 */ 173 174 175/* NIC global capabilities. 176 */ 177 178#define TLV_TAG_GLOBAL_CAPABILITIES (0x00010000) 179 180struct tlv_global_capabilities { 181 uint32_t tag; 182 uint32_t length; 183 uint32_t flags; 184}; 185 186 187/* Siena-style per-port MAC address allocation. 188 * 189 * There are <count> addresses, starting at <base_address> and incrementing 190 * by adding <stride> to the low-order byte(s). 191 * 192 * (See also TLV_TAG_GLOBAL_MAC for an alternative, specifying a global pool 193 * of contiguous MAC addresses for the firmware to allocate as it sees fit.) 194 */ 195 196#define TLV_TAG_PORT_MAC(port) (0x00020000 + (port)) 197 198struct tlv_port_mac { 199 uint32_t tag; 200 uint32_t length; 201 uint8_t base_address[6]; 202 uint16_t reserved; 203 uint16_t count; 204 uint16_t stride; 205}; 206 207 208/* Static VPD. 209 * 210 * This is the portion of VPD which is set at manufacturing time and not 211 * expected to change. It is formatted as a standard PCI VPD block. There are 212 * global and per-pf TLVs for this, the global TLV is new for Medford and is 213 * used in preference to the per-pf TLV. 214 */ 215 216#define TLV_TAG_PF_STATIC_VPD(pf) (0x00030000 + (pf)) 217 218struct tlv_pf_static_vpd { 219 uint32_t tag; 220 uint32_t length; 221 uint8_t bytes[]; 222}; 223 224#define TLV_TAG_GLOBAL_STATIC_VPD (0x001f0000) 225 226struct tlv_global_static_vpd { 227 uint32_t tag; 228 uint32_t length; 229 uint8_t bytes[]; 230}; 231 232 233/* Dynamic VPD. 234 * 235 * This is the portion of VPD which may be changed (e.g. by firmware updates). 236 * It is formatted as a standard PCI VPD block. There are global and per-pf TLVs 237 * for this, the global TLV is new for Medford and is used in preference to the 238 * per-pf TLV. 239 */ 240 241#define TLV_TAG_PF_DYNAMIC_VPD(pf) (0x10030000 + (pf)) 242 243struct tlv_pf_dynamic_vpd { 244 uint32_t tag; 245 uint32_t length; 246 uint8_t bytes[]; 247}; 248 249#define TLV_TAG_GLOBAL_DYNAMIC_VPD (0x10200000) 250 251struct tlv_global_dynamic_vpd { 252 uint32_t tag; 253 uint32_t length; 254 uint8_t bytes[]; 255}; 256 257 258/* "DBI" PCI config space changes. 259 * 260 * This is a set of edits made to the default PCI config space values before 261 * the device is allowed to enumerate. There are global and per-pf TLVs for 262 * this, the global TLV is new for Medford and is used in preference to the 263 * per-pf TLV. 264 */ 265 266#define TLV_TAG_PF_DBI(pf) (0x00040000 + (pf)) 267 268struct tlv_pf_dbi { 269 uint32_t tag; 270 uint32_t length; 271 struct { 272 uint16_t addr; 273 uint16_t byte_enables; 274 uint32_t value; 275 } items[]; 276}; 277 278 279#define TLV_TAG_GLOBAL_DBI (0x00210000) 280 281struct tlv_global_dbi { 282 uint32_t tag; 283 uint32_t length; 284 struct { 285 uint16_t addr; 286 uint16_t byte_enables; 287 uint32_t value; 288 } items[]; 289}; 290 291 292/* Partition subtype codes. 293 * 294 * A subtype may optionally be stored for each type of partition present in 295 * the NVRAM. For example, this may be used to allow a generic firmware update 296 * utility to select a specific variant of firmware for a specific variant of 297 * board. 298 * 299 * The description[] field is an optional string which is returned in the 300 * MC_CMD_NVRAM_METADATA response if present. 301 */ 302 303#define TLV_TAG_PARTITION_SUBTYPE(type) (0x00050000 + (type)) 304 305struct tlv_partition_subtype { 306 uint32_t tag; 307 uint32_t length; 308 uint32_t subtype; 309 uint8_t description[]; 310}; 311 312 313/* Partition version codes. 314 * 315 * A version may optionally be stored for each type of partition present in 316 * the NVRAM. This provides a standard way of tracking the currently stored 317 * version of each of the various component images. 318 */ 319 320#define TLV_TAG_PARTITION_VERSION(type) (0x10060000 + (type)) 321 322struct tlv_partition_version { 323 uint32_t tag; 324 uint32_t length; 325 uint16_t version_w; 326 uint16_t version_x; 327 uint16_t version_y; 328 uint16_t version_z; 329}; 330 331/* Global PCIe configuration */ 332 333#define TLV_TAG_GLOBAL_PCIE_CONFIG (0x10070000) 334 335struct tlv_pcie_config { 336 uint32_t tag; 337 uint32_t length; 338 int16_t max_pf_number; /**< Largest PF RID (lower PFs may be hidden) */ 339 uint16_t pf_aper; /**< BIU aperture for PF BAR2 */ 340 uint16_t vf_aper; /**< BIU aperture for VF BAR0 */ 341 uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */ 342#define TLV_MAX_PF_DEFAULT (-1) /* Use FW default for largest PF RID */ 343#define TLV_APER_DEFAULT (0xFFFF) /* Use FW default for a given aperture */ 344}; 345 346/* Per-PF configuration. Note that not all these fields are necessarily useful 347 * as the apertures are constrained by the BIU settings (the one case we do 348 * use is to make BAR2 bigger than the BIU thinks to reserve space), but we can 349 * tidy things up later */ 350 351#define TLV_TAG_PF_PCIE_CONFIG(pf) (0x10080000 + (pf)) 352 353struct tlv_per_pf_pcie_config { 354 uint32_t tag; 355 uint32_t length; 356 uint8_t vfs_total; 357 uint8_t port_allocation; 358 uint16_t vectors_per_pf; 359 uint16_t vectors_per_vf; 360 uint8_t pf_bar0_aperture; 361 uint8_t pf_bar2_aperture; 362 uint8_t vf_bar0_aperture; 363 uint8_t vf_base; 364 uint16_t supp_pagesz; 365 uint16_t msix_vec_base; 366}; 367 368 369/* Development ONLY. This is a single TLV tag for all the gubbins 370 * that can be set through the MC command-line other than the PCIe 371 * settings. This is a temporary measure. */ 372#define TLV_TAG_TMP_GUBBINS (0x10090000) /* legacy symbol - do not use */ 373#define TLV_TAG_TMP_GUBBINS_HUNT TLV_TAG_TMP_GUBBINS 374 375struct tlv_tmp_gubbins { 376 uint32_t tag; 377 uint32_t length; 378 /* Consumed by dpcpu.c */ 379 uint64_t tx0_tags; /* Bitmap */ 380 uint64_t tx1_tags; /* Bitmap */ 381 uint64_t dl_tags; /* Bitmap */ 382 uint32_t flags; 383#define TLV_DPCPU_TX_STRIPE (1) /* No longer used, has no effect */ 384#define TLV_DPCPU_BIU_TAGS (2) /* Use BIU tag manager */ 385#define TLV_DPCPU_TX0_TAGS (4) /* tx0_tags is valid */ 386#define TLV_DPCPU_TX1_TAGS (8) /* tx1_tags is valid */ 387#define TLV_DPCPU_DL_TAGS (16) /* dl_tags is valid */ 388 /* Consumed by features.c */ 389 uint32_t dut_features; /* All 1s -> leave alone */ 390 int8_t with_rmon; /* 0 -> off, 1 -> on, -1 -> leave alone */ 391 /* Consumed by clocks_hunt.c */ 392 int8_t clk_mode; /* 0 -> off, 1 -> on, -1 -> leave alone */ 393 /* No longer used, superseded by TLV_TAG_DESCRIPTOR_CACHE_CONFIG. */ 394 int8_t rx_dc_size; /* -1 -> leave alone */ 395 int8_t tx_dc_size; 396 int16_t num_q_allocs; 397}; 398 399/* Global port configuration 400 * 401 * This is now deprecated in favour of a platform-provided default 402 * and dynamic config override via tlv_global_port_options. 403 */ 404#define TLV_TAG_GLOBAL_PORT_CONFIG (0x000a0000) 405 406struct tlv_global_port_config { 407 uint32_t tag; 408 uint32_t length; 409 uint32_t ports_per_core; 410 uint32_t max_port_speed; 411}; 412 413 414/* Firmware options. 415 * 416 * This is intended for user-configurable selection of optional firmware 417 * features and variants. 418 * 419 * Initially, this consists only of the satellite CPU firmware variant 420 * selection, but this tag could be extended in the future (using the 421 * tag length to determine whether additional fields are present). 422 */ 423 424#define TLV_TAG_FIRMWARE_OPTIONS (0x100b0000) 425 426struct tlv_firmware_options { 427 uint32_t tag; 428 uint32_t length; 429 uint32_t firmware_variant; 430#define TLV_FIRMWARE_VARIANT_DRIVER_SELECTED (0xffffffff) 431 432/* These are the values for overriding the driver's choice; the definitions 433 * are taken from MCDI so that they don't get out of step. Include 434 * <ci/mgmt/mc_driver_pcol.h> or the equivalent from your driver's tree if 435 * you need to use these constants. 436 */ 437#define TLV_FIRMWARE_VARIANT_FULL_FEATURED MC_CMD_FW_FULL_FEATURED 438#define TLV_FIRMWARE_VARIANT_LOW_LATENCY MC_CMD_FW_LOW_LATENCY 439#define TLV_FIRMWARE_VARIANT_PACKED_STREAM MC_CMD_FW_PACKED_STREAM 440#define TLV_FIRMWARE_VARIANT_HIGH_TX_RATE MC_CMD_FW_HIGH_TX_RATE 441#define TLV_FIRMWARE_VARIANT_PACKED_STREAM_HASH_MODE_1 \ 442 MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 443#define TLV_FIRMWARE_VARIANT_RULES_ENGINE MC_CMD_FW_RULES_ENGINE 444#define TLV_FIRMWARE_VARIANT_DPDK MC_CMD_FW_DPDK 445#define TLV_FIRMWARE_VARIANT_L3XUDP MC_CMD_FW_L3XUDP 446}; 447 448/* Voltage settings 449 * 450 * Intended for boards with A0 silicon where the core voltage may 451 * need tweaking. Most likely set once when the pass voltage is 452 * determined. */ 453 454#define TLV_TAG_0V9_SETTINGS (0x000c0000) 455 456struct tlv_0v9_settings { 457 uint32_t tag; 458 uint32_t length; 459 uint16_t flags; /* Boards with high 0v9 settings may need active cooling */ 460#define TLV_TAG_0V9_REQUIRES_FAN (1) 461 uint16_t target_voltage; /* In millivolts */ 462 /* Since the limits are meant to be centred to the target (and must at least 463 * contain it) they need setting as well. */ 464 uint16_t warn_low; /* In millivolts */ 465 uint16_t warn_high; /* In millivolts */ 466 uint16_t panic_low; /* In millivolts */ 467 uint16_t panic_high; /* In millivolts */ 468}; 469 470 471/* Clock configuration */ 472 473#define TLV_TAG_CLOCK_CONFIG (0x000d0000) /* legacy symbol - do not use */ 474#define TLV_TAG_CLOCK_CONFIG_HUNT TLV_TAG_CLOCK_CONFIG 475 476struct tlv_clock_config { 477 uint32_t tag; 478 uint32_t length; 479 uint16_t clk_sys; /* MHz */ 480 uint16_t clk_dpcpu; /* MHz */ 481 uint16_t clk_icore; /* MHz */ 482 uint16_t clk_pcs; /* MHz */ 483}; 484 485#define TLV_TAG_CLOCK_CONFIG_MEDFORD (0x00100000) 486 487struct tlv_clock_config_medford { 488 uint32_t tag; 489 uint32_t length; 490 uint16_t clk_sys; /* MHz */ 491 uint16_t clk_mc; /* MHz */ 492 uint16_t clk_rmon; /* MHz */ 493 uint16_t clk_vswitch; /* MHz */ 494 uint16_t clk_dpcpu; /* MHz */ 495 uint16_t clk_pcs; /* MHz */ 496}; 497 498 499/* EF10-style global pool of MAC addresses. 500 * 501 * There are <count> addresses, starting at <base_address>, which are 502 * contiguous. Firmware is responsible for allocating addresses from this 503 * pool to ports / PFs as appropriate. 504 */ 505 506#define TLV_TAG_GLOBAL_MAC (0x000e0000) 507 508struct tlv_global_mac { 509 uint32_t tag; 510 uint32_t length; 511 uint8_t base_address[6]; 512 uint16_t reserved1; 513 uint16_t count; 514 uint16_t reserved2; 515}; 516 517#define TLV_TAG_ATB_0V9_TARGET (0x000f0000) /* legacy symbol - do not use */ 518#define TLV_TAG_ATB_0V9_TARGET_HUNT TLV_TAG_ATB_0V9_TARGET 519 520/* The target value for the 0v9 power rail measured on-chip at the 521 * analogue test bus */ 522struct tlv_0v9_atb_target { 523 uint32_t tag; 524 uint32_t length; 525 uint16_t millivolts; 526 uint16_t reserved; 527}; 528 529/* Factory settings for amplitude calibration of the PCIE TX serdes */ 530#define TLV_TAG_TX_PCIE_AMP_CONFIG (0x00220000) 531struct tlv_pcie_tx_amp_config { 532 uint32_t tag; 533 uint32_t length; 534 uint8_t quad_tx_imp2k[4]; 535 uint8_t quad_tx_imp50[4]; 536 uint8_t lane_amp[16]; 537}; 538 539/* Enum to select an OEM and enable additional functionality related to this OEM 540 * (e.g. vendor extensions to VPD, NC-SI etc.) */ 541#define TLV_TAG_OEM (0x00230000) 542struct tlv_oem { 543 uint32_t tag; 544 uint32_t length; 545 uint8_t oem; 546}; 547#define TLV_OEM_NONE 0 548#define TLV_OEM_DELL 1 549 550/* Global PCIe configuration, second revision. This represents the visible PFs 551 * by a bitmap rather than having the number of the highest visible one. As such 552 * it can (for a 16-PF chip) represent a superset of what TLV_TAG_GLOBAL_PCIE_CONFIG 553 * can and it should be used in place of that tag in future (but compatibility with 554 * the old tag will be left in the firmware indefinitely). */ 555 556#define TLV_TAG_GLOBAL_PCIE_CONFIG_R2 (0x10100000) 557 558struct tlv_pcie_config_r2 { 559 uint32_t tag; 560 uint32_t length; 561 uint16_t visible_pfs; /**< Bitmap of visible PFs */ 562 uint16_t pf_aper; /**< BIU aperture for PF BAR2 */ 563 uint16_t vf_aper; /**< BIU aperture for VF BAR0 */ 564 uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */ 565}; 566 567/* Dynamic port mode. 568 * 569 * Allows selecting alternate port configuration for platforms that support it 570 * (e.g. 1x40G vs 2x10G on Milano, 1x40G vs 4x10G on Medford). This affects the 571 * number of externally visible ports (and, hence, PF to port mapping), so must 572 * be done at boot time. 573 * 574 * Port mode naming convention is 575 * 576 * [nports_on_cage0]x[port_lane_width]_[nports_on_cage1]x[port_lane_width] 577 * 578 * Port lane width determines the capabilities (speeds) of the ports, subject 579 * to architecture capabilities (e.g. 25G support) and switch bandwidth 580 * constraints: 581 * - single lane ports can do 25G/10G/1G 582 * - dual lane ports can do 50G/25G/10G/1G (with fallback to 1 lane) 583 * - quad lane ports can do 100G/40G/50G/25G/10G/1G (with fallback to 2 or 1 lanes) 584 585 * This tag supercedes tlv_global_port_config. 586 */ 587 588#define TLV_TAG_GLOBAL_PORT_MODE (0x10110000) 589 590struct tlv_global_port_mode { 591 uint32_t tag; 592 uint32_t length; 593 uint32_t port_mode; 594#define TLV_PORT_MODE_DEFAULT (0xffffffff) /* Default for given platform */ 595 596/* Huntington port modes */ 597#define TLV_PORT_MODE_10G (0) 598#define TLV_PORT_MODE_40G (1) 599#define TLV_PORT_MODE_10G_10G (2) 600#define TLV_PORT_MODE_40G_40G (3) 601#define TLV_PORT_MODE_10G_10G_10G_10G (4) 602#define TLV_PORT_MODE_40G_10G_10G (6) 603#define TLV_PORT_MODE_10G_10G_40G (7) 604 605/* Medford (and later) port modes */ 606#define TLV_PORT_MODE_1x1_NA (0) /* Single 10G/25G on mdi0 */ 607#define TLV_PORT_MODE_1x4_NA (1) /* Single 100G/40G on mdi0 */ 608#define TLV_PORT_MODE_NA_1x4 (22) /* Single 100G/40G on mdi1 */ 609#define TLV_PORT_MODE_1x2_NA (10) /* Single 50G on mdi0 */ 610#define TLV_PORT_MODE_NA_1x2 (11) /* Single 50G on mdi1 */ 611#define TLV_PORT_MODE_1x1_1x1 (2) /* Single 10G/25G on mdi0, single 10G/25G on mdi1 */ 612#define TLV_PORT_MODE_1x4_1x4 (3) /* Single 40G on mdi0, single 40G on mdi1 */ 613#define TLV_PORT_MODE_2x1_2x1 (5) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1 */ 614#define TLV_PORT_MODE_4x1_NA (4) /* Quad 10G/25G on mdi0 */ 615#define TLV_PORT_MODE_NA_4x1 (8) /* Quad 10G/25G on mdi1 */ 616#define TLV_PORT_MODE_1x4_2x1 (6) /* Single 40G on mdi0, dual 10G/25G on mdi1 */ 617#define TLV_PORT_MODE_2x1_1x4 (7) /* Dual 10G/25G on mdi0, single 40G on mdi1 */ 618#define TLV_PORT_MODE_1x2_1x2 (12) /* Single 50G on mdi0, single 50G on mdi1 */ 619#define TLV_PORT_MODE_2x2_NA (13) /* Dual 50G on mdi0 */ 620#define TLV_PORT_MODE_NA_2x2 (14) /* Dual 50G on mdi1 */ 621#define TLV_PORT_MODE_1x4_1x2 (15) /* Single 40G on mdi0, single 50G on mdi1 */ 622#define TLV_PORT_MODE_1x2_1x4 (16) /* Single 50G on mdi0, single 40G on mdi1 */ 623#define TLV_PORT_MODE_1x2_2x1 (17) /* Single 50G on mdi0, dual 10G/25G on mdi1 */ 624#define TLV_PORT_MODE_2x1_1x2 (18) /* Dual 10G/25G on mdi0, single 50G on mdi1 */ 625 626/* Snapper-only Medford2 port modes. 627 * These modes are eftest only, to allow snapper explicit 628 * selection between multi-channel and LLPCS. In production, 629 * this selection is automatic and outside world should not 630 * care about LLPCS. 631 */ 632#define TLV_PORT_MODE_2x1_2x1_LL (19) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1, low-latency PCS */ 633#define TLV_PORT_MODE_4x1_NA_LL (20) /* Quad 10G/25G on mdi0, low-latency PCS */ 634#define TLV_PORT_MODE_NA_4x1_LL (21) /* Quad 10G/25G on mdi1, low-latency PCS */ 635#define TLV_PORT_MODE_1x1_NA_LL (23) /* Single 10G/25G on mdi0, low-latency PCS */ 636#define TLV_PORT_MODE_1x1_1x1_LL (24) /* Single 10G/25G on mdi0, single 10G/25G on mdi1, low-latency PCS */ 637#define TLV_PORT_MODE_BUG63720_DO_NOT_USE (9) /* bug63720: Do not use */ 638#define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL 639 640/* Deprecated Medford aliases - DO NOT USE IN NEW CODE */ 641#define TLV_PORT_MODE_10G_10G_10G_10G_Q (5) 642#define TLV_PORT_MODE_10G_10G_10G_10G_Q1 (4) 643#define TLV_PORT_MODE_10G_10G_10G_10G_Q2 (8) 644#define TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2 (9) 645 646#define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL 647}; 648 649/* Type of the v-switch created implicitly by the firmware */ 650 651#define TLV_TAG_VSWITCH_TYPE(port) (0x10120000 + (port)) 652 653struct tlv_vswitch_type { 654 uint32_t tag; 655 uint32_t length; 656 uint32_t vswitch_type; 657#define TLV_VSWITCH_TYPE_DEFAULT (0xffffffff) /* Firmware default; equivalent to no TLV present for a given port */ 658#define TLV_VSWITCH_TYPE_NONE (0) 659#define TLV_VSWITCH_TYPE_VLAN (1) 660#define TLV_VSWITCH_TYPE_VEB (2) 661#define TLV_VSWITCH_TYPE_VEPA (3) 662#define TLV_VSWITCH_TYPE_MUX (4) 663#define TLV_VSWITCH_TYPE_TEST (5) 664}; 665 666/* A VLAN tag for the v-port created implicitly by the firmware */ 667 668#define TLV_TAG_VPORT_VLAN_TAG(pf) (0x10130000 + (pf)) 669 670struct tlv_vport_vlan_tag { 671 uint32_t tag; 672 uint32_t length; 673 uint32_t vlan_tag; 674#define TLV_VPORT_NO_VLAN_TAG (0xFFFFFFFF) /* Default in the absence of TLV for a given PF */ 675}; 676 677/* Offset to be applied to the 0v9 setting, wherever it came from */ 678 679#define TLV_TAG_ATB_0V9_OFFSET (0x10140000) 680 681struct tlv_0v9_atb_offset { 682 uint32_t tag; 683 uint32_t length; 684 int16_t offset_millivolts; 685 uint16_t reserved; 686}; 687 688/* A privilege mask given on reset to all non-admin PCIe functions (that is other than first-PF-per-port). 689 * The meaning of particular bits is defined in mcdi_ef10.yml under MC_CMD_PRIVILEGE_MASK, see also bug 44583. 690 * TLV_TAG_PRIVILEGE_MASK_ADD specifies bits that should be added (ORed) to firmware default while 691 * TLV_TAG_PRIVILEGE_MASK_REM specifies bits that should be removed (ANDed) from firmware default: 692 * Initial_privilege_mask = (firmware_default_mask | privilege_mask_add) & ~privilege_mask_rem */ 693 694#define TLV_TAG_PRIVILEGE_MASK (0x10150000) /* legacy symbol - do not use */ 695 696struct tlv_privilege_mask { /* legacy structure - do not use */ 697 uint32_t tag; 698 uint32_t length; 699 uint32_t privilege_mask; 700}; 701 702#define TLV_TAG_PRIVILEGE_MASK_ADD (0x10150000) 703 704struct tlv_privilege_mask_add { 705 uint32_t tag; 706 uint32_t length; 707 uint32_t privilege_mask_add; 708}; 709 710#define TLV_TAG_PRIVILEGE_MASK_REM (0x10160000) 711 712struct tlv_privilege_mask_rem { 713 uint32_t tag; 714 uint32_t length; 715 uint32_t privilege_mask_rem; 716}; 717 718/* Additional privileges given to all PFs. 719 * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */ 720 721#define TLV_TAG_PRIVILEGE_MASK_ADD_ALL_PFS (0x10190000) 722 723struct tlv_privilege_mask_add_all_pfs { 724 uint32_t tag; 725 uint32_t length; 726 uint32_t privilege_mask_add; 727}; 728 729/* Additional privileges given to a selected PF. 730 * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */ 731 732#define TLV_TAG_PRIVILEGE_MASK_ADD_SINGLE_PF(pf) (0x101A0000 + (pf)) 733 734struct tlv_privilege_mask_add_single_pf { 735 uint32_t tag; 736 uint32_t length; 737 uint32_t privilege_mask_add; 738}; 739 740/* Turning on/off the PFIOV mode. 741 * This tag only takes effect if TLV_TAG_VSWITCH_TYPE is missing or set to DEFAULT. */ 742 743#define TLV_TAG_PFIOV(port) (0x10170000 + (port)) 744 745struct tlv_pfiov { 746 uint32_t tag; 747 uint32_t length; 748 uint32_t pfiov; 749#define TLV_PFIOV_OFF (0) /* Default */ 750#define TLV_PFIOV_ON (1) 751}; 752 753/* Multicast filter chaining mode selection. 754 * 755 * When enabled, multicast packets are delivered to all recipients of all 756 * matching multicast filters, with the exception that IP multicast filters 757 * will steal traffic from MAC multicast filters on a per-function basis. 758 * (New behaviour.) 759 * 760 * When disabled, multicast packets will always be delivered only to the 761 * recipients of the highest priority matching multicast filter. 762 * (Legacy behaviour.) 763 * 764 * The DEFAULT mode (which is the same as the tag not being present at all) 765 * is equivalent to ENABLED in production builds, and DISABLED in eftest 766 * builds. 767 * 768 * This option is intended to provide run-time control over this feature 769 * while it is being stabilised and may be withdrawn at some point in the 770 * future; the new behaviour is intended to become the standard behaviour. 771 */ 772 773#define TLV_TAG_MCAST_FILTER_CHAINING (0x10180000) 774 775struct tlv_mcast_filter_chaining { 776 uint32_t tag; 777 uint32_t length; 778 uint32_t mode; 779#define TLV_MCAST_FILTER_CHAINING_DEFAULT (0xffffffff) 780#define TLV_MCAST_FILTER_CHAINING_DISABLED (0) 781#define TLV_MCAST_FILTER_CHAINING_ENABLED (1) 782}; 783 784/* Pacer rate limit per PF */ 785#define TLV_TAG_RATE_LIMIT(pf) (0x101b0000 + (pf)) 786 787struct tlv_rate_limit { 788 uint32_t tag; 789 uint32_t length; 790 uint32_t rate_mbps; 791}; 792 793/* OCSD Enable/Disable 794 * 795 * This setting allows OCSD to be disabled. This is a requirement for HP 796 * servers to support PCI passthrough for virtualization. 797 * 798 * The DEFAULT mode (which is the same as the tag not being present) is 799 * equivalent to ENABLED. 800 * 801 * This option is not used by the MCFW, and is entirely handled by the various 802 * drivers that support OCSD, by reading the setting before they attempt 803 * to enable OCSD. 804 * 805 * bit0: OCSD Disabled/Enabled 806 */ 807 808#define TLV_TAG_OCSD (0x101C0000) 809 810struct tlv_ocsd { 811 uint32_t tag; 812 uint32_t length; 813 uint32_t mode; 814#define TLV_OCSD_DISABLED 0 815#define TLV_OCSD_ENABLED 1 /* Default */ 816}; 817 818/* Descriptor cache config. 819 * 820 * Sets the sizes of the TX and RX descriptor caches as a power of 2. It also 821 * sets the total number of VIs. When the number of VIs is reduced VIs are taken 822 * away from the highest numbered port first, so a vi_count of 1024 means 1024 823 * VIs on the first port and 0 on the second (on a Torino). 824 */ 825 826#define TLV_TAG_DESCRIPTOR_CACHE_CONFIG (0x101d0000) 827 828struct tlv_descriptor_cache_config { 829 uint32_t tag; 830 uint32_t length; 831 uint8_t rx_desc_cache_size; 832 uint8_t tx_desc_cache_size; 833 uint16_t vi_count; 834}; 835#define TLV_DESC_CACHE_DEFAULT (0xff) 836#define TLV_VI_COUNT_DEFAULT (0xffff) 837 838/* RX event merging config (read batching). 839 * 840 * Sets the global maximum number of events for the merging bins, and the 841 * global timeout configuration for the bins. 842 */ 843 844#define TLV_TAG_RX_EVENT_MERGING_CONFIG (0x101e0000) 845 846struct tlv_rx_event_merging_config { 847 uint32_t tag; 848 uint32_t length; 849 uint32_t max_events; 850#define TLV_RX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1) 851 uint32_t timeout_ns; 852}; 853#define TLV_RX_EVENT_MERGING_MAX_EVENTS_DEFAULT (0xffffffff) 854#define TLV_RX_EVENT_MERGING_TIMEOUT_NS_DEFAULT (0xffffffff) 855 856#define TLV_TAG_PCIE_LINK_SETTINGS (0x101f0000) 857struct tlv_pcie_link_settings { 858 uint32_t tag; 859 uint32_t length; 860 uint16_t gen; /* Target PCIe generation: 1, 2, 3 */ 861 uint16_t width; /* Number of lanes */ 862}; 863 864/* TX event merging config. 865 * 866 * Sets the global maximum number of events for the merging bins, and the 867 * global timeout configuration for the bins, and the global timeout for 868 * empty queues. 869 */ 870#define TLV_TAG_TX_EVENT_MERGING_CONFIG (0x10210000) 871struct tlv_tx_event_merging_config { 872 uint32_t tag; 873 uint32_t length; 874 uint32_t max_events; 875#define TLV_TX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1) 876 uint32_t timeout_ns; 877 uint32_t qempty_timeout_ns; /* Medford only */ 878}; 879#define TLV_TX_EVENT_MERGING_MAX_EVENTS_DEFAULT (0xffffffff) 880#define TLV_TX_EVENT_MERGING_TIMEOUT_NS_DEFAULT (0xffffffff) 881#define TLV_TX_EVENT_MERGING_QEMPTY_TIMEOUT_NS_DEFAULT (0xffffffff) 882 883#define TLV_TAG_LICENSE (0x30800000) 884 885typedef struct tlv_license { 886 uint32_t tag; 887 uint32_t length; 888 uint8_t data[]; 889} tlv_license_t; 890 891/* TSA NIC IP address configuration (DEPRECATED) 892 * 893 * Sets the TSA NIC IP address statically via configuration tool or dynamically 894 * via DHCP via snooping based on the mode selection (0=Static, 1=DHCP, 2=Snoop) 895 * 896 * NOTE: This TAG is temporarily placed in the dynamic config partition and will 897 * be moved to a private partition during TSA development. It is not used in any 898 * released code yet. 899 */ 900 901#define TLV_TAG_TMP_TSAN_CONFIG (0x10220000) /* DEPRECATED */ 902 903#define TLV_TSAN_IP_MODE_STATIC (0) 904#define TLV_TSAN_IP_MODE_DHCP (1) 905#define TLV_TSAN_IP_MODE_SNOOP (2) 906typedef struct tlv_tsan_config { 907 uint32_t tag; 908 uint32_t length; 909 uint32_t mode; 910 uint32_t ip; 911 uint32_t netmask; 912 uint32_t gateway; 913 uint32_t port; 914 uint32_t bind_retry; /* DEPRECATED */ 915 uint32_t bind_bkout; /* DEPRECATED */ 916} tlv_tsan_config_t; 917 918/* TSA Controller IP address configuration (DEPRECATED) 919 * 920 * Sets the TSA Controller IP address statically via configuration tool 921 * 922 * NOTE: This TAG is temporarily placed in the dynamic config partition and will 923 * be moved to a private partition during TSA development. It is not used in any 924 * released code yet. 925 */ 926 927#define TLV_TAG_TMP_TSAC_CONFIG (0x10230000) /* DEPRECATED */ 928 929#define TLV_MAX_TSACS (4) 930typedef struct tlv_tsac_config { 931 uint32_t tag; 932 uint32_t length; 933 uint32_t num_tsacs; 934 uint32_t ip[TLV_MAX_TSACS]; 935 uint32_t port[TLV_MAX_TSACS]; 936} tlv_tsac_config_t; 937 938/* Binding ticket (DEPRECATED) 939 * 940 * Sets the TSA NIC binding ticket used for binding process between the TSA NIC 941 * and the TSA Controller 942 * 943 * NOTE: This TAG is temporarily placed in the dynamic config partition and will 944 * be moved to a private partition during TSA development. It is not used in any 945 * released code yet. 946 */ 947 948#define TLV_TAG_TMP_BINDING_TICKET (0x10240000) /* DEPRECATED */ 949 950typedef struct tlv_binding_ticket { 951 uint32_t tag; 952 uint32_t length; 953 uint8_t bytes[]; 954} tlv_binding_ticket_t; 955 956/* Solarflare private key (DEPRECATED) 957 * 958 * Sets the Solareflare private key used for signing during the binding process 959 * 960 * NOTE: This TAG is temporarily placed in the dynamic config partition and will 961 * be moved to a private partition during TSA development. It is not used in any 962 * released code yet. 963 */ 964 965#define TLV_TAG_TMP_PIK_SF (0x10250000) /* DEPRECATED */ 966 967typedef struct tlv_pik_sf { 968 uint32_t tag; 969 uint32_t length; 970 uint8_t bytes[]; 971} tlv_pik_sf_t; 972 973/* CA root certificate (DEPRECATED) 974 * 975 * Sets the CA root certificate used for TSA Controller verfication during 976 * TLS connection setup between the TSA NIC and the TSA Controller 977 * 978 * NOTE: This TAG is temporarily placed in the dynamic config partition and will 979 * be moved to a private partition during TSA development. It is not used in any 980 * released code yet. 981 */ 982 983#define TLV_TAG_TMP_CA_ROOT_CERT (0x10260000) /* DEPRECATED */ 984 985typedef struct tlv_ca_root_cert { 986 uint32_t tag; 987 uint32_t length; 988 uint8_t bytes[]; 989} tlv_ca_root_cert_t; 990 991/* Tx vFIFO Low latency configuration 992 * 993 * To keep the desired booting behaviour for the switch, it just requires to 994 * know if the low latency mode is enabled. 995 */ 996 997#define TLV_TAG_TX_VFIFO_ULL_MODE (0x10270000) 998struct tlv_tx_vfifo_ull_mode { 999 uint32_t tag; 1000 uint32_t length;
1001 uint8_t mode; 1002#define TLV_TX_VFIFO_ULL_MODE_DEFAULT 0 1003}; 1004 1005/* BIU mode 1006 * 1007 * Medford2 tag for selecting VI window decode (see values below) 1008 */ 1009#define TLV_TAG_BIU_VI_WINDOW_MODE (0x10280000) 1010struct tlv_biu_vi_window_mode { 1011 uint32_t tag; 1012 uint32_t length; 1013 uint8_t mode; 1014#define TLV_BIU_VI_WINDOW_MODE_8K 0 /* 8k per VI, CTPIO not mapped, medford/hunt compatible */ 1015#define TLV_BIU_VI_WINDOW_MODE_16K 1 /* 16k per VI, CTPIO mapped */ 1016#define TLV_BIU_VI_WINDOW_MODE_64K 2 /* 64k per VI, CTPIO mapped, POWER-friendly */ 1017}; 1018 1019/* FastPD mode 1020 * 1021 * Medford2 tag for configuring the FastPD mode (see values below) 1022 */ 1023#define TLV_TAG_FASTPD_MODE(port) (0x10290000 + (port)) 1024struct tlv_fastpd_mode { 1025 uint32_t tag; 1026 uint32_t length; 1027 uint8_t mode; 1028#define TLV_FASTPD_MODE_SOFT_ALL 0 /* All packets to the SoftPD */ 1029#define TLV_FASTPD_MODE_FAST_ALL 1 /* All packets to the FastPD */ 1030#define TLV_FASTPD_MODE_FAST_SUPPORTED 2 /* Supported packet types to the FastPD; everything else to the SoftPD */ 1031}; 1032 1033/* L3xUDP datapath firmware UDP port configuration 1034 * 1035 * Sets the list of UDP ports on which the encapsulation will be handled. 1036 * The number of ports in the list is implied by the length of the TLV item. 1037 */ 1038#define TLV_TAG_L3XUDP_PORTS (0x102a0000) 1039struct tlv_l3xudp_ports { 1040 uint32_t tag; 1041 uint32_t length; 1042 uint16_t ports[]; 1043#define TLV_TAG_L3XUDP_PORTS_MAX_NUM_PORTS 16 1044}; 1045 1046/* Wake on LAN setting 1047 * 1048 * Enables the Wake On Lan (WoL) functionality on the given port. This will be 1049 * a persistent setting for manageability firmware. Drivers have direct access 1050 * to WoL using MCDI. 1051 */ 1052#define TLV_TAG_WAKE_ON_LAN(port) (0x102b0000 + (port)) 1053struct tlv_wake_on_lan { 1054 uint32_t tag; 1055 uint32_t length; 1056 uint8_t mode; 1057 uint8_t bytes[]; 1058#define TLV_WAKE_ON_LAN_MODE_DISABLED 0 1059#define TLV_WAKE_ON_LAN_MODE_MAGIC_PACKET 1 1060#define TLV_WAKE_ON_LAN_MAX_NUM_BYTES 255 1061}; 1062 1063#endif /* CI_MGMT_TLV_LAYOUT_H */ 1064