LXR dpdk/drivers/net/atlantic/hw_atl/hw_atl

   1/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) */
   2/* Copyright (C) 2014-2017 aQuantia Corporation. */
   3
   4/* File hw_atl_llh.h: Declarations of bitfield and register access functions for
   5 * Atlantic registers.
   6 */
   7
   8#ifndef HW_ATL_LLH_H
   9#define HW_ATL_LLH_H
  10
  11#include "../atl_types.h"
  12
  13struct aq_hw_s;
  14
  15/* global */
  16
  17/* set global microprocessor semaphore */
  18void hw_atl_reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw,  u32 glb_cpu_sem,
  19                                u32 semaphore);
  20
  21/* get global microprocessor semaphore */
  22u32 hw_atl_reg_glb_cpu_sem_get(struct aq_hw_s *aq_hw, u32 semaphore);
  23
  24/* set global register reset disable */
  25void hw_atl_glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis);
  26
  27/* set soft reset */
  28void hw_atl_glb_soft_res_set(struct aq_hw_s *aq_hw, u32 soft_res);
  29
  30/* get soft reset */
  31u32 hw_atl_glb_soft_res_get(struct aq_hw_s *aq_hw);
  32
  33/* stats */
  34
  35u32 hw_atl_rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw);
  36
  37/* get rx dma good octet counter lsw */
  38u32 hw_atl_stats_rx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw);
  39
  40/* get rx dma good packet counter lsw */
  41u32 hw_atl_stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw);
  42
  43/* get tx dma good octet counter lsw */
  44u32 hw_atl_stats_tx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw);
  45
  46/* get tx dma good packet counter lsw */
  47u32 hw_atl_stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw);
  48
  49/* get rx dma good octet counter msw */
  50u32 hw_atl_stats_rx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw);
  51
  52/* get rx dma good packet counter msw */
  53u32 hw_atl_stats_rx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw);
  54
  55/* get tx dma good octet counter msw */
  56u32 hw_atl_stats_tx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw);
  57
  58/* get tx dma good packet counter msw */
  59u32 hw_atl_stats_tx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw);
  60
  61/* get msm rx errors counter register */
  62u32 hw_atl_reg_mac_msm_rx_errs_cnt_get(struct aq_hw_s *aq_hw);
  63
  64/* get msm rx unicast frames counter register */
  65u32 hw_atl_reg_mac_msm_rx_ucst_frm_cnt_get(struct aq_hw_s *aq_hw);
  66
  67/* get msm rx multicast frames counter register */
  68u32 hw_atl_reg_mac_msm_rx_mcst_frm_cnt_get(struct aq_hw_s *aq_hw);
  69
  70/* get msm rx broadcast frames counter register */
  71u32 hw_atl_reg_mac_msm_rx_bcst_frm_cnt_get(struct aq_hw_s *aq_hw);
  72
  73/* get msm rx broadcast octets counter register 1 */
  74u32 hw_atl_reg_mac_msm_rx_bcst_octets_counter1get(struct aq_hw_s *aq_hw);
  75
  76/* get msm rx unicast octets counter register 0 */
  77u32 hw_atl_reg_mac_msm_rx_ucst_octets_counter0get(struct aq_hw_s *aq_hw);
  78
  79/* get rx dma statistics counter 7 */
  80u32 hw_atl_reg_rx_dma_stat_counter7get(struct aq_hw_s *aq_hw);
  81
  82/* get msm tx errors counter register */
  83u32 hw_atl_reg_mac_msm_tx_errs_cnt_get(struct aq_hw_s *aq_hw);
  84
  85/* get msm tx unicast frames counter register */
  86u32 hw_atl_reg_mac_msm_tx_ucst_frm_cnt_get(struct aq_hw_s *aq_hw);
  87
  88/* get msm tx multicast frames counter register */
  89u32 hw_atl_reg_mac_msm_tx_mcst_frm_cnt_get(struct aq_hw_s *aq_hw);
  90
  91/* get msm tx broadcast frames counter register */
  92u32 hw_atl_reg_mac_msm_tx_bcst_frm_cnt_get(struct aq_hw_s *aq_hw);
  93
  94/* get msm tx multicast octets counter register 1 */
  95u32 hw_atl_reg_mac_msm_tx_mcst_octets_counter1get(struct aq_hw_s *aq_hw);
  96
  97/* get msm tx broadcast octets counter register 1 */
  98u32 hw_atl_reg_mac_msm_tx_bcst_octets_counter1get(struct aq_hw_s *aq_hw);
  99
 100/* get msm tx unicast octets counter register 0 */
 101u32 hw_atl_reg_mac_msm_tx_ucst_octets_counter0get(struct aq_hw_s *aq_hw);
 102
 103/* get global mif identification */
 104u32 hw_atl_reg_glb_mif_id_get(struct aq_hw_s *aq_hw);
 105
 106/* interrupt */
 107
 108/* set interrupt auto mask lsw */
 109void hw_atl_itr_irq_auto_masklsw_set(struct aq_hw_s *aq_hw,
 110                                     u32 irq_auto_masklsw);
 111
 112/* set interrupt mapping enable rx */
 113void hw_atl_itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx,
 114                                  u32 rx);
 115
 116/* set interrupt mapping enable tx */
 117void hw_atl_itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx,
 118                                  u32 tx);
 119
 120/* set interrupt mapping rx */
 121void hw_atl_itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx);
 122
 123/* set interrupt mapping tx */
 124void hw_atl_itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx);
 125
 126/* set interrupt mask clear lsw */
 127void hw_atl_itr_irq_msk_clearlsw_set(struct aq_hw_s *aq_hw,
 128                                     u32 irq_msk_clearlsw);
 129
 130/* set interrupt mask set lsw */
 131void hw_atl_itr_irq_msk_setlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_setlsw);
 132
 133/* set interrupt register reset disable */
 134void hw_atl_itr_irq_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 irq_reg_res_dis);
 135
 136/* set interrupt status clear lsw */
 137void hw_atl_itr_irq_status_clearlsw_set(struct aq_hw_s *aq_hw,
 138                                        u32 irq_status_clearlsw);
 139
 140/* get interrupt status lsw */
 141u32 hw_atl_itr_irq_statuslsw_get(struct aq_hw_s *aq_hw);
 142
 143/* get reset interrupt */
 144u32 hw_atl_itr_res_irq_get(struct aq_hw_s *aq_hw);
 145
 146/* set reset interrupt */
 147void hw_atl_itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq);
 148
 149/* rdm */
 150
 151/* set cpu id */
 152void hw_atl_rdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca);
 153
 154/* set rx dca enable */
 155void hw_atl_rdm_rx_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_dca_en);
 156
 157/* set rx dca mode */
 158void hw_atl_rdm_rx_dca_mode_set(struct aq_hw_s *aq_hw, u32 rx_dca_mode);
 159
 160/* set rx descriptor data buffer size */
 161void hw_atl_rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw,
 162                                           u32 rx_desc_data_buff_size,
 163                                    u32 descriptor);
 164
 165/* set rx descriptor dca enable */
 166void hw_atl_rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en,
 167                                   u32 dca);
 168
 169/* set rx descriptor enable */
 170void hw_atl_rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en,
 171                               u32 descriptor);
 172
 173/* set rx descriptor header splitting */
 174void hw_atl_rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw,
 175                                           u32 rx_desc_head_splitting,
 176                                    u32 descriptor);
 177
 178/* get rx descriptor head pointer */
 179u32 hw_atl_rdm_rx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor);
 180
 181/* set rx descriptor length */
 182void hw_atl_rdm_rx_desc_len_set(struct aq_hw_s *aq_hw, u32 rx_desc_len,
 183                                u32 descriptor);
 184
 185/* set rx descriptor write-back interrupt enable */
 186void hw_atl_rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
 187                                         u32 rx_desc_wr_wb_irq_en);
 188
 189/* set rx header dca enable */
 190void hw_atl_rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en,
 191                                   u32 dca);
 192
 193/* set rx payload dca enable */
 194void hw_atl_rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en,
 195                                  u32 dca);
 196
 197/* set rx descriptor header buffer size */
 198void hw_atl_rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw,
 199                                           u32 rx_desc_head_buff_size,
 200                                           u32 descriptor);
 201
 202/* set rx descriptor reset */
 203void hw_atl_rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res,
 204                                u32 descriptor);
 205
 206/* Set RDM Interrupt Moderation Enable */
 207void hw_atl_rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
 208                                      u32 rdm_intr_moder_en);
 209
 210/* reg */
 211
 212/* set general interrupt mapping register */
 213void hw_atl_reg_gen_irq_map_set(struct aq_hw_s *aq_hw, u32 gen_intr_map,
 214                                u32 regidx);
 215
 216/* get general interrupt status register */
 217u32 hw_atl_reg_gen_irq_status_get(struct aq_hw_s *aq_hw);
 218
 219/* set interrupt global control register */
 220void hw_atl_reg_irq_glb_ctl_set(struct aq_hw_s *aq_hw, u32 intr_glb_ctl);
 221
 222/* set interrupt throttle register */
 223void hw_atl_reg_irq_thr_set(struct aq_hw_s *aq_hw, u32 intr_thr, u32 throttle);
 224
 225/* set rx dma descriptor base address lsw */
 226void hw_atl_reg_rx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
 227                                               u32 rx_dma_desc_base_addrlsw,
 228                                        u32 descriptor);
 229
 230/* set rx dma descriptor base address msw */
 231void hw_atl_reg_rx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
 232                                               u32 rx_dma_desc_base_addrmsw,
 233                                        u32 descriptor);
 234
 235/* get rx dma descriptor status register */
 236u32 hw_atl_reg_rx_dma_desc_status_get(struct aq_hw_s *aq_hw, u32 descriptor);
 237
 238/* set rx dma descriptor tail pointer register */
 239void hw_atl_reg_rx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
 240                                         u32 rx_dma_desc_tail_ptr,
 241                                  u32 descriptor);
 242
 243/* set rx filter multicast filter mask register */
 244void hw_atl_reg_rx_flr_mcst_flr_msk_set(struct aq_hw_s *aq_hw,
 245                                        u32 rx_flr_mcst_flr_msk);
 246
 247/* set rx filter multicast filter register */
 248void hw_atl_reg_rx_flr_mcst_flr_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr,
 249                                    u32 filter);
 250
 251/* set rx filter rss control register 1 */
 252void hw_atl_reg_rx_flr_rss_control1set(struct aq_hw_s *aq_hw,
 253                                       u32 rx_flr_rss_control1);
 254
 255/* Set RX Filter Control Register 2 */
 256void hw_atl_reg_rx_flr_control2_set(struct aq_hw_s *aq_hw, u32 rx_flr_control2);
 257
 258/* Set RX Interrupt Moderation Control Register */
 259void hw_atl_reg_rx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
 260                                       u32 rx_intr_moderation_ctl,
 261                                u32 queue);
 262
 263/* set tx dma debug control */
 264void hw_atl_reg_tx_dma_debug_ctl_set(struct aq_hw_s *aq_hw,
 265                                     u32 tx_dma_debug_ctl);
 266
 267/* set tx dma descriptor base address lsw */
 268void hw_atl_reg_tx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
 269                                               u32 tx_dma_desc_base_addrlsw,
 270                                        u32 descriptor);
 271
 272/* set tx dma descriptor base address msw */
 273void hw_atl_reg_tx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
 274                                               u32 tx_dma_desc_base_addrmsw,
 275                                        u32 descriptor);
 276
 277/* set tx dma descriptor tail pointer register */
 278void hw_atl_reg_tx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
 279                                         u32 tx_dma_desc_tail_ptr,
 280                                         u32 descriptor);
 281
 282/* Set TX Interrupt Moderation Control Register */
 283void hw_atl_reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
 284                                       u32 tx_intr_moderation_ctl,
 285                                       u32 queue);
 286
 287/* set global microprocessor scratch pad */
 288void hw_atl_reg_glb_cpu_scratch_scp_set(struct aq_hw_s *aq_hw,
 289                                        u32 glb_cpu_scratch_scp,
 290                                        u32 scratch_scp);
 291
 292/* rpb */
 293
 294/* set dma system loopback */
 295void hw_atl_rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk);
 296
 297/* set rx traffic class mode */
 298void hw_atl_rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw,
 299                                           u32 rx_traf_class_mode);
 300
 301/* get rx traffic class mode */
 302u32 hw_atl_rpb_rpf_rx_traf_class_mode_get(struct aq_hw_s *aq_hw);
 303
 304/* set rx buffer enable */
 305void hw_atl_rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en);
 306
 307/* set rx buffer high threshold (per tc) */
 308void hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
 309                                                u32 rx_buff_hi_threshold_per_tc,
 310                                                u32 buffer);
 311
 312/* set rx buffer low threshold (per tc) */
 313void hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
 314                                                u32 rx_buff_lo_threshold_per_tc,
 315                                         u32 buffer);
 316
 317/* set rx flow control mode */
 318void hw_atl_rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw,
 319                                     u32 rx_flow_ctl_mode);
 320
 321/* set rx packet buffer size (per tc) */
 322void hw_atl_rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
 323                                            u32 rx_pkt_buff_size_per_tc,
 324                                            u32 buffer);
 325
 326/* set rx xoff enable (per tc) */
 327void hw_atl_rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw,
 328                                      u32 rx_xoff_en_per_tc,
 329                                      u32 buffer);
 330
 331/* rpf */
 332
 333/* set l2 broadcast count threshold */
 334void hw_atl_rpfl2broadcast_count_threshold_set(struct aq_hw_s *aq_hw,
 335                                               u32 l2broadcast_count_threshold);
 336
 337/* set l2 broadcast enable */
 338void hw_atl_rpfl2broadcast_en_set(struct aq_hw_s *aq_hw, u32 l2broadcast_en);
 339
 340/* set l2 broadcast filter action */
 341void hw_atl_rpfl2broadcast_flr_act_set(struct aq_hw_s *aq_hw,
 342                                       u32 l2broadcast_flr_act);
 343
 344/* set l2 multicast filter enable */
 345void hw_atl_rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw,
 346                                      u32 l2multicast_flr_en,
 347                                      u32 filter);
 348
 349/* set l2 promiscuous mode enable */
 350void hw_atl_rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw,
 351                                         u32 l2promiscuous_mode_en);
 352
 353/* set l2 unicast filter action */
 354void hw_atl_rpfl2unicast_flr_act_set(struct aq_hw_s *aq_hw,
 355                                     u32 l2unicast_flr_act,
 356                                     u32 filter);
 357
 358/* set l2 unicast filter enable */
 359void hw_atl_rpfl2_uc_flr_en_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_en,
 360                                u32 filter);
 361
 362/* set l2 unicast destination address lsw */
 363void hw_atl_rpfl2unicast_dest_addresslsw_set(struct aq_hw_s *aq_hw,
 364                                             u32 l2unicast_dest_addresslsw,
 365                                             u32 filter);
 366
 367/* set l2 unicast destination address msw */
 368void hw_atl_rpfl2unicast_dest_addressmsw_set(struct aq_hw_s *aq_hw,
 369                                             u32 l2unicast_dest_addressmsw,
 370                                      u32 filter);
 371
 372/* Set L2 Accept all Multicast packets */
 373void hw_atl_rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw,
 374                                            u32 l2_accept_all_mc_packets);
 375
 376/* set user-priority tc mapping */
 377void hw_atl_rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw,
 378                                             u32 user_priority_tc_map, u32 tc);
 379
 380/* set rss key address */
 381void hw_atl_rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr);
 382
 383/* set rss key write data */
 384void hw_atl_rpf_rss_key_wr_data_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_data);
 385
 386/* get rss key write enable */
 387u32 hw_atl_rpf_rss_key_wr_en_get(struct aq_hw_s *aq_hw);
 388
 389/* set rss key write enable */
 390void hw_atl_rpf_rss_key_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_en);
 391
 392/* set rss redirection table address */
 393void hw_atl_rpf_rss_redir_tbl_addr_set(struct aq_hw_s *aq_hw,
 394                                       u32 rss_redir_tbl_addr);
 395
 396/* set rss redirection table write data */
 397void hw_atl_rpf_rss_redir_tbl_wr_data_set(struct aq_hw_s *aq_hw,
 398                                          u32 rss_redir_tbl_wr_data);
 399
 400/* get rss redirection write enable */
 401u32 hw_atl_rpf_rss_redir_wr_en_get(struct aq_hw_s *aq_hw);
 402
 403/* set rss redirection write enable */
 404void hw_atl_rpf_rss_redir_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_redir_wr_en);
 405
 406/* set tpo to rpf system loopback */
 407void hw_atl_rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw_s *aq_hw,
 408                                       u32 tpo_to_rpf_sys_lbk);
 409
 410/* set vlan inner ethertype */
 411void hw_atl_rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, u32 vlan_inner_etht);
 412
 413/* set vlan outer ethertype */
 414void hw_atl_rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht);
 415
 416/* set vlan promiscuous mode enable */
 417void hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw,
 418                                      u32 vlan_prom_mode_en);
 419
 420/* Set VLAN untagged action */
 421void hw_atl_rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw,
 422                                      u32 vlan_untagged_act);
 423
 424/* Set VLAN accept untagged packets */
 425void hw_atl_rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw,
 426                                                 u32 vlan_acc_untagged_packets);
 427
 428/* Set VLAN filter enable */
 429void hw_atl_rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, u32 vlan_flr_en,
 430                                u32 filter);
 431
 432/* Set VLAN Filter Action */
 433void hw_atl_rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_filter_act,
 434                                 u32 filter);
 435
 436/* Set VLAN ID Filter */
 437void hw_atl_rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr,
 438                                u32 filter);
 439
 440/* set ethertype filter enable */
 441void hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en,
 442                                u32 filter);
 443
 444/* set  ethertype user-priority enable */
 445void hw_atl_rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw,
 446                                          u32 etht_user_priority_en,
 447                                          u32 filter);
 448
 449/* set  ethertype rx queue enable */
 450void hw_atl_rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw,
 451                                     u32 etht_rx_queue_en,
 452                                     u32 filter);
 453
 454/* set ethertype rx queue */
 455void hw_atl_rpf_etht_rx_queue_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue,
 456                                  u32 filter);
 457
 458/* set ethertype user-priority */
 459void hw_atl_rpf_etht_user_priority_set(struct aq_hw_s *aq_hw,
 460                                       u32 etht_user_priority,
 461                                       u32 filter);
 462
 463/* set ethertype management queue */
 464void hw_atl_rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, u32 etht_mgt_queue,
 465                                   u32 filter);
 466
 467/* set ethertype filter action */
 468void hw_atl_rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act,
 469                                 u32 filter);
 470
 471/* set ethertype filter */
 472void hw_atl_rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter);
 473
 474/* rpo */
 475
 476/* set ipv4 header checksum offload enable */
 477void hw_atl_rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
 478                                              u32 ipv4header_crc_offload_en);
 479
 480/* set rx descriptor vlan stripping */
 481void hw_atl_rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw,
 482                                           u32 rx_desc_vlan_stripping,
 483                                           u32 descriptor);
 484
 485/* set tcp/udp checksum offload enable */
 486void hw_atl_rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
 487                                           u32 tcp_udp_crc_offload_en);
 488
 489/* Set LRO Patch Optimization Enable. */
 490void hw_atl_rpo_lro_patch_optimization_en_set(struct aq_hw_s *aq_hw,
 491                                              u32 lro_patch_optimization_en);
 492
 493/* Set Large Receive Offload Enable */
 494void hw_atl_rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en);
 495
 496/* Set LRO Q Sessions Limit */
 497void hw_atl_rpo_lro_qsessions_lim_set(struct aq_hw_s *aq_hw,
 498                                      u32 lro_qsessions_lim);
 499
 500/* Set LRO Total Descriptor Limit */
 501void hw_atl_rpo_lro_total_desc_lim_set(struct aq_hw_s *aq_hw,
 502                                       u32 lro_total_desc_lim);
 503
 504/* Set LRO Min Payload of First Packet */
 505void hw_atl_rpo_lro_min_pay_of_first_pkt_set(struct aq_hw_s *aq_hw,
 506                                             u32 lro_min_pld_of_first_pkt);
 507
 508/* Set LRO Packet Limit */
 509void hw_atl_rpo_lro_pkt_lim_set(struct aq_hw_s *aq_hw, u32 lro_packet_lim);
 510
 511/* Set LRO Max Number of Descriptors */
 512void hw_atl_rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw,
 513                                               u32 lro_max_desc_num, u32 lro);
 514
 515/* Set LRO Time Base Divider */
 516void hw_atl_rpo_lro_time_base_divider_set(struct aq_hw_s *aq_hw,
 517                                          u32 lro_time_base_divider);
 518
 519/*Set LRO Inactive Interval */
 520void hw_atl_rpo_lro_inactive_interval_set(struct aq_hw_s *aq_hw,
 521                                          u32 lro_inactive_interval);
 522
 523/*Set LRO Max Coalescing Interval */
 524void hw_atl_rpo_lro_max_coalescing_interval_set(struct aq_hw_s *aq_hw,
 525                                                u32 lro_max_coal_interval);
 526
 527/* rx */
 528
 529/* set rx register reset disable */
 530void hw_atl_rx_rx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 rx_reg_res_dis);
 531
 532/* tdm */
 533
 534/* set cpu id */
 535void hw_atl_tdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca);
 536
 537/* set large send offload enable */
 538void hw_atl_tdm_large_send_offload_en_set(struct aq_hw_s *aq_hw,
 539                                          u32 large_send_offload_en);
 540
 541/* set tx descriptor enable */
 542void hw_atl_tdm_tx_desc_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_en,
 543                               u32 descriptor);
 544
 545/* set tx dca enable */
 546void hw_atl_tdm_tx_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_dca_en);
 547
 548/* set tx dca mode */
 549void hw_atl_tdm_tx_dca_mode_set(struct aq_hw_s *aq_hw, u32 tx_dca_mode);
 550
 551/* set tx descriptor dca enable */
 552void hw_atl_tdm_tx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_dca_en,
 553                                   u32 dca);
 554
 555/* get tx descriptor head pointer */
 556u32 hw_atl_tdm_tx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor);
 557
 558/* set tx descriptor length */
 559void hw_atl_tdm_tx_desc_len_set(struct aq_hw_s *aq_hw, u32 tx_desc_len,
 560                                u32 descriptor);
 561
 562/* set tx descriptor write-back interrupt enable */
 563void hw_atl_tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
 564                                         u32 tx_desc_wr_wb_irq_en);
 565
 566/* set tx descriptor write-back threshold */
 567void hw_atl_tdm_tx_desc_wr_wb_threshold_set(struct aq_hw_s *aq_hw,
 568                                            u32 tx_desc_wr_wb_threshold,
 569                                     u32 descriptor);
 570
 571/* Set TDM Interrupt Moderation Enable */
 572void hw_atl_tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
 573                                      u32 tdm_irq_moderation_en);
 574/* thm */
 575
 576/* set lso tcp flag of first packet */
 577void hw_atl_thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw_s *aq_hw,
 578                                              u32 lso_tcp_flag_of_first_pkt);
 579
 580/* set lso tcp flag of last packet */
 581void hw_atl_thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw_s *aq_hw,
 582                                             u32 lso_tcp_flag_of_last_pkt);
 583
 584/* set lso tcp flag of middle packet */
 585void hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw,
 586                                               u32 lso_tcp_flag_of_middle_pkt);
 587
 588/* tpb */
 589
 590/* set TX Traffic Class Mode */
 591void hw_atl_rpb_tps_tx_tc_mode_set(struct aq_hw_s *aq_hw,
 592                                   u32 tx_traf_class_mode);
 593
 594/* get TX Traffic Class Mode */
 595u32 hw_atl_rpb_tps_tx_tc_mode_get(struct aq_hw_s *aq_hw);
 596
 597/* set tx buffer enable */
 598void hw_atl_tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en);
 599
 600/* set tx buffer high threshold (per tc) */
 601void hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
 602                                                u32 tx_buff_hi_threshold_per_tc,
 603                                         u32 buffer);
 604
 605/* set tx buffer low threshold (per tc) */
 606void hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
 607                                                u32 tx_buff_lo_threshold_per_tc,
 608                                         u32 buffer);
 609
 610/* set tx dma system loopback enable */
 611void hw_atl_tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw,
 612                                      u32 tx_dma_sys_lbk_en);
 613
 614/* set tx packet buffer size (per tc) */
 615void hw_atl_tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
 616                                            u32 tx_pkt_buff_size_per_tc,
 617                                            u32 buffer);
 618
 619/* set tx path pad insert enable */
 620void hw_atl_tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw,
 621                                       u32 tx_path_scp_ins_en);
 622
 623/* tpo */
 624
 625/* set ipv4 header checksum offload enable */
 626void hw_atl_tpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
 627                                              u32 ipv4header_crc_offload_en);
 628
 629/* set tcp/udp checksum offload enable */
 630void hw_atl_tpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
 631                                           u32 tcp_udp_crc_offload_en);
 632
 633/* set tx pkt system loopback enable */
 634void hw_atl_tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw,
 635                                      u32 tx_pkt_sys_lbk_en);
 636
 637/* tps */
 638
 639/* set tx packet scheduler data arbitration mode */
 640void hw_atl_tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw,
 641                                              u32 tx_pkt_shed_data_arb_mode);
 642
 643/* set tx packet scheduler descriptor rate current time reset */
 644void hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw_s *aq_hw,
 645                                                        u32 curr_time_res);
 646
 647/* set tx packet scheduler descriptor rate limit */
 648void hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw_s *aq_hw,
 649                                              u32 tx_pkt_shed_desc_rate_lim);
 650
 651/* set tx packet scheduler descriptor tc arbitration mode */
 652void hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw,
 653                                                 u32 arb_mode);
 654
 655/* set tx packet scheduler descriptor tc max credit */
 656void hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw,
 657                                                   u32 max_credit,
 658                                            u32 tc);
 659
 660/* set tx packet scheduler descriptor tc weight */
 661void hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw,
 662                                               u32 tx_pkt_shed_desc_tc_weight,
 663                                        u32 tc);
 664
 665/* set tx packet scheduler descriptor vm arbitration mode */
 666void hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw,
 667                                                 u32 arb_mode);
 668
 669/* set tx packet scheduler tc data max credit */
 670void hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw,
 671                                                   u32 max_credit,
 672                                            u32 tc);
 673
 674/* set tx packet scheduler tc data weight */
 675void hw_atl_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,
 676                                               u32 tx_pkt_shed_tc_data_weight,
 677                                        u32 tc);
 678
 679/* tx */
 680
 681/* set tx register reset disable */
 682void hw_atl_tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis);
 683
 684/* msm */
 685
 686/* get register access status */
 687u32 hw_atl_msm_reg_access_status_get(struct aq_hw_s *aq_hw);
 688
 689/* set  register address for indirect address */
 690void hw_atl_msm_reg_addr_for_indirect_addr_set(struct aq_hw_s *aq_hw,
 691                                               u32 reg_addr_for_indirect_addr);
 692
 693/* set register read strobe */
 694void hw_atl_msm_reg_rd_strobe_set(struct aq_hw_s *aq_hw, u32 reg_rd_strobe);
 695
 696/* get  register read data */
 697u32 hw_atl_msm_reg_rd_data_get(struct aq_hw_s *aq_hw);
 698
 699/* set  register write data */
 700void hw_atl_msm_reg_wr_data_set(struct aq_hw_s *aq_hw, u32 reg_wr_data);
 701
 702/* set register write strobe */
 703void hw_atl_msm_reg_wr_strobe_set(struct aq_hw_s *aq_hw, u32 reg_wr_strobe);
 704
 705/* pci */
 706
 707/* set pci register reset disable */
 708void hw_atl_pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis);
 709
 710/* set uP Force Interrupt */
 711void hw_atl_mcp_up_force_intr_set(struct aq_hw_s *aq_hw, u32 up_force_intr);
 712
 713
 714#endif /* HW_ATL_LLH_H */
 715