1
2
3
4
5#include "e1000_api.h"
6
7STATIC void e1000_reload_nvm_generic(struct e1000_hw *hw);
8
9
10
11
12
13
14
15void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
16{
17 struct e1000_nvm_info *nvm = &hw->nvm;
18 DEBUGFUNC("e1000_init_nvm_ops_generic");
19
20
21 nvm->ops.init_params = e1000_null_ops_generic;
22 nvm->ops.acquire = e1000_null_ops_generic;
23 nvm->ops.read = e1000_null_read_nvm;
24 nvm->ops.release = e1000_null_nvm_generic;
25 nvm->ops.reload = e1000_reload_nvm_generic;
26 nvm->ops.update = e1000_null_ops_generic;
27 nvm->ops.valid_led_default = e1000_null_led_default;
28 nvm->ops.validate = e1000_null_ops_generic;
29 nvm->ops.write = e1000_null_write_nvm;
30}
31
32
33
34
35
36
37
38
39s32 e1000_null_read_nvm(struct e1000_hw E1000_UNUSEDARG *hw,
40 u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,
41 u16 E1000_UNUSEDARG *c)
42{
43 DEBUGFUNC("e1000_null_read_nvm");
44 UNREFERENCED_4PARAMETER(hw, a, b, c);
45 return E1000_SUCCESS;
46}
47
48
49
50
51
52void e1000_null_nvm_generic(struct e1000_hw E1000_UNUSEDARG *hw)
53{
54 DEBUGFUNC("e1000_null_nvm_generic");
55 UNREFERENCED_1PARAMETER(hw);
56 return;
57}
58
59
60
61
62
63
64s32 e1000_null_led_default(struct e1000_hw E1000_UNUSEDARG *hw,
65 u16 E1000_UNUSEDARG *data)
66{
67 DEBUGFUNC("e1000_null_led_default");
68 UNREFERENCED_2PARAMETER(hw, data);
69 return E1000_SUCCESS;
70}
71
72
73
74
75
76
77
78
79s32 e1000_null_write_nvm(struct e1000_hw E1000_UNUSEDARG *hw,
80 u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,
81 u16 E1000_UNUSEDARG *c)
82{
83 DEBUGFUNC("e1000_null_write_nvm");
84 UNREFERENCED_4PARAMETER(hw, a, b, c);
85 return E1000_SUCCESS;
86}
87
88
89
90
91
92
93
94
95STATIC void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
96{
97 *eecd = *eecd | E1000_EECD_SK;
98 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
99 E1000_WRITE_FLUSH(hw);
100 usec_delay(hw->nvm.delay_usec);
101}
102
103
104
105
106
107
108
109
110STATIC void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
111{
112 *eecd = *eecd & ~E1000_EECD_SK;
113 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
114 E1000_WRITE_FLUSH(hw);
115 usec_delay(hw->nvm.delay_usec);
116}
117
118
119
120
121
122
123
124
125
126
127
128STATIC void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
129{
130 struct e1000_nvm_info *nvm = &hw->nvm;
131 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
132 u32 mask;
133
134 DEBUGFUNC("e1000_shift_out_eec_bits");
135
136 mask = 0x01 << (count - 1);
137 if (nvm->type == e1000_nvm_eeprom_microwire)
138 eecd &= ~E1000_EECD_DO;
139 else
140 if (nvm->type == e1000_nvm_eeprom_spi)
141 eecd |= E1000_EECD_DO;
142
143 do {
144 eecd &= ~E1000_EECD_DI;
145
146 if (data & mask)
147 eecd |= E1000_EECD_DI;
148
149 E1000_WRITE_REG(hw, E1000_EECD, eecd);
150 E1000_WRITE_FLUSH(hw);
151
152 usec_delay(nvm->delay_usec);
153
154 e1000_raise_eec_clk(hw, &eecd);
155 e1000_lower_eec_clk(hw, &eecd);
156
157 mask >>= 1;
158 } while (mask);
159
160 eecd &= ~E1000_EECD_DI;
161 E1000_WRITE_REG(hw, E1000_EECD, eecd);
162}
163
164
165
166
167
168
169
170
171
172
173
174
175STATIC u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
176{
177 u32 eecd;
178 u32 i;
179 u16 data;
180
181 DEBUGFUNC("e1000_shift_in_eec_bits");
182
183 eecd = E1000_READ_REG(hw, E1000_EECD);
184
185 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
186 data = 0;
187
188 for (i = 0; i < count; i++) {
189 data <<= 1;
190 e1000_raise_eec_clk(hw, &eecd);
191
192 eecd = E1000_READ_REG(hw, E1000_EECD);
193
194 eecd &= ~E1000_EECD_DI;
195 if (eecd & E1000_EECD_DO)
196 data |= 1;
197
198 e1000_lower_eec_clk(hw, &eecd);
199 }
200
201 return data;
202}
203
204
205
206
207
208
209
210
211
212s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
213{
214 u32 attempts = 100000;
215 u32 i, reg = 0;
216
217 DEBUGFUNC("e1000_poll_eerd_eewr_done");
218
219 for (i = 0; i < attempts; i++) {
220 if (ee_reg == E1000_NVM_POLL_READ)
221 reg = E1000_READ_REG(hw, E1000_EERD);
222 else
223 reg = E1000_READ_REG(hw, E1000_EEWR);
224
225 if (reg & E1000_NVM_RW_REG_DONE)
226 return E1000_SUCCESS;
227
228 usec_delay(5);
229 }
230
231 return -E1000_ERR_NVM;
232}
233
234
235
236
237
238
239
240
241
242s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
243{
244 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
245 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
246
247 DEBUGFUNC("e1000_acquire_nvm_generic");
248
249 E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
250 eecd = E1000_READ_REG(hw, E1000_EECD);
251
252 while (timeout) {
253 if (eecd & E1000_EECD_GNT)
254 break;
255 usec_delay(5);
256 eecd = E1000_READ_REG(hw, E1000_EECD);
257 timeout--;
258 }
259
260 if (!timeout) {
261 eecd &= ~E1000_EECD_REQ;
262 E1000_WRITE_REG(hw, E1000_EECD, eecd);
263 DEBUGOUT("Could not acquire NVM grant\n");
264 return -E1000_ERR_NVM;
265 }
266
267 return E1000_SUCCESS;
268}
269
270
271
272
273
274
275
276STATIC void e1000_standby_nvm(struct e1000_hw *hw)
277{
278 struct e1000_nvm_info *nvm = &hw->nvm;
279 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
280
281 DEBUGFUNC("e1000_standby_nvm");
282
283 if (nvm->type == e1000_nvm_eeprom_microwire) {
284 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
285 E1000_WRITE_REG(hw, E1000_EECD, eecd);
286 E1000_WRITE_FLUSH(hw);
287 usec_delay(nvm->delay_usec);
288
289 e1000_raise_eec_clk(hw, &eecd);
290
291
292 eecd |= E1000_EECD_CS;
293 E1000_WRITE_REG(hw, E1000_EECD, eecd);
294 E1000_WRITE_FLUSH(hw);
295 usec_delay(nvm->delay_usec);
296
297 e1000_lower_eec_clk(hw, &eecd);
298 } else if (nvm->type == e1000_nvm_eeprom_spi) {
299
300 eecd |= E1000_EECD_CS;
301 E1000_WRITE_REG(hw, E1000_EECD, eecd);
302 E1000_WRITE_FLUSH(hw);
303 usec_delay(nvm->delay_usec);
304 eecd &= ~E1000_EECD_CS;
305 E1000_WRITE_REG(hw, E1000_EECD, eecd);
306 E1000_WRITE_FLUSH(hw);
307 usec_delay(nvm->delay_usec);
308 }
309}
310
311
312
313
314
315
316
317void e1000_stop_nvm(struct e1000_hw *hw)
318{
319 u32 eecd;
320
321 DEBUGFUNC("e1000_stop_nvm");
322
323 eecd = E1000_READ_REG(hw, E1000_EECD);
324 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
325
326 eecd |= E1000_EECD_CS;
327 e1000_lower_eec_clk(hw, &eecd);
328 } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
329
330 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
331 E1000_WRITE_REG(hw, E1000_EECD, eecd);
332 e1000_raise_eec_clk(hw, &eecd);
333 e1000_lower_eec_clk(hw, &eecd);
334 }
335}
336
337
338
339
340
341
342
343void e1000_release_nvm_generic(struct e1000_hw *hw)
344{
345 u32 eecd;
346
347 DEBUGFUNC("e1000_release_nvm_generic");
348
349 e1000_stop_nvm(hw);
350
351 eecd = E1000_READ_REG(hw, E1000_EECD);
352 eecd &= ~E1000_EECD_REQ;
353 E1000_WRITE_REG(hw, E1000_EECD, eecd);
354}
355
356
357
358
359
360
361
362STATIC s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
363{
364 struct e1000_nvm_info *nvm = &hw->nvm;
365 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
366 u8 spi_stat_reg;
367
368 DEBUGFUNC("e1000_ready_nvm_eeprom");
369
370 if (nvm->type == e1000_nvm_eeprom_microwire) {
371
372 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
373 E1000_WRITE_REG(hw, E1000_EECD, eecd);
374
375 eecd |= E1000_EECD_CS;
376 E1000_WRITE_REG(hw, E1000_EECD, eecd);
377 } else if (nvm->type == e1000_nvm_eeprom_spi) {
378 u16 timeout = NVM_MAX_RETRY_SPI;
379
380
381 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
382 E1000_WRITE_REG(hw, E1000_EECD, eecd);
383 E1000_WRITE_FLUSH(hw);
384 usec_delay(1);
385
386
387
388
389
390
391 while (timeout) {
392 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
393 hw->nvm.opcode_bits);
394 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
395 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
396 break;
397
398 usec_delay(5);
399 e1000_standby_nvm(hw);
400 timeout--;
401 }
402
403 if (!timeout) {
404 DEBUGOUT("SPI NVM Status error\n");
405 return -E1000_ERR_NVM;
406 }
407 }
408
409 return E1000_SUCCESS;
410}
411
412
413
414
415
416
417
418
419
420
421s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
422{
423 struct e1000_nvm_info *nvm = &hw->nvm;
424 u32 i = 0;
425 s32 ret_val;
426 u16 word_in;
427 u8 read_opcode = NVM_READ_OPCODE_SPI;
428
429 DEBUGFUNC("e1000_read_nvm_spi");
430
431
432
433
434 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
435 (words == 0)) {
436 DEBUGOUT("nvm parameter(s) out of bounds\n");
437 return -E1000_ERR_NVM;
438 }
439
440 ret_val = nvm->ops.acquire(hw);
441 if (ret_val)
442 return ret_val;
443
444 ret_val = e1000_ready_nvm_eeprom(hw);
445 if (ret_val)
446 goto release;
447
448 e1000_standby_nvm(hw);
449
450 if ((nvm->address_bits == 8) && (offset >= 128))
451 read_opcode |= NVM_A8_OPCODE_SPI;
452
453
454 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
455 e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
456
457
458
459
460
461 for (i = 0; i < words; i++) {
462 word_in = e1000_shift_in_eec_bits(hw, 16);
463 data[i] = (word_in >> 8) | (word_in << 8);
464 }
465
466release:
467 nvm->ops.release(hw);
468
469 return ret_val;
470}
471
472
473
474
475
476
477
478
479
480
481s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
482 u16 *data)
483{
484 struct e1000_nvm_info *nvm = &hw->nvm;
485 u32 i = 0;
486 s32 ret_val;
487 u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
488
489 DEBUGFUNC("e1000_read_nvm_microwire");
490
491
492
493
494 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
495 (words == 0)) {
496 DEBUGOUT("nvm parameter(s) out of bounds\n");
497 return -E1000_ERR_NVM;
498 }
499
500 ret_val = nvm->ops.acquire(hw);
501 if (ret_val)
502 return ret_val;
503
504 ret_val = e1000_ready_nvm_eeprom(hw);
505 if (ret_val)
506 goto release;
507
508 for (i = 0; i < words; i++) {
509
510 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
511 e1000_shift_out_eec_bits(hw, (u16)(offset + i),
512 nvm->address_bits);
513
514
515
516
517 data[i] = e1000_shift_in_eec_bits(hw, 16);
518 e1000_standby_nvm(hw);
519 }
520
521release:
522 nvm->ops.release(hw);
523
524 return ret_val;
525}
526
527
528
529
530
531
532
533
534
535
536s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
537{
538 struct e1000_nvm_info *nvm = &hw->nvm;
539 u32 i, eerd = 0;
540 s32 ret_val = E1000_SUCCESS;
541
542 DEBUGFUNC("e1000_read_nvm_eerd");
543
544
545
546
547 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
548 (words == 0)) {
549 DEBUGOUT("nvm parameter(s) out of bounds\n");
550 return -E1000_ERR_NVM;
551 }
552
553 for (i = 0; i < words; i++) {
554 eerd = ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) +
555 E1000_NVM_RW_REG_START;
556
557 E1000_WRITE_REG(hw, E1000_EERD, eerd);
558 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
559 if (ret_val)
560 break;
561
562 data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
563 E1000_NVM_RW_REG_DATA);
564 }
565
566 if (ret_val)
567 DEBUGOUT1("NVM read error: %d\n", ret_val);
568
569 return ret_val;
570}
571
572
573
574
575
576
577
578
579
580
581
582
583
584s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
585{
586 struct e1000_nvm_info *nvm = &hw->nvm;
587 s32 ret_val = -E1000_ERR_NVM;
588 u16 widx = 0;
589
590 DEBUGFUNC("e1000_write_nvm_spi");
591
592
593
594
595 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
596 (words == 0)) {
597 DEBUGOUT("nvm parameter(s) out of bounds\n");
598 return -E1000_ERR_NVM;
599 }
600
601 while (widx < words) {
602 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
603
604 ret_val = nvm->ops.acquire(hw);
605 if (ret_val)
606 return ret_val;
607
608 ret_val = e1000_ready_nvm_eeprom(hw);
609 if (ret_val) {
610 nvm->ops.release(hw);
611 return ret_val;
612 }
613
614 e1000_standby_nvm(hw);
615
616
617 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
618 nvm->opcode_bits);
619
620 e1000_standby_nvm(hw);
621
622
623
624
625 if ((nvm->address_bits == 8) && (offset >= 128))
626 write_opcode |= NVM_A8_OPCODE_SPI;
627
628
629 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
630 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
631 nvm->address_bits);
632
633
634 while (widx < words) {
635 u16 word_out = data[widx];
636 word_out = (word_out >> 8) | (word_out << 8);
637 e1000_shift_out_eec_bits(hw, word_out, 16);
638 widx++;
639
640 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
641 e1000_standby_nvm(hw);
642 break;
643 }
644 }
645 msec_delay(10);
646 nvm->ops.release(hw);
647 }
648
649 return ret_val;
650}
651
652
653
654
655
656
657
658
659
660
661
662
663
664s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
665 u16 *data)
666{
667 struct e1000_nvm_info *nvm = &hw->nvm;
668 s32 ret_val;
669 u32 eecd;
670 u16 words_written = 0;
671 u16 widx = 0;
672
673 DEBUGFUNC("e1000_write_nvm_microwire");
674
675
676
677
678 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
679 (words == 0)) {
680 DEBUGOUT("nvm parameter(s) out of bounds\n");
681 return -E1000_ERR_NVM;
682 }
683
684 ret_val = nvm->ops.acquire(hw);
685 if (ret_val)
686 return ret_val;
687
688 ret_val = e1000_ready_nvm_eeprom(hw);
689 if (ret_val)
690 goto release;
691
692 e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
693 (u16)(nvm->opcode_bits + 2));
694
695 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
696
697 e1000_standby_nvm(hw);
698
699 while (words_written < words) {
700 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
701 nvm->opcode_bits);
702
703 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
704 nvm->address_bits);
705
706 e1000_shift_out_eec_bits(hw, data[words_written], 16);
707
708 e1000_standby_nvm(hw);
709
710 for (widx = 0; widx < 200; widx++) {
711 eecd = E1000_READ_REG(hw, E1000_EECD);
712 if (eecd & E1000_EECD_DO)
713 break;
714 usec_delay(50);
715 }
716
717 if (widx == 200) {
718 DEBUGOUT("NVM Write did not complete\n");
719 ret_val = -E1000_ERR_NVM;
720 goto release;
721 }
722
723 e1000_standby_nvm(hw);
724
725 words_written++;
726 }
727
728 e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
729 (u16)(nvm->opcode_bits + 2));
730
731 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
732
733release:
734 nvm->ops.release(hw);
735
736 return ret_val;
737}
738
739
740
741
742
743
744
745
746
747
748s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
749 u32 pba_num_size)
750{
751 s32 ret_val;
752 u16 nvm_data;
753 u16 pba_ptr;
754 u16 offset;
755 u16 length;
756
757 DEBUGFUNC("e1000_read_pba_string_generic");
758
759 if ((hw->mac.type == e1000_i210 ||
760 hw->mac.type == e1000_i211) &&
761 !e1000_get_flash_presence_i210(hw)) {
762 DEBUGOUT("Flashless no PBA string\n");
763 return -E1000_ERR_NVM_PBA_SECTION;
764 }
765
766 if (pba_num == NULL) {
767 DEBUGOUT("PBA string buffer was null\n");
768 return -E1000_ERR_INVALID_ARGUMENT;
769 }
770
771 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
772 if (ret_val) {
773 DEBUGOUT("NVM Read Error\n");
774 return ret_val;
775 }
776
777 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
778 if (ret_val) {
779 DEBUGOUT("NVM Read Error\n");
780 return ret_val;
781 }
782
783
784
785
786
787 if (nvm_data != NVM_PBA_PTR_GUARD) {
788 DEBUGOUT("NVM PBA number is not stored as string\n");
789
790
791 if (pba_num_size < E1000_PBANUM_LENGTH) {
792 DEBUGOUT("PBA string buffer too small\n");
793 return E1000_ERR_NO_SPACE;
794 }
795
796
797 pba_num[0] = (nvm_data >> 12) & 0xF;
798 pba_num[1] = (nvm_data >> 8) & 0xF;
799 pba_num[2] = (nvm_data >> 4) & 0xF;
800 pba_num[3] = nvm_data & 0xF;
801 pba_num[4] = (pba_ptr >> 12) & 0xF;
802 pba_num[5] = (pba_ptr >> 8) & 0xF;
803 pba_num[6] = '-';
804 pba_num[7] = 0;
805 pba_num[8] = (pba_ptr >> 4) & 0xF;
806 pba_num[9] = pba_ptr & 0xF;
807
808
809 pba_num[10] = '\0';
810
811
812 for (offset = 0; offset < 10; offset++) {
813 if (pba_num[offset] < 0xA)
814 pba_num[offset] += '0';
815 else if (pba_num[offset] < 0x10)
816 pba_num[offset] += 'A' - 0xA;
817 }
818
819 return E1000_SUCCESS;
820 }
821
822 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
823 if (ret_val) {
824 DEBUGOUT("NVM Read Error\n");
825 return ret_val;
826 }
827
828 if (length == 0xFFFF || length == 0) {
829 DEBUGOUT("NVM PBA number section invalid length\n");
830 return -E1000_ERR_NVM_PBA_SECTION;
831 }
832
833 if (pba_num_size < (((u32)length * 2) - 1)) {
834 DEBUGOUT("PBA string buffer too small\n");
835 return -E1000_ERR_NO_SPACE;
836 }
837
838
839 pba_ptr++;
840 length--;
841
842 for (offset = 0; offset < length; offset++) {
843 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
844 if (ret_val) {
845 DEBUGOUT("NVM Read Error\n");
846 return ret_val;
847 }
848 pba_num[offset * 2] = (u8)(nvm_data >> 8);
849 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
850 }
851 pba_num[offset * 2] = '\0';
852
853 return E1000_SUCCESS;
854}
855
856
857
858
859
860
861
862
863
864s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)
865{
866 s32 ret_val;
867 u16 nvm_data;
868 u16 pba_ptr;
869 u16 length;
870
871 DEBUGFUNC("e1000_read_pba_length_generic");
872
873 if (pba_num_size == NULL) {
874 DEBUGOUT("PBA buffer size was null\n");
875 return -E1000_ERR_INVALID_ARGUMENT;
876 }
877
878 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
879 if (ret_val) {
880 DEBUGOUT("NVM Read Error\n");
881 return ret_val;
882 }
883
884 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
885 if (ret_val) {
886 DEBUGOUT("NVM Read Error\n");
887 return ret_val;
888 }
889
890
891 if (nvm_data != NVM_PBA_PTR_GUARD) {
892 *pba_num_size = E1000_PBANUM_LENGTH;
893 return E1000_SUCCESS;
894 }
895
896 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
897 if (ret_val) {
898 DEBUGOUT("NVM Read Error\n");
899 return ret_val;
900 }
901
902 if (length == 0xFFFF || length == 0) {
903 DEBUGOUT("NVM PBA number section invalid length\n");
904 return -E1000_ERR_NVM_PBA_SECTION;
905 }
906
907
908
909
910 *pba_num_size = ((u32)length * 2) - 1;
911
912 return E1000_SUCCESS;
913}
914
915
916
917
918
919
920
921
922
923s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num)
924{
925 s32 ret_val;
926 u16 nvm_data;
927
928 DEBUGFUNC("e1000_read_pba_num_generic");
929
930 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
931 if (ret_val) {
932 DEBUGOUT("NVM Read Error\n");
933 return ret_val;
934 } else if (nvm_data == NVM_PBA_PTR_GUARD) {
935 DEBUGOUT("NVM Not Supported\n");
936 return -E1000_NOT_IMPLEMENTED;
937 }
938 *pba_num = (u32)(nvm_data << 16);
939
940 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
941 if (ret_val) {
942 DEBUGOUT("NVM Read Error\n");
943 return ret_val;
944 }
945 *pba_num |= nvm_data;
946
947 return E1000_SUCCESS;
948}
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963s32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
964 u32 eeprom_buf_size, u16 max_pba_block_size,
965 struct e1000_pba *pba)
966{
967 s32 ret_val;
968 u16 pba_block_size;
969
970 if (pba == NULL)
971 return -E1000_ERR_PARAM;
972
973 if (eeprom_buf == NULL) {
974 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2,
975 &pba->word[0]);
976 if (ret_val)
977 return ret_val;
978 } else {
979 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
980 pba->word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
981 pba->word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
982 } else {
983 return -E1000_ERR_PARAM;
984 }
985 }
986
987 if (pba->word[0] == NVM_PBA_PTR_GUARD) {
988 if (pba->pba_block == NULL)
989 return -E1000_ERR_PARAM;
990
991 ret_val = e1000_get_pba_block_size(hw, eeprom_buf,
992 eeprom_buf_size,
993 &pba_block_size);
994 if (ret_val)
995 return ret_val;
996
997 if (pba_block_size > max_pba_block_size)
998 return -E1000_ERR_PARAM;
999
1000 if (eeprom_buf == NULL) {
1001 ret_val = e1000_read_nvm(hw, pba->word[1],
1002 pba_block_size,
1003 pba->pba_block);
1004 if (ret_val)
1005 return ret_val;
1006 } else {
1007 if (eeprom_buf_size > (u32)(pba->word[1] +
1008 pba_block_size)) {
1009 memcpy(pba->pba_block,
1010 &eeprom_buf[pba->word[1]],
1011 pba_block_size * sizeof(u16));
1012 } else {
1013 return -E1000_ERR_PARAM;
1014 }
1015 }
1016 }
1017
1018 return E1000_SUCCESS;
1019}
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032s32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
1033 u32 eeprom_buf_size, struct e1000_pba *pba)
1034{
1035 s32 ret_val;
1036
1037 if (pba == NULL)
1038 return -E1000_ERR_PARAM;
1039
1040 if (eeprom_buf == NULL) {
1041 ret_val = e1000_write_nvm(hw, NVM_PBA_OFFSET_0, 2,
1042 &pba->word[0]);
1043 if (ret_val)
1044 return ret_val;
1045 } else {
1046 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1047 eeprom_buf[NVM_PBA_OFFSET_0] = pba->word[0];
1048 eeprom_buf[NVM_PBA_OFFSET_1] = pba->word[1];
1049 } else {
1050 return -E1000_ERR_PARAM;
1051 }
1052 }
1053
1054 if (pba->word[0] == NVM_PBA_PTR_GUARD) {
1055 if (pba->pba_block == NULL)
1056 return -E1000_ERR_PARAM;
1057
1058 if (eeprom_buf == NULL) {
1059 ret_val = e1000_write_nvm(hw, pba->word[1],
1060 pba->pba_block[0],
1061 pba->pba_block);
1062 if (ret_val)
1063 return ret_val;
1064 } else {
1065 if (eeprom_buf_size > (u32)(pba->word[1] +
1066 pba->pba_block[0])) {
1067 memcpy(&eeprom_buf[pba->word[1]],
1068 pba->pba_block,
1069 pba->pba_block[0] * sizeof(u16));
1070 } else {
1071 return -E1000_ERR_PARAM;
1072 }
1073 }
1074 }
1075
1076 return E1000_SUCCESS;
1077}
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091s32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf,
1092 u32 eeprom_buf_size, u16 *pba_block_size)
1093{
1094 s32 ret_val;
1095 u16 pba_word[2];
1096 u16 length;
1097
1098 DEBUGFUNC("e1000_get_pba_block_size");
1099
1100 if (eeprom_buf == NULL) {
1101 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, &pba_word[0]);
1102 if (ret_val)
1103 return ret_val;
1104 } else {
1105 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1106 pba_word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
1107 pba_word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
1108 } else {
1109 return -E1000_ERR_PARAM;
1110 }
1111 }
1112
1113 if (pba_word[0] == NVM_PBA_PTR_GUARD) {
1114 if (eeprom_buf == NULL) {
1115 ret_val = e1000_read_nvm(hw, pba_word[1] + 0, 1,
1116 &length);
1117 if (ret_val)
1118 return ret_val;
1119 } else {
1120 if (eeprom_buf_size > pba_word[1])
1121 length = eeprom_buf[pba_word[1] + 0];
1122 else
1123 return -E1000_ERR_PARAM;
1124 }
1125
1126 if (length == 0xFFFF || length == 0)
1127 return -E1000_ERR_NVM_PBA_SECTION;
1128 } else {
1129
1130 length = 0;
1131 }
1132
1133 if (pba_block_size != NULL)
1134 *pba_block_size = length;
1135
1136 return E1000_SUCCESS;
1137}
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
1148{
1149 u32 rar_high;
1150 u32 rar_low;
1151 u16 i;
1152
1153 rar_high = E1000_READ_REG(hw, E1000_RAH(0));
1154 rar_low = E1000_READ_REG(hw, E1000_RAL(0));
1155
1156 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
1157 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
1158
1159 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
1160 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
1161
1162 for (i = 0; i < ETH_ADDR_LEN; i++)
1163 hw->mac.addr[i] = hw->mac.perm_addr[i];
1164
1165 return E1000_SUCCESS;
1166}
1167
1168
1169
1170
1171
1172
1173
1174
1175s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
1176{
1177 s32 ret_val;
1178 u16 checksum = 0;
1179 u16 i, nvm_data;
1180
1181 DEBUGFUNC("e1000_validate_nvm_checksum_generic");
1182
1183 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1184 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1185 if (ret_val) {
1186 DEBUGOUT("NVM Read Error\n");
1187 return ret_val;
1188 }
1189 checksum += nvm_data;
1190 }
1191
1192 if (checksum != (u16) NVM_SUM) {
1193 DEBUGOUT("NVM Checksum Invalid\n");
1194 return -E1000_ERR_NVM;
1195 }
1196
1197 return E1000_SUCCESS;
1198}
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
1209{
1210 s32 ret_val;
1211 u16 checksum = 0;
1212 u16 i, nvm_data;
1213
1214 DEBUGFUNC("e1000_update_nvm_checksum");
1215
1216 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
1217 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1218 if (ret_val) {
1219 DEBUGOUT("NVM Read Error while updating checksum.\n");
1220 return ret_val;
1221 }
1222 checksum += nvm_data;
1223 }
1224 checksum = (u16) NVM_SUM - checksum;
1225 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
1226 if (ret_val)
1227 DEBUGOUT("NVM Write Error while updating checksum.\n");
1228
1229 return ret_val;
1230}
1231
1232
1233
1234
1235
1236
1237
1238
1239STATIC void e1000_reload_nvm_generic(struct e1000_hw *hw)
1240{
1241 u32 ctrl_ext;
1242
1243 DEBUGFUNC("e1000_reload_nvm_generic");
1244
1245 usec_delay(10);
1246 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1247 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1248 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1249 E1000_WRITE_FLUSH(hw);
1250}
1251
1252
1253
1254
1255
1256
1257
1258
1259void e1000_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers)
1260{
1261 u16 eeprom_verh, eeprom_verl, etrack_test, fw_version;
1262 u8 q, hval, rem, result;
1263 u16 comb_verh, comb_verl, comb_offset;
1264
1265 memset(fw_vers, 0, sizeof(struct e1000_fw_version));
1266
1267
1268
1269
1270 switch (hw->mac.type) {
1271 case e1000_i211:
1272 e1000_read_invm_version(hw, fw_vers);
1273 return;
1274 case e1000_82575:
1275 case e1000_82576:
1276 case e1000_82580:
1277 case e1000_i354:
1278 hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
1279
1280
1281
1282 if ((etrack_test & NVM_MAJOR_MASK) != NVM_ETRACK_VALID) {
1283 hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
1284 fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
1285 >> NVM_MAJOR_SHIFT;
1286 fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK)
1287 >> NVM_MINOR_SHIFT;
1288 fw_vers->eep_build = (fw_version & NVM_IMAGE_ID_MASK);
1289 goto etrack_id;
1290 }
1291 break;
1292 case e1000_i210:
1293 if (!(e1000_get_flash_presence_i210(hw))) {
1294 e1000_read_invm_version(hw, fw_vers);
1295 return;
1296 }
1297
1298 case e1000_i350:
1299 hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
1300
1301 hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset);
1302 if ((comb_offset != 0x0) &&
1303 (comb_offset != NVM_VER_INVALID)) {
1304
1305 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset
1306 + 1), 1, &comb_verh);
1307 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset),
1308 1, &comb_verl);
1309
1310
1311 if ((comb_verh && comb_verl) &&
1312 ((comb_verh != NVM_VER_INVALID) &&
1313 (comb_verl != NVM_VER_INVALID))) {
1314
1315 fw_vers->or_valid = true;
1316 fw_vers->or_major =
1317 comb_verl >> NVM_COMB_VER_SHFT;
1318 fw_vers->or_build =
1319 (comb_verl << NVM_COMB_VER_SHFT)
1320 | (comb_verh >> NVM_COMB_VER_SHFT);
1321 fw_vers->or_patch =
1322 comb_verh & NVM_COMB_VER_MASK;
1323 }
1324 }
1325 break;
1326 default:
1327 hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
1328 return;
1329 }
1330 hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
1331 fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
1332 >> NVM_MAJOR_SHIFT;
1333
1334
1335 if ((fw_version & NVM_NEW_DEC_MASK) == 0x0) {
1336 eeprom_verl = (fw_version & NVM_COMB_VER_MASK);
1337 } else {
1338 eeprom_verl = (fw_version & NVM_MINOR_MASK)
1339 >> NVM_MINOR_SHIFT;
1340 }
1341
1342
1343
1344 q = eeprom_verl / NVM_HEX_CONV;
1345 hval = q * NVM_HEX_TENS;
1346 rem = eeprom_verl % NVM_HEX_CONV;
1347 result = hval + rem;
1348 fw_vers->eep_minor = result;
1349
1350etrack_id:
1351 if ((etrack_test & NVM_MAJOR_MASK) == NVM_ETRACK_VALID) {
1352 hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl);
1353 hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh);
1354 fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT)
1355 | eeprom_verl;
1356 } else if ((etrack_test & NVM_ETRACK_VALID) == 0) {
1357 hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verh);
1358 hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verl);
1359 fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT) |
1360 eeprom_verl;
1361 }
1362}
1363
1364
1365