1/* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6#ifndef RTE_PMD_MLX5_DEFS_H_ 7#define RTE_PMD_MLX5_DEFS_H_ 8 9#include <ethdev_driver.h> 10#include <rte_vxlan.h> 11 12#include "mlx5_autoconf.h" 13 14/* Maximum number of simultaneous VLAN filters. */ 15#define MLX5_MAX_VLAN_IDS 128 16 17/* 18 * Request TX completion every time descriptors reach this threshold since 19 * the previous request. Must be a power of two for performance reasons. 20 */ 21#define MLX5_TX_COMP_THRESH 32u 22 23/* 24 * Request TX completion every time the total number of WQEBBs used for inlining 25 * packets exceeds the size of WQ divided by this divisor. Better to be power of 26 * two for performance. 27 */ 28#define MLX5_TX_COMP_THRESH_INLINE_DIV (1 << 3) 29 30/* 31 * Maximal amount of normal completion CQEs 32 * processed in one call of tx_burst() routine. 33 */ 34#define MLX5_TX_COMP_MAX_CQE 2u 35 36 37/* Size of per-queue MR cache array for linear search. */ 38#define MLX5_MR_CACHE_N 8 39 40/* Size of MR cache table for binary search. */ 41#define MLX5_MR_BTREE_CACHE_N 256 42 43/* 44 * If defined, only use software counters. The PMD will never ask the hardware 45 * for these, and many of them won't be available. 46 */ 47#ifndef MLX5_PMD_SOFT_COUNTERS 48#define MLX5_PMD_SOFT_COUNTERS 1 49#endif 50 51/* Alarm timeout. */ 52#define MLX5_ALARM_TIMEOUT_US 100000 53 54/* Maximum number of extended statistics counters. */ 55#define MLX5_MAX_XSTATS 32 56 57/* Maximum Packet headers size (L2+L3+L4) for TSO. */ 58#define MLX5_MAX_TSO_HEADER (128u + 34u) 59 60/* Inline data size required by NICs. */ 61#define MLX5_INLINE_HSIZE_NONE 0 62#define MLX5_INLINE_HSIZE_L2 (sizeof(struct rte_ether_hdr) + \ 63 sizeof(struct rte_vlan_hdr)) 64#define MLX5_INLINE_HSIZE_L3 (MLX5_INLINE_HSIZE_L2 + \ 65 sizeof(struct rte_ipv6_hdr)) 66#define MLX5_INLINE_HSIZE_L4 (MLX5_INLINE_HSIZE_L3 + \ 67 sizeof(struct rte_tcp_hdr)) 68#define MLX5_INLINE_HSIZE_INNER_L2 (MLX5_INLINE_HSIZE_L3 + \ 69 sizeof(struct rte_udp_hdr) + \ 70 sizeof(struct rte_vxlan_hdr) + \ 71 sizeof(struct rte_ether_hdr) + \ 72 sizeof(struct rte_vlan_hdr)) 73#define MLX5_INLINE_HSIZE_INNER_L3 (MLX5_INLINE_HSIZE_INNER_L2 + \ 74 sizeof(struct rte_ipv6_hdr)) 75#define MLX5_INLINE_HSIZE_INNER_L4 (MLX5_INLINE_HSIZE_INNER_L3 + \ 76 sizeof(struct rte_tcp_hdr)) 77 78/* Threshold of buffer replenishment for vectorized Rx. */ 79#define MLX5_VPMD_RXQ_RPLNSH_THRESH(n) \ 80 (RTE_MIN(MLX5_VPMD_RX_MAX_BURST, (unsigned int)(n) >> 2)) 81 82/* Maximum size of burst for vectorized Rx. */ 83#define MLX5_VPMD_RX_MAX_BURST 64U 84 85/* Recommended optimal burst size. */ 86#define MLX5_RX_DEFAULT_BURST 64U 87#define MLX5_TX_DEFAULT_BURST 64U 88 89/* Number of packets vectorized Rx can simultaneously process in a loop. */ 90#define MLX5_VPMD_DESCS_PER_LOOP 4 91 92/* Mask of RSS on source only or destination only. */ 93#define MLX5_RSS_SRC_DST_ONLY (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY | \ 94 ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY) 95 96/* Supported RSS */ 97#define MLX5_RSS_HF_MASK (~(ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP | \ 98 MLX5_RSS_SRC_DST_ONLY)) 99 100/* Timeout in seconds to get a valid link status. */ 101#define MLX5_LINK_STATUS_TIMEOUT 10 102 103/* Number of times to retry retrieving the physical link information. */ 104#define MLX5_GET_LINK_STATUS_RETRY_COUNT 3 105 106/* Maximum number of UAR pages used by a port, 107 * These are the size and mask for an array of mutexes used to synchronize 108 * the access to port's UARs on platforms that do not support 64 bit writes. 109 * In such systems it is possible to issue the 64 bits DoorBells through two 110 * consecutive writes, each write 32 bits. The access to a UAR page (which can 111 * be accessible by all threads in the process) must be synchronized 112 * (for example, using a semaphore). Such a synchronization is not required 113 * when ringing DoorBells on different UAR pages. 114 * A port with 512 Tx queues uses 8, 4kBytes, UAR pages which are shared 115 * among the ports. 116 */ 117#define MLX5_UAR_PAGE_NUM_MAX 64 118#define MLX5_UAR_PAGE_NUM_MASK ((MLX5_UAR_PAGE_NUM_MAX) - 1) 119 120/* Fields of memory mapping type in offset parameter of mmap() */ 121#define MLX5_UAR_MMAP_CMD_SHIFT 8 122#define MLX5_UAR_MMAP_CMD_MASK 0xff 123 124/* Environment variable to control the doorbell register mapping. */ 125#define MLX5_SHUT_UP_BF "MLX5_SHUT_UP_BF" 126#if defined(RTE_ARCH_ARM64) 127#define MLX5_SHUT_UP_BF_DEFAULT "0" 128#else 129#define MLX5_SHUT_UP_BF_DEFAULT "1" 130#endif 131 132#ifndef HAVE_MLX5DV_MMAP_GET_NC_PAGES_CMD 133#define MLX5_MMAP_GET_NC_PAGES_CMD 3 134#endif 135 136/* Log 2 of the default number of strides per WQE for Multi-Packet RQ. */ 137#define MLX5_MPRQ_STRIDE_NUM_N 6U 138 139/* Log 2 of the default size of a stride per WQE for Multi-Packet RQ. */ 140#define MLX5_MPRQ_STRIDE_SIZE_N 11U 141 142/* Two-byte shift is disabled for Multi-Packet RQ. */ 143#define MLX5_MPRQ_TWO_BYTE_SHIFT 0 144 145/* 146 * Minimum size of packet to be memcpy'd instead of being attached as an 147 * external buffer. 148 */ 149#define MLX5_MPRQ_MEMCPY_DEFAULT_LEN 128 150 151/* Minimum number Rx queues to enable Multi-Packet RQ. */ 152#define MLX5_MPRQ_MIN_RXQS 12 153 154/* Cache size of mempool for Multi-Packet RQ. */ 155#define MLX5_MPRQ_MP_CACHE_SZ 32U 156 157/* MLX5_DV_XMETA_EN supported values. */ 158#define MLX5_XMETA_MODE_LEGACY 0 159#define MLX5_XMETA_MODE_META16 1 160#define MLX5_XMETA_MODE_META32 2 161/* Provide info on patrial hw miss. Implies MLX5_XMETA_MODE_META16 */ 162#define MLX5_XMETA_MODE_MISS_INFO 3 163 164/* MLX5_TX_DB_NC supported values. */ 165#define MLX5_TXDB_CACHED 0 166#define MLX5_TXDB_NCACHED 1 167#define MLX5_TXDB_HEURISTIC 2 168 169/* Tx accurate scheduling on timestamps parameters. */ 170#define MLX5_TXPP_WAIT_INIT_TS 1000ul /* How long to wait timestamp. */ 171#define MLX5_TXPP_CLKQ_SIZE 1 172#define MLX5_TXPP_REARM ((1UL << MLX5_WQ_INDEX_WIDTH) / 4) 173#define MLX5_TXPP_REARM_SQ_SIZE (((1UL << MLX5_CQ_INDEX_WIDTH) / \ 174 MLX5_TXPP_REARM) * 2) 175#define MLX5_TXPP_REARM_CQ_SIZE (MLX5_TXPP_REARM_SQ_SIZE / 2) 176/* The minimal size test packet to put into one WQE, padded by HW. */ 177#define MLX5_TXPP_TEST_PKT_SIZE (sizeof(struct rte_ether_hdr) + \ 178 sizeof(struct rte_ipv4_hdr)) 179 180/* Size of the simple hash table for metadata register table. */ 181#define MLX5_FLOW_MREG_HTABLE_SZ 4096 182#define MLX5_FLOW_MREG_HNAME "MARK_COPY_TABLE" 183#define MLX5_DEFAULT_COPY_ID UINT32_MAX 184 185/* Size of the simple hash table for header modify table. */ 186#define MLX5_FLOW_HDR_MODIFY_HTABLE_SZ (1 << 16) 187 188/* Size of the simple hash table for encap decap table. */ 189#define MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ (1 << 16) 190 191/* Hairpin TX/RX queue configuration parameters. */ 192#define MLX5_HAIRPIN_QUEUE_STRIDE 6 193#define MLX5_HAIRPIN_JUMBO_LOG_SIZE (14 + 2) 194 195/* Maximum number of indirect actions supported by rte_flow */ 196#define MLX5_MAX_INDIRECT_ACTIONS 3 197 198/* 199 * Linux definition of static_assert is found in /usr/include/assert.h. 200 * Windows does not require a redefinition. 201 */ 202#if !defined(HAVE_STATIC_ASSERT) && !defined(RTE_EXEC_ENV_WINDOWS) 203#define static_assert _Static_assert 204#endif 205 206#endif /* RTE_PMD_MLX5_DEFS_H_ */ 207