LXR dpdk/lib/net/rte

   1/* SPDX-License-Identifier: BSD-3-Clause
   2 * Copyright(C) 2019 Marvell International Ltd.
   3 */
   4
   5#ifndef _RTE_HIGIG_H_
   6#define _RTE_HIGIG_H_
   7
   8/**
   9 * @file
  10 *
  11 * HIGIG2 headers definition.
  12 *
  13 * It is a layer 2.5 protocol and used in Broadcom switches.
  14 */
  15
  16#include <stdint.h>
  17#include <rte_byteorder.h>
  18
  19#ifdef __cplusplus
  20extern "C" {
  21#endif
  22
  23/**
  24 *
  25 * higig2 frc header.
  26 */
  27struct rte_higig2_frc {
  28#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
  29        uint32_t ksop:8;
  30        uint32_t tc:4;
  31        uint32_t mcst:1;
  32        uint32_t resv:3;
  33        uint32_t dst_modid:8;
  34        uint32_t dst_pid:8;
  35        uint32_t src_modid:8;
  36        uint32_t src_pid:8;
  37        uint32_t lbid:8;
  38        uint32_t ppd_type:3;
  39        uint32_t resv1:3;
  40        uint32_t dp:2;
  41#elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
  42        uint32_t ksop:8;
  43        uint32_t resv:3;
  44        uint32_t mcst:1;
  45        uint32_t tc:4;
  46        uint32_t dst_modid:8;
  47        uint32_t dst_pid:8;
  48        uint32_t src_modid:8;
  49        uint32_t src_pid:8;
  50        uint32_t lbid:8;
  51        uint32_t dp:2;
  52        uint32_t resv1:3;
  53        uint32_t ppd_type:3;
  54#endif
  55};
  56
  57
  58/**
  59 *
  60 * higig2 ppt type0 header
  61 */
  62struct rte_higig2_ppt_type0 {
  63#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
  64        uint32_t mirror:1;
  65        uint32_t mirror_done:1;
  66        uint32_t mirror_only:1;
  67        uint32_t ingress_tagged:1;
  68        uint32_t dst_tgid:3;
  69        uint32_t dst_t:1;
  70        uint32_t vc_label2:4;
  71        uint32_t label_present:1;
  72        uint32_t l3:1;
  73        uint32_t res:2;
  74        uint32_t vc_label1:8;
  75        uint32_t vc_label0:8;
  76        uint32_t vid_high:8;
  77        uint32_t vid_low:8;
  78        uint32_t opc:3;
  79        uint32_t res1:2;
  80        uint32_t srce_t:1;
  81        uint32_t pf:2;
  82        uint32_t res2:5;
  83        uint32_t hdr_ext_length:3;
  84#elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
  85        uint32_t dst_t:1;
  86        uint32_t dst_tgid:3;
  87        uint32_t ingress_tagged:1;
  88        uint32_t mirror_only:1;
  89        uint32_t mirror_done:1;
  90        uint32_t mirror:1;
  91        uint32_t res:2;
  92        uint32_t l3:1;
  93        uint32_t label_present:1;
  94        uint32_t vc_label2:4;
  95        uint32_t vc_label1:8;
  96        uint32_t vc_label0:8;
  97        uint32_t vid_high:8;
  98        uint32_t vid_low:8;
  99        uint32_t pf:2;
 100        uint32_t srce_t:1;
 101        uint32_t res1:2;
 102        uint32_t opc:3;
 103        uint32_t hdr_ext_length:3;
 104        uint32_t res2:5;
 105#endif
 106};
 107
 108
 109/**
 110 *
 111 * higig2 ppt type1 header.
 112 */
 113__extension__
 114struct rte_higig2_ppt_type1 {
 115        uint16_t classification;
 116        uint16_t resv;
 117        uint16_t vid;
 118#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
 119        uint16_t opcode:3;
 120        uint16_t resv1:2;
 121        uint16_t src_t:1;
 122        uint16_t pfm:2;
 123        uint16_t resv2:5;
 124        uint16_t hdr_ext_len:3;
 125#elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
 126        uint16_t pfm:2;
 127        uint16_t src_t:1;
 128        uint16_t resv1:2;
 129        uint16_t opcode:3;
 130        uint16_t hdr_ext_len:3;
 131        uint16_t resv2:5;
 132#endif
 133};
 134
 135/**
 136 *
 137 * higig2 header
 138 */
 139RTE_STD_C11
 140struct rte_higig2_hdr {
 141        struct rte_higig2_frc fcr;
 142        union {
 143                struct rte_higig2_ppt_type0 ppt0;
 144                struct rte_higig2_ppt_type1 ppt1;
 145        };
 146};
 147
 148#ifdef __cplusplus
 149}
 150#endif
 151
 152#endif /* RTE_HIGIG_H_ */
 153