1/* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Intel Corporation 3 */ 4 5/** 6 * @file Header file containing DPDK compilation parameters 7 * 8 * Header file containing DPDK compilation parameters. Also include the 9 * meson-generated header file containing the detected parameters that 10 * are variable across builds or build environments. 11 */ 12#ifndef _RTE_CONFIG_H_ 13#define _RTE_CONFIG_H_ 14 15#include <rte_build_config.h> 16 17/* legacy defines */ 18#ifdef RTE_EXEC_ENV_LINUX 19#define RTE_EXEC_ENV_LINUXAPP 1 20#endif 21#ifdef RTE_EXEC_ENV_FREEBSD 22#define RTE_EXEC_ENV_BSDAPP 1 23#endif 24 25/* String that appears before the version number */ 26#define RTE_VER_PREFIX "DPDK" 27 28/****** library defines ********/ 29 30/* EAL defines */ 31#define RTE_MAX_HEAPS 32 32#define RTE_MAX_MEMSEG_LISTS 128 33#define RTE_MAX_MEMSEG_PER_LIST 8192 34#define RTE_MAX_MEM_MB_PER_LIST 32768 35#define RTE_MAX_MEMSEG_PER_TYPE 32768 36#define RTE_MAX_MEM_MB_PER_TYPE 65536 37#define RTE_MAX_MEMZONE 2560 38#define RTE_MAX_TAILQ 32 39#define RTE_LOG_DP_LEVEL RTE_LOG_INFO 40#define RTE_BACKTRACE 1 41#define RTE_MAX_VFIO_CONTAINERS 64 42 43/* bsd module defines */ 44#define RTE_CONTIGMEM_MAX_NUM_BUFS 64 45#define RTE_CONTIGMEM_DEFAULT_NUM_BUFS 1 46#define RTE_CONTIGMEM_DEFAULT_BUF_SIZE (512*1024*1024) 47 48/* mempool defines */ 49#define RTE_MEMPOOL_CACHE_MAX_SIZE 512 50 51/* mbuf defines */ 52#define RTE_MBUF_DEFAULT_MEMPOOL_OPS "ring_mp_mc" 53#define RTE_MBUF_REFCNT_ATOMIC 1 54#define RTE_PKTMBUF_HEADROOM 128 55 56/* ether defines */ 57#define RTE_MAX_QUEUES_PER_PORT 1024 58#define RTE_ETHDEV_QUEUE_STAT_CNTRS 16 /* max 256 */ 59#define RTE_ETHDEV_RXTX_CALLBACKS 1 60#define RTE_MAX_MULTI_HOST_CTRLS 4 61 62/* cryptodev defines */ 63#define RTE_CRYPTO_MAX_DEVS 64 64#define RTE_CRYPTODEV_NAME_LEN 64 65#define RTE_CRYPTO_CALLBACKS 1 66 67/* compressdev defines */ 68#define RTE_COMPRESS_MAX_DEVS 64 69 70/* regexdev defines */ 71#define RTE_MAX_REGEXDEV_DEVS 32 72 73/* eventdev defines */ 74#define RTE_EVENT_MAX_DEVS 16 75#define RTE_EVENT_MAX_QUEUES_PER_DEV 255 76#define RTE_EVENT_TIMER_ADAPTER_NUM_MAX 32 77#define RTE_EVENT_ETH_INTR_RING_SIZE 1024 78#define RTE_EVENT_CRYPTO_ADAPTER_MAX_INSTANCE 32 79#define RTE_EVENT_ETH_TX_ADAPTER_MAX_INSTANCE 32 80 81/* rawdev defines */ 82#define RTE_RAWDEV_MAX_DEVS 64 83 84/* ip_fragmentation defines */ 85#define RTE_LIBRTE_IP_FRAG_MAX_FRAG 4 86#undef RTE_LIBRTE_IP_FRAG_TBL_STAT 87 88/* rte_power defines */ 89#define RTE_MAX_LCORE_FREQS 64 90 91/* rte_sched defines */ 92#undef RTE_SCHED_RED 93#undef RTE_SCHED_COLLECT_STATS 94#undef RTE_SCHED_SUBPORT_TC_OV 95#define RTE_SCHED_PORT_N_GRINDERS 8 96#undef RTE_SCHED_VECTOR 97 98/* KNI defines */ 99#define RTE_KNI_PREEMPT_DEFAULT 1 100 101/* rte_graph defines */ 102#define RTE_GRAPH_BURST_SIZE 256 103#define RTE_LIBRTE_GRAPH_STATS 1 104 105/****** driver defines ********/ 106 107/* Packet prefetching in PMDs */ 108#define RTE_PMD_PACKET_PREFETCH 1 109 110/* QuickAssist device */ 111/* Max. number of QuickAssist devices which can be attached */ 112#define RTE_PMD_QAT_MAX_PCI_DEVICES 48 113#define RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS 16 114#define RTE_PMD_QAT_COMP_IM_BUFFER_SIZE 65536 115 116/* virtio crypto defines */ 117#define RTE_MAX_VIRTIO_CRYPTO 32 118 119/* DPAA SEC max cryptodev devices*/ 120#define RTE_LIBRTE_DPAA_MAX_CRYPTODEV 4 121 122/* fm10k defines */ 123#define RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE 1 124 125/* hns3 defines */ 126#define RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF 256 127 128/* i40e defines */ 129#define RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC 1 130#undef RTE_LIBRTE_I40E_16BYTE_RX_DESC 131#define RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF 64 132#define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4 133#define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM 4 134 135/* Ring net PMD settings */ 136#define RTE_PMD_RING_MAX_RX_RINGS 16 137#define RTE_PMD_RING_MAX_TX_RINGS 16 138 139/* QEDE PMD defines */ 140#define RTE_LIBRTE_QEDE_FW "" 141 142/* DLB2 defines */ 143#undef RTE_LIBRTE_PMD_DLB2_QUELL_STATS 144 145#endif /* _RTE_CONFIG_H_ */ 146