LXR dpdk/drivers/bus/fslmc/portal/dpaa2_hw

   1/* SPDX-License-Identifier: BSD-3-Clause
   2 *
   3 *   Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
   4 *   Copyright 2016-2020 NXP
   5 *
   6 */
   7
   8#ifndef _DPAA2_HW_PVT_H_
   9#define _DPAA2_HW_PVT_H_
  10
  11#include <rte_eventdev.h>
  12#include <dpaax_iova_table.h>
  13
  14#include <mc/fsl_mc_sys.h>
  15#include <fsl_qbman_portal.h>
  16
  17#ifndef false
  18#define false      0
  19#endif
  20#ifndef true
  21#define true       1
  22#endif
  23#define lower_32_bits(x) ((uint32_t)(x))
  24#define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16))
  25
  26#ifndef VLAN_TAG_SIZE
  27#define VLAN_TAG_SIZE   4 /** < Vlan Header Length */
  28#endif
  29
  30/* Maximum number of slots available in TX ring */
  31#define MAX_TX_RING_SLOTS                       32
  32#define MAX_EQ_RESP_ENTRIES                     (MAX_TX_RING_SLOTS + 1)
  33
  34/* Maximum number of slots available in RX ring */
  35#define DPAA2_EQCR_RING_SIZE            8
  36/* Maximum number of slots available in RX ring on LX2 */
  37#define DPAA2_LX2_EQCR_RING_SIZE        32
  38
  39/* Maximum number of slots available in RX ring */
  40#define DPAA2_DQRR_RING_SIZE            16
  41/* Maximum number of slots available in RX ring on LX2 */
  42#define DPAA2_LX2_DQRR_RING_SIZE        32
  43
  44/* EQCR shift to get EQCR size (2 >> 3) = 8 for LS2/LS2 */
  45#define DPAA2_EQCR_SHIFT                3
  46/* EQCR shift to get EQCR size for LX2 (2 >> 5) = 32 for LX2 */
  47#define DPAA2_LX2_EQCR_SHIFT            5
  48
  49/* Flag to determine an ordered queue mbuf */
  50#define DPAA2_ENQUEUE_FLAG_ORP          (1ULL << 30)
  51/* ORP ID shift and mask */
  52#define DPAA2_EQCR_OPRID_SHIFT          16
  53#define DPAA2_EQCR_OPRID_MASK           0x3FFF0000
  54/* Sequence number shift and mask */
  55#define DPAA2_EQCR_SEQNUM_SHIFT         0
  56#define DPAA2_EQCR_SEQNUM_MASK          0x0000FFFF
  57
  58#define DPAA2_SWP_CENA_REGION           0
  59#define DPAA2_SWP_CINH_REGION           1
  60#define DPAA2_SWP_CENA_MEM_REGION       2
  61
  62#define DPAA2_MAX_TX_RETRY_COUNT        10000
  63
  64#define MC_PORTAL_INDEX         0
  65#define NUM_DPIO_REGIONS        2
  66#define NUM_DQS_PER_QUEUE       2
  67
  68/* Maximum release/acquire from QBMAN */
  69#define DPAA2_MBUF_MAX_ACQ_REL  7
  70
  71#define DPAA2_MEMPOOL_OPS_NAME          "dpaa2"
  72
  73#define MAX_BPID 256
  74#define DPAA2_MBUF_HW_ANNOTATION        64
  75#define DPAA2_FD_PTA_SIZE               0
  76
  77/* we will re-use the HEADROOM for annotation in RX */
  78#define DPAA2_HW_BUF_RESERVE    0
  79#define DPAA2_PACKET_LAYOUT_ALIGN       64 /*changing from 256 */
  80
  81#define DPAA2_DPCI_MAX_QUEUES 2
  82
  83struct dpaa2_queue;
  84
  85struct eqresp_metadata {
  86        struct dpaa2_queue *dpaa2_q;
  87        struct rte_mempool *mp;
  88};
  89
  90#define DPAA2_PORTAL_DEQUEUE_DEPTH      32
  91struct dpaa2_portal_dqrr {
  92        struct rte_mbuf *mbuf[DPAA2_PORTAL_DEQUEUE_DEPTH];
  93        uint64_t dqrr_held;
  94        uint8_t dqrr_size;
  95};
  96
  97struct dpaa2_dpio_dev {
  98        TAILQ_ENTRY(dpaa2_dpio_dev) next;
  99                /**< Pointer to Next device instance */
 100        uint16_t index; /**< Index of a instance in the list */
 101        rte_atomic16_t ref_count;
 102                /**< How many thread contexts are sharing this.*/
 103        uint16_t eqresp_ci;
 104        uint16_t eqresp_pi;
 105        struct qbman_result *eqresp;
 106        struct eqresp_metadata *eqresp_meta;
 107        struct fsl_mc_io *dpio; /** handle to DPIO portal object */
 108        uint16_t token;
 109        struct qbman_swp *sw_portal; /** SW portal object */
 110        const struct qbman_result *dqrr[4];
 111                /**< DQRR Entry for this SW portal */
 112        void *mc_portal; /**< MC Portal for configuring this device */
 113        uintptr_t qbman_portal_ce_paddr;
 114                /**< Physical address of Cache Enabled Area */
 115        uintptr_t ce_size; /**< Size of the CE region */
 116        uintptr_t qbman_portal_ci_paddr;
 117                /**< Physical address of Cache Inhibit Area */
 118        uintptr_t ci_size; /**< Size of the CI region */
 119        struct rte_intr_handle intr_handle; /* Interrupt related info */
 120        int32_t epoll_fd; /**< File descriptor created for interrupt polling */
 121        int32_t hw_id; /**< An unique ID of this DPIO device instance */
 122        struct dpaa2_portal_dqrr dpaa2_held_bufs;
 123};
 124
 125struct dpaa2_dpbp_dev {
 126        TAILQ_ENTRY(dpaa2_dpbp_dev) next;
 127                /**< Pointer to Next device instance */
 128        struct fsl_mc_io dpbp;  /** handle to DPBP portal object */
 129        uint16_t token;
 130        rte_atomic16_t in_use;
 131        uint32_t dpbp_id; /*HW ID for DPBP object */
 132};
 133
 134struct queue_storage_info_t {
 135        struct qbman_result *dq_storage[NUM_DQS_PER_QUEUE];
 136        struct qbman_result *active_dqs;
 137        uint8_t active_dpio_id;
 138        uint8_t toggle;
 139        uint8_t last_num_pkts;
 140};
 141
 142struct dpaa2_queue;
 143
 144typedef void (dpaa2_queue_cb_dqrr_t)(struct qbman_swp *swp,
 145                const struct qbman_fd *fd,
 146                const struct qbman_result *dq,
 147                struct dpaa2_queue *rxq,
 148                struct rte_event *ev);
 149
 150typedef void (dpaa2_queue_cb_eqresp_free_t)(uint16_t eqresp_ci);
 151
 152struct dpaa2_queue {
 153        struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
 154        union {
 155                struct rte_eth_dev_data *eth_data;
 156                struct rte_cryptodev_data *crypto_data;
 157        };
 158        uint32_t fqid;          /*!< Unique ID of this queue */
 159        uint16_t flow_id;       /*!< To be used by DPAA2 frmework */
 160        uint8_t tc_index;       /*!< traffic class identifier */
 161        uint8_t cgid;           /*! < Congestion Group id for this queue */
 162        uint64_t rx_pkts;
 163        uint64_t tx_pkts;
 164        uint64_t err_pkts;
 165        union {
 166                struct queue_storage_info_t *q_storage;
 167                struct qbman_result *cscn;
 168        };
 169        struct rte_event ev;
 170        dpaa2_queue_cb_dqrr_t *cb;
 171        dpaa2_queue_cb_eqresp_free_t *cb_eqresp_free;
 172        struct dpaa2_bp_info *bp_array;
 173        /*to store tx_conf_queue corresponding to tx_queue*/
 174        struct dpaa2_queue *tx_conf_queue;
 175        int32_t eventfd;        /*!< Event Fd of this queue */
 176        uint16_t nb_desc;
 177        uint16_t resv;
 178        uint64_t offloads;
 179} __rte_cache_aligned;
 180
 181struct swp_active_dqs {
 182        struct qbman_result *global_active_dqs;
 183        uint64_t reserved[7];
 184};
 185
 186#define NUM_MAX_SWP 64
 187
 188extern struct swp_active_dqs rte_global_active_dqs_list[NUM_MAX_SWP];
 189
 190struct dpaa2_dpci_dev {
 191        TAILQ_ENTRY(dpaa2_dpci_dev) next;
 192                /**< Pointer to Next device instance */
 193        struct fsl_mc_io dpci;  /** handle to DPCI portal object */
 194        uint16_t token;
 195        rte_atomic16_t in_use;
 196        uint32_t dpci_id; /*HW ID for DPCI object */
 197        struct dpaa2_queue rx_queue[DPAA2_DPCI_MAX_QUEUES];
 198        struct dpaa2_queue tx_queue[DPAA2_DPCI_MAX_QUEUES];
 199};
 200
 201struct dpaa2_dpcon_dev {
 202        TAILQ_ENTRY(dpaa2_dpcon_dev) next;
 203        struct fsl_mc_io dpcon;
 204        uint16_t token;
 205        rte_atomic16_t in_use;
 206        uint32_t dpcon_id;
 207        uint16_t qbman_ch_id;
 208        uint8_t num_priorities;
 209        uint8_t channel_index;
 210};
 211
 212/* Refer to Table 7-3 in SEC BG */
 213#define QBMAN_FLE_WORD4_FMT_SBF 0x0    /* Single buffer frame */
 214#define QBMAN_FLE_WORD4_FMT_SGE 0x2 /* Scatter gather frame */
 215
 216struct qbman_fle_word4 {
 217        uint32_t bpid:14; /* Frame buffer pool ID */
 218        uint32_t ivp:1; /* Invalid Pool ID. */
 219        uint32_t bmt:1; /* Bypass Memory Translation */
 220        uint32_t offset:12; /* Frame offset */
 221        uint32_t fmt:2; /* Frame Format */
 222        uint32_t sl:1; /* Short Length */
 223        uint32_t f:1; /* Final bit */
 224};
 225
 226struct qbman_fle {
 227        uint32_t addr_lo;
 228        uint32_t addr_hi;
 229        uint32_t length;
 230        /* FMT must be 00, MSB is final bit  */
 231        union {
 232                uint32_t fin_bpid_offset;
 233                struct qbman_fle_word4 word4;
 234        };
 235        uint32_t frc;
 236        uint32_t reserved[3]; /* Not used currently */
 237};
 238
 239struct qbman_sge {
 240        uint32_t addr_lo;
 241        uint32_t addr_hi;
 242        uint32_t length;
 243        uint32_t fin_bpid_offset;
 244};
 245
 246/* There are three types of frames: Single, Scatter Gather and Frame Lists */
 247enum qbman_fd_format {
 248        qbman_fd_single = 0,
 249        qbman_fd_list,
 250        qbman_fd_sg
 251};
 252/*Macros to define operations on FD*/
 253#define DPAA2_SET_FD_ADDR(fd, addr) do {                        \
 254        (fd)->simple.addr_lo = lower_32_bits((size_t)(addr));   \
 255        (fd)->simple.addr_hi = upper_32_bits((uint64_t)(addr)); \
 256} while (0)
 257#define DPAA2_SET_FD_LEN(fd, length)    ((fd)->simple.len = length)
 258#define DPAA2_SET_FD_BPID(fd, bpid)     ((fd)->simple.bpid_offset |= bpid)
 259#define DPAA2_SET_ONLY_FD_BPID(fd, bpid) \
 260        ((fd)->simple.bpid_offset = bpid)
 261#define DPAA2_SET_FD_IVP(fd)   (((fd)->simple.bpid_offset |= 0x00004000))
 262#define DPAA2_SET_FD_OFFSET(fd, offset) \
 263        (((fd)->simple.bpid_offset |= (uint32_t)(offset) << 16))
 264#define DPAA2_SET_FD_INTERNAL_JD(fd, len) \
 265        ((fd)->simple.frc = (0x80000000 | (len)))
 266#define DPAA2_GET_FD_FRC_PARSE_SUM(fd)  \
 267                        ((uint16_t)(((fd)->simple.frc & 0xffff0000) >> 16))
 268#define DPAA2_RESET_FD_FRC(fd)          ((fd)->simple.frc = 0)
 269#define DPAA2_SET_FD_FRC(fd, _frc)      ((fd)->simple.frc = _frc)
 270#define DPAA2_RESET_FD_CTRL(fd)  ((fd)->simple.ctrl = 0)
 271
 272#define DPAA2_SET_FD_ASAL(fd, asal)     ((fd)->simple.ctrl |= (asal << 16))
 273
 274#define DPAA2_RESET_FD_FLC(fd)  do {    \
 275        (fd)->simple.flc_lo = 0;        \
 276        (fd)->simple.flc_hi = 0;        \
 277} while (0)
 278
 279#define DPAA2_SET_FD_FLC(fd, addr)      do { \
 280        (fd)->simple.flc_lo = lower_32_bits((size_t)(addr));    \
 281        (fd)->simple.flc_hi = upper_32_bits((uint64_t)(addr));  \
 282} while (0)
 283#define DPAA2_SET_FLE_INTERNAL_JD(fle, len) ((fle)->frc = (0x80000000 | (len)))
 284#define DPAA2_GET_FLE_ADDR(fle)                                 \
 285        (size_t)((((uint64_t)((fle)->addr_hi)) << 32) + (fle)->addr_lo)
 286#define DPAA2_SET_FLE_ADDR(fle, addr) do { \
 287        (fle)->addr_lo = lower_32_bits((size_t)addr);           \
 288        (fle)->addr_hi = upper_32_bits((uint64_t)addr);         \
 289} while (0)
 290#define DPAA2_GET_FLE_CTXT(fle)                                 \
 291        ((((uint64_t)((fle)->reserved[1])) << 32) + (fle)->reserved[0])
 292#define DPAA2_FLE_SAVE_CTXT(fle, addr) do { \
 293        (fle)->reserved[0] = lower_32_bits((size_t)addr);       \
 294        (fle)->reserved[1] = upper_32_bits((uint64_t)addr);     \
 295} while (0)
 296#define DPAA2_SET_FLE_OFFSET(fle, offset) \
 297        ((fle)->fin_bpid_offset |= (uint32_t)(offset) << 16)
 298#define DPAA2_SET_FLE_LEN(fle, len)    ((fle)->length = len)
 299#define DPAA2_SET_FLE_BPID(fle, bpid) ((fle)->fin_bpid_offset |= (size_t)bpid)
 300#define DPAA2_GET_FLE_BPID(fle) ((fle)->fin_bpid_offset & 0x000000ff)
 301#define DPAA2_SET_FLE_FIN(fle)  ((fle)->fin_bpid_offset |= 1 << 31)
 302#define DPAA2_SET_FLE_IVP(fle)   (((fle)->fin_bpid_offset |= 0x00004000))
 303#define DPAA2_SET_FLE_BMT(fle)   (((fle)->fin_bpid_offset |= 0x00008000))
 304#define DPAA2_SET_FD_COMPOUND_FMT(fd)   \
 305        ((fd)->simple.bpid_offset |= (uint32_t)1 << 28)
 306#define DPAA2_GET_FD_ADDR(fd)   \
 307(((((uint64_t)((fd)->simple.addr_hi)) << 32) + (fd)->simple.addr_lo))
 308
 309#define DPAA2_GET_FD_LEN(fd)    ((fd)->simple.len)
 310#define DPAA2_GET_FD_BPID(fd)   (((fd)->simple.bpid_offset & 0x00003FFF))
 311#define DPAA2_GET_FD_IVP(fd)   (((fd)->simple.bpid_offset & 0x00004000) >> 14)
 312#define DPAA2_GET_FD_OFFSET(fd) (((fd)->simple.bpid_offset & 0x0FFF0000) >> 16)
 313#define DPAA2_GET_FD_FRC(fd)   ((fd)->simple.frc)
 314#define DPAA2_GET_FD_FLC(fd) \
 315        (((uint64_t)((fd)->simple.flc_hi) << 32) + (fd)->simple.flc_lo)
 316#define DPAA2_GET_FD_ERR(fd)   ((fd)->simple.ctrl & 0x000000FF)
 317#define DPAA2_GET_FD_FA_ERR(fd)   ((fd)->simple.ctrl & 0x00000040)
 318#define DPAA2_GET_FLE_OFFSET(fle) (((fle)->fin_bpid_offset & 0x0FFF0000) >> 16)
 319#define DPAA2_SET_FLE_SG_EXT(fle) ((fle)->fin_bpid_offset |= (uint64_t)1 << 29)
 320#define DPAA2_IS_SET_FLE_SG_EXT(fle)    \
 321        (((fle)->fin_bpid_offset & ((uint64_t)1 << 29)) ? 1 : 0)
 322
 323#define DPAA2_INLINE_MBUF_FROM_BUF(buf, meta_data_size) \
 324        ((struct rte_mbuf *)((size_t)(buf) - (meta_data_size)))
 325
 326#define DPAA2_ASAL_VAL (DPAA2_MBUF_HW_ANNOTATION / 64)
 327
 328#define DPAA2_FD_SET_FORMAT(fd, format) do {                            \
 329                (fd)->simple.bpid_offset &= 0xCFFFFFFF;                 \
 330                (fd)->simple.bpid_offset |= (uint32_t)format << 28;     \
 331} while (0)
 332#define DPAA2_FD_GET_FORMAT(fd) (((fd)->simple.bpid_offset >> 28) & 0x3)
 333
 334#define DPAA2_SG_SET_FORMAT(sg, format) do {                            \
 335                (sg)->fin_bpid_offset &= 0xCFFFFFFF;                    \
 336                (sg)->fin_bpid_offset |= (uint32_t)format << 28;        \
 337} while (0)
 338
 339#define DPAA2_SG_SET_FINAL(sg, fin)     do {                            \
 340                (sg)->fin_bpid_offset &= 0x7FFFFFFF;                    \
 341                (sg)->fin_bpid_offset |= (uint32_t)fin << 31;           \
 342} while (0)
 343#define DPAA2_SG_IS_FINAL(sg) (!!((sg)->fin_bpid_offset >> 31))
 344/* Only Enqueue Error responses will be
 345 * pushed on FQID_ERR of Enqueue FQ
 346 */
 347#define DPAA2_EQ_RESP_ERR_FQ            0
 348/* All Enqueue responses will be pushed on address
 349 * set with qbman_eq_desc_set_response
 350 */
 351#define DPAA2_EQ_RESP_ALWAYS            1
 352
 353/* Various structures representing contiguous memory maps */
 354struct dpaa2_memseg {
 355        TAILQ_ENTRY(dpaa2_memseg) next;
 356        char *vaddr;
 357        rte_iova_t iova;
 358        size_t len;
 359};
 360
 361#ifdef RTE_LIBRTE_DPAA2_USE_PHYS_IOVA
 362extern uint8_t dpaa2_virt_mode;
 363static void *dpaa2_mem_ptov(phys_addr_t paddr) __rte_unused;
 364
 365static void *dpaa2_mem_ptov(phys_addr_t paddr)
 366{
 367        void *va;
 368
 369        if (dpaa2_virt_mode)
 370                return (void *)(size_t)paddr;
 371
 372        va = (void *)dpaax_iova_table_get_va(paddr);
 373        if (likely(va != NULL))
 374                return va;
 375
 376        /* If not, Fallback to full memseg list searching */
 377        va = rte_mem_iova2virt(paddr);
 378
 379        return va;
 380}
 381
 382static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr) __rte_unused;
 383
 384static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr)
 385{
 386        const struct rte_memseg *memseg;
 387
 388        if (dpaa2_virt_mode)
 389                return vaddr;
 390
 391        memseg = rte_mem_virt2memseg((void *)(uintptr_t)vaddr, NULL);
 392        if (memseg)
 393                return memseg->iova + RTE_PTR_DIFF(vaddr, memseg->addr);
 394        return (size_t)NULL;
 395}
 396
 397/**
 398 * When we are using Physical addresses as IO Virtual Addresses,
 399 * Need to call conversion routines dpaa2_mem_vtop & dpaa2_mem_ptov
 400 * wherever required.
 401 * These routines are called with help of below MACRO's
 402 */
 403
 404#define DPAA2_MBUF_VADDR_TO_IOVA(mbuf) ((mbuf)->buf_iova)
 405
 406/**
 407 * macro to convert Virtual address to IOVA
 408 */
 409#define DPAA2_VADDR_TO_IOVA(_vaddr) dpaa2_mem_vtop((size_t)(_vaddr))
 410
 411/**
 412 * macro to convert IOVA to Virtual address
 413 */
 414#define DPAA2_IOVA_TO_VADDR(_iova) dpaa2_mem_ptov((size_t)(_iova))
 415
 416/**
 417 * macro to convert modify the memory containing IOVA to Virtual address
 418 */
 419#define DPAA2_MODIFY_IOVA_TO_VADDR(_mem, _type) \
 420        {_mem = (_type)(dpaa2_mem_ptov((size_t)(_mem))); }
 421
 422#else   /* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */
 423
 424#define DPAA2_MBUF_VADDR_TO_IOVA(mbuf) ((mbuf)->buf_addr)
 425#define DPAA2_VADDR_TO_IOVA(_vaddr) (phys_addr_t)(_vaddr)
 426#define DPAA2_IOVA_TO_VADDR(_iova) (void *)(_iova)
 427#define DPAA2_MODIFY_IOVA_TO_VADDR(_mem, _type)
 428
 429#endif /* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */
 430
 431static inline
 432int check_swp_active_dqs(uint16_t dpio_index)
 433{
 434        if (rte_global_active_dqs_list[dpio_index].global_active_dqs != NULL)
 435                return 1;
 436        return 0;
 437}
 438
 439static inline
 440void clear_swp_active_dqs(uint16_t dpio_index)
 441{
 442        rte_global_active_dqs_list[dpio_index].global_active_dqs = NULL;
 443}
 444
 445static inline
 446struct qbman_result *get_swp_active_dqs(uint16_t dpio_index)
 447{
 448        return rte_global_active_dqs_list[dpio_index].global_active_dqs;
 449}
 450
 451static inline
 452void set_swp_active_dqs(uint16_t dpio_index, struct qbman_result *dqs)
 453{
 454        rte_global_active_dqs_list[dpio_index].global_active_dqs = dqs;
 455}
 456
 457__rte_internal
 458struct dpaa2_dpbp_dev *dpaa2_alloc_dpbp_dev(void);
 459
 460__rte_internal
 461void dpaa2_free_dpbp_dev(struct dpaa2_dpbp_dev *dpbp);
 462
 463__rte_internal
 464int dpaa2_dpbp_supported(void);
 465
 466__rte_internal
 467struct dpaa2_dpci_dev *rte_dpaa2_alloc_dpci_dev(void);
 468
 469__rte_internal
 470void rte_dpaa2_free_dpci_dev(struct dpaa2_dpci_dev *dpci);
 471
 472/* Global MCP pointer */
 473__rte_internal
 474void *dpaa2_get_mcp_ptr(int portal_idx);
 475
 476#endif
 477