1/* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 6#define MYPF_BASE 0x1b000 7#define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr)) 8 9#define PF0_BASE 0x1e000 10#define PF0_REG(reg_addr) (PF0_BASE + (reg_addr)) 11 12#define PF_STRIDE 0x400 13#define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE) 14#define PF_REG(idx, reg) (PF_BASE(idx) + (reg)) 15 16#define MYPORT_BASE 0x1c000 17#define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr)) 18 19#define PORT0_BASE 0x20000 20#define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr)) 21 22#define PORT_STRIDE 0x2000 23#define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE) 24#define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg)) 25 26#define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) 27#define NUM_PCIE_MEM_ACCESS_INSTANCES 8 28 29#define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 30#define NUM_PCIE_FW_INSTANCES 8 31 32#define T5_MYPORT_BASE 0x2c000 33#define T5_MYPORT_REG(reg_addr) (T5_MYPORT_BASE + (reg_addr)) 34 35#define T5_PORT0_BASE 0x30000 36#define T5_PORT0_REG(reg_addr) (T5_PORT0_BASE + (reg_addr)) 37 38#define T5_PORT_STRIDE 0x4000 39#define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE) 40#define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg)) 41 42#define MPS_T5_CLS_SRAM_L(idx) (A_MPS_T5_CLS_SRAM_L + (idx) * 8) 43#define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512 44 45#define MPS_T5_CLS_SRAM_H(idx) (A_MPS_T5_CLS_SRAM_H + (idx) * 8) 46#define NUM_MPS_T5_CLS_SRAM_H_INSTANCES 512 47 48#define S_DATAPORTNUM 12 49#define M_DATAPORTNUM 0xfU 50#define V_DATAPORTNUM(x) ((x) << S_DATAPORTNUM) 51 52#define S_DATALKPTYPE 10 53#define M_DATALKPTYPE 0x3U 54#define V_DATALKPTYPE(x) ((x) << S_DATALKPTYPE) 55 56/* registers for module SGE */ 57#define SGE_BASE_ADDR 0x1000 58 59#define A_SGE_PF_KDOORBELL 0x0 60#define A_SGE_VF_KDOORBELL 0x0 61 62#define S_QID 15 63#define M_QID 0x1ffffU 64#define V_QID(x) ((x) << S_QID) 65#define G_QID(x) (((x) >> S_QID) & M_QID) 66 67#define S_DBPRIO 14 68#define V_DBPRIO(x) ((x) << S_DBPRIO) 69#define F_DBPRIO V_DBPRIO(1U) 70 71#define S_PIDX 0 72#define M_PIDX 0x3fffU 73#define V_PIDX(x) ((x) << S_PIDX) 74#define G_PIDX(x) (((x) >> S_PIDX) & M_PIDX) 75 76#define S_DBTYPE 13 77#define V_DBTYPE(x) ((x) << S_DBTYPE) 78#define F_DBTYPE V_DBTYPE(1U) 79 80#define S_PIDX_T5 0 81#define M_PIDX_T5 0x1fffU 82#define V_PIDX_T5(x) ((x) << S_PIDX_T5) 83#define G_PIDX_T5(x) (((x) >> S_PIDX_T5) & M_PIDX_T5) 84 85#define A_SGE_PF_GTS 0x4 86 87#define T4VF_SGE_BASE_ADDR 0x0000 88#define A_SGE_VF_GTS 0x4 89 90#define S_INGRESSQID 16 91#define M_INGRESSQID 0xffffU 92#define V_INGRESSQID(x) ((x) << S_INGRESSQID) 93#define G_INGRESSQID(x) (((x) >> S_INGRESSQID) & M_INGRESSQID) 94 95#define S_SEINTARM 12 96#define V_SEINTARM(x) ((x) << S_SEINTARM) 97#define F_SEINTARM V_SEINTARM(1U) 98 99#define S_CIDXINC 0 100#define M_CIDXINC 0xfffU 101#define V_CIDXINC(x) ((x) << S_CIDXINC) 102#define G_CIDXINC(x) (((x) >> S_CIDXINC) & M_CIDXINC) 103 104#define A_SGE_CONTROL 0x1008 105 106#define S_RXPKTCPLMODE 18 107#define V_RXPKTCPLMODE(x) ((x) << S_RXPKTCPLMODE) 108#define F_RXPKTCPLMODE V_RXPKTCPLMODE(1U) 109 110#define S_EGRSTATUSPAGESIZE 17 111#define V_EGRSTATUSPAGESIZE(x) ((x) << S_EGRSTATUSPAGESIZE) 112#define F_EGRSTATUSPAGESIZE V_EGRSTATUSPAGESIZE(1U) 113 114#define S_PKTSHIFT 10 115#define M_PKTSHIFT 0x7U 116#define V_PKTSHIFT(x) ((x) << S_PKTSHIFT) 117#define G_PKTSHIFT(x) (((x) >> S_PKTSHIFT) & M_PKTSHIFT) 118 119#define S_INGPADBOUNDARY 4 120#define M_INGPADBOUNDARY 0x7U 121#define V_INGPADBOUNDARY(x) ((x) << S_INGPADBOUNDARY) 122#define G_INGPADBOUNDARY(x) (((x) >> S_INGPADBOUNDARY) & M_INGPADBOUNDARY) 123 124#define A_SGE_HOST_PAGE_SIZE 0x100c 125 126#define S_HOSTPAGESIZEPF7 28 127#define M_HOSTPAGESIZEPF7 0xfU 128#define V_HOSTPAGESIZEPF7(x) ((x) << S_HOSTPAGESIZEPF7) 129#define G_HOSTPAGESIZEPF7(x) (((x) >> S_HOSTPAGESIZEPF7) & M_HOSTPAGESIZEPF7) 130 131#define S_HOSTPAGESIZEPF6 24 132#define M_HOSTPAGESIZEPF6 0xfU 133#define V_HOSTPAGESIZEPF6(x) ((x) << S_HOSTPAGESIZEPF6) 134#define G_HOSTPAGESIZEPF6(x) (((x) >> S_HOSTPAGESIZEPF6) & M_HOSTPAGESIZEPF6) 135 136#define S_HOSTPAGESIZEPF5 20 137#define M_HOSTPAGESIZEPF5 0xfU 138#define V_HOSTPAGESIZEPF5(x) ((x) << S_HOSTPAGESIZEPF5) 139#define G_HOSTPAGESIZEPF5(x) (((x) >> S_HOSTPAGESIZEPF5) & M_HOSTPAGESIZEPF5) 140 141#define S_HOSTPAGESIZEPF4 16 142#define M_HOSTPAGESIZEPF4 0xfU 143#define V_HOSTPAGESIZEPF4(x) ((x) << S_HOSTPAGESIZEPF4) 144#define G_HOSTPAGESIZEPF4(x) (((x) >> S_HOSTPAGESIZEPF4) & M_HOSTPAGESIZEPF4) 145 146#define S_HOSTPAGESIZEPF3 12 147#define M_HOSTPAGESIZEPF3 0xfU 148#define V_HOSTPAGESIZEPF3(x) ((x) << S_HOSTPAGESIZEPF3) 149#define G_HOSTPAGESIZEPF3(x) (((x) >> S_HOSTPAGESIZEPF3) & M_HOSTPAGESIZEPF3) 150 151#define S_HOSTPAGESIZEPF2 8 152#define M_HOSTPAGESIZEPF2 0xfU 153#define V_HOSTPAGESIZEPF2(x) ((x) << S_HOSTPAGESIZEPF2) 154#define G_HOSTPAGESIZEPF2(x) (((x) >> S_HOSTPAGESIZEPF2) & M_HOSTPAGESIZEPF2) 155 156#define S_HOSTPAGESIZEPF1 4 157#define M_HOSTPAGESIZEPF1 0xfU 158#define V_HOSTPAGESIZEPF1(x) ((x) << S_HOSTPAGESIZEPF1) 159#define G_HOSTPAGESIZEPF1(x) (((x) >> S_HOSTPAGESIZEPF1) & M_HOSTPAGESIZEPF1) 160 161#define S_HOSTPAGESIZEPF0 0 162#define M_HOSTPAGESIZEPF0 0xfU 163#define V_HOSTPAGESIZEPF0(x) ((x) << S_HOSTPAGESIZEPF0) 164#define G_HOSTPAGESIZEPF0(x) (((x) >> S_HOSTPAGESIZEPF0) & M_HOSTPAGESIZEPF0) 165 166#define A_SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010 167 168#define S_QUEUESPERPAGEPF1 4 169#define M_QUEUESPERPAGEPF1 0xfU 170#define V_QUEUESPERPAGEPF1(x) ((x) << S_QUEUESPERPAGEPF1) 171#define G_QUEUESPERPAGEPF1(x) (((x) >> S_QUEUESPERPAGEPF1) & M_QUEUESPERPAGEPF1) 172 173#define S_QUEUESPERPAGEPF0 0 174#define M_QUEUESPERPAGEPF0 0xfU 175#define V_QUEUESPERPAGEPF0(x) ((x) << S_QUEUESPERPAGEPF0) 176#define G_QUEUESPERPAGEPF0(x) (((x) >> S_QUEUESPERPAGEPF0) & M_QUEUESPERPAGEPF0) 177 178#define A_SGE_EGRESS_QUEUES_PER_PAGE_VF 0x1014 179 180#define S_ERR_CPL_EXCEED_IQE_SIZE 22 181#define V_ERR_CPL_EXCEED_IQE_SIZE(x) ((x) << S_ERR_CPL_EXCEED_IQE_SIZE) 182#define F_ERR_CPL_EXCEED_IQE_SIZE V_ERR_CPL_EXCEED_IQE_SIZE(1U) 183 184#define S_ERR_INVALID_CIDX_INC 21 185#define V_ERR_INVALID_CIDX_INC(x) ((x) << S_ERR_INVALID_CIDX_INC) 186#define F_ERR_INVALID_CIDX_INC V_ERR_INVALID_CIDX_INC(1U) 187 188#define S_ERR_CPL_OPCODE_0 19 189#define V_ERR_CPL_OPCODE_0(x) ((x) << S_ERR_CPL_OPCODE_0) 190#define F_ERR_CPL_OPCODE_0 V_ERR_CPL_OPCODE_0(1U) 191 192#define S_ERR_DROPPED_DB 18 193#define V_ERR_DROPPED_DB(x) ((x) << S_ERR_DROPPED_DB) 194#define F_ERR_DROPPED_DB V_ERR_DROPPED_DB(1U) 195 196#define S_ERR_DATA_CPL_ON_HIGH_QID1 17 197#define V_ERR_DATA_CPL_ON_HIGH_QID1(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID1) 198#define F_ERR_DATA_CPL_ON_HIGH_QID1 V_ERR_DATA_CPL_ON_HIGH_QID1(1U) 199 200#define S_ERR_DATA_CPL_ON_HIGH_QID0 16 201#define V_ERR_DATA_CPL_ON_HIGH_QID0(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID0) 202#define F_ERR_DATA_CPL_ON_HIGH_QID0 V_ERR_DATA_CPL_ON_HIGH_QID0(1U) 203 204#define S_ERR_BAD_DB_PIDX3 15 205#define V_ERR_BAD_DB_PIDX3(x) ((x) << S_ERR_BAD_DB_PIDX3) 206#define F_ERR_BAD_DB_PIDX3 V_ERR_BAD_DB_PIDX3(1U) 207 208#define S_ERR_BAD_DB_PIDX2 14 209#define V_ERR_BAD_DB_PIDX2(x) ((x) << S_ERR_BAD_DB_PIDX2) 210#define F_ERR_BAD_DB_PIDX2 V_ERR_BAD_DB_PIDX2(1U) 211 212#define S_ERR_BAD_DB_PIDX1 13 213#define V_ERR_BAD_DB_PIDX1(x) ((x) << S_ERR_BAD_DB_PIDX1) 214#define F_ERR_BAD_DB_PIDX1 V_ERR_BAD_DB_PIDX1(1U) 215 216#define S_ERR_BAD_DB_PIDX0 12 217#define V_ERR_BAD_DB_PIDX0(x) ((x) << S_ERR_BAD_DB_PIDX0) 218#define F_ERR_BAD_DB_PIDX0 V_ERR_BAD_DB_PIDX0(1U) 219 220#define S_ERR_ING_PCIE_CHAN 11 221#define V_ERR_ING_PCIE_CHAN(x) ((x) << S_ERR_ING_PCIE_CHAN) 222#define F_ERR_ING_PCIE_CHAN V_ERR_ING_PCIE_CHAN(1U) 223 224#define S_ERR_ING_CTXT_PRIO 10 225#define V_ERR_ING_CTXT_PRIO(x) ((x) << S_ERR_ING_CTXT_PRIO) 226#define F_ERR_ING_CTXT_PRIO V_ERR_ING_CTXT_PRIO(1U) 227 228#define S_ERR_EGR_CTXT_PRIO 9 229#define V_ERR_EGR_CTXT_PRIO(x) ((x) << S_ERR_EGR_CTXT_PRIO) 230#define F_ERR_EGR_CTXT_PRIO V_ERR_EGR_CTXT_PRIO(1U) 231 232#define S_DBFIFO_HP_INT 8 233#define V_DBFIFO_HP_INT(x) ((x) << S_DBFIFO_HP_INT) 234#define F_DBFIFO_HP_INT V_DBFIFO_HP_INT(1U) 235 236#define S_DBFIFO_LP_INT 7 237#define V_DBFIFO_LP_INT(x) ((x) << S_DBFIFO_LP_INT) 238#define F_DBFIFO_LP_INT V_DBFIFO_LP_INT(1U) 239 240#define S_INGRESS_SIZE_ERR 5 241#define V_INGRESS_SIZE_ERR(x) ((x) << S_INGRESS_SIZE_ERR) 242#define F_INGRESS_SIZE_ERR V_INGRESS_SIZE_ERR(1U) 243 244#define S_EGRESS_SIZE_ERR 4 245#define V_EGRESS_SIZE_ERR(x) ((x) << S_EGRESS_SIZE_ERR) 246#define F_EGRESS_SIZE_ERR V_EGRESS_SIZE_ERR(1U) 247 248#define A_SGE_INT_ENABLE3 0x1040 249 250#define A_SGE_FL_BUFFER_SIZE0 0x1044 251#define A_SGE_FL_BUFFER_SIZE1 0x1048 252#define A_SGE_FL_BUFFER_SIZE2 0x104c 253#define A_SGE_FL_BUFFER_SIZE3 0x1050 254 255#define A_SGE_FLM_CFG 0x1090 256 257#define S_CREDITCNT 4 258#define M_CREDITCNT 0x3U 259#define V_CREDITCNT(x) ((x) << S_CREDITCNT) 260#define G_CREDITCNT(x) (((x) >> S_CREDITCNT) & M_CREDITCNT) 261 262#define S_CREDITCNTPACKING 2 263#define M_CREDITCNTPACKING 0x3U 264#define V_CREDITCNTPACKING(x) ((x) << S_CREDITCNTPACKING) 265#define G_CREDITCNTPACKING(x) (((x) >> S_CREDITCNTPACKING) & M_CREDITCNTPACKING) 266 267#define A_SGE_CONM_CTRL 0x1094 268 269#define S_T6_EGRTHRESHOLDPACKING 16 270#define M_T6_EGRTHRESHOLDPACKING 0xffU 271#define G_T6_EGRTHRESHOLDPACKING(x) (((x) >> S_T6_EGRTHRESHOLDPACKING) & \ 272 M_T6_EGRTHRESHOLDPACKING) 273 274#define S_EGRTHRESHOLD 8 275#define M_EGRTHRESHOLD 0x3fU 276#define V_EGRTHRESHOLD(x) ((x) << S_EGRTHRESHOLD) 277#define G_EGRTHRESHOLD(x) (((x) >> S_EGRTHRESHOLD) & M_EGRTHRESHOLD) 278 279#define S_EGRTHRESHOLDPACKING 14 280#define M_EGRTHRESHOLDPACKING 0x3fU 281#define V_EGRTHRESHOLDPACKING(x) ((x) << S_EGRTHRESHOLDPACKING) 282#define G_EGRTHRESHOLDPACKING(x) (((x) >> S_EGRTHRESHOLDPACKING) & \ 283 M_EGRTHRESHOLDPACKING) 284 285#define S_INGTHRESHOLD 2 286#define M_INGTHRESHOLD 0x3fU 287#define V_INGTHRESHOLD(x) ((x) << S_INGTHRESHOLD) 288#define G_INGTHRESHOLD(x) (((x) >> S_INGTHRESHOLD) & M_INGTHRESHOLD) 289 290#define A_SGE_INGRESS_RX_THRESHOLD 0x10a0 291 292#define S_THRESHOLD_0 24 293#define M_THRESHOLD_0 0x3fU 294#define V_THRESHOLD_0(x) ((x) << S_THRESHOLD_0) 295#define G_THRESHOLD_0(x) (((x) >> S_THRESHOLD_0) & M_THRESHOLD_0) 296 297#define S_THRESHOLD_1 16 298#define M_THRESHOLD_1 0x3fU 299#define V_THRESHOLD_1(x) ((x) << S_THRESHOLD_1) 300#define G_THRESHOLD_1(x) (((x) >> S_THRESHOLD_1) & M_THRESHOLD_1) 301 302#define S_THRESHOLD_2 8 303#define M_THRESHOLD_2 0x3fU 304#define V_THRESHOLD_2(x) ((x) << S_THRESHOLD_2) 305#define G_THRESHOLD_2(x) (((x) >> S_THRESHOLD_2) & M_THRESHOLD_2) 306 307#define S_THRESHOLD_3 0 308#define M_THRESHOLD_3 0x3fU 309#define V_THRESHOLD_3(x) ((x) << S_THRESHOLD_3) 310#define G_THRESHOLD_3(x) (((x) >> S_THRESHOLD_3) & M_THRESHOLD_3) 311 312#define A_SGE_TIMER_VALUE_0_AND_1 0x10b8 313 314#define S_TIMERVALUE0 16 315#define M_TIMERVALUE0 0xffffU 316#define V_TIMERVALUE0(x) ((x) << S_TIMERVALUE0) 317#define G_TIMERVALUE0(x) (((x) >> S_TIMERVALUE0) & M_TIMERVALUE0) 318 319#define S_TIMERVALUE1 0 320#define M_TIMERVALUE1 0xffffU 321#define V_TIMERVALUE1(x) ((x) << S_TIMERVALUE1) 322#define G_TIMERVALUE1(x) (((x) >> S_TIMERVALUE1) & M_TIMERVALUE1) 323 324#define A_SGE_TIMER_VALUE_2_AND_3 0x10bc 325 326#define S_TIMERVALUE2 16 327#define M_TIMERVALUE2 0xffffU 328#define V_TIMERVALUE2(x) ((x) << S_TIMERVALUE2) 329#define G_TIMERVALUE2(x) (((x) >> S_TIMERVALUE2) & M_TIMERVALUE2) 330 331#define S_TIMERVALUE3 0 332#define M_TIMERVALUE3 0xffffU 333#define V_TIMERVALUE3(x) ((x) << S_TIMERVALUE3) 334#define G_TIMERVALUE3(x) (((x) >> S_TIMERVALUE3) & M_TIMERVALUE3) 335 336#define A_SGE_TIMER_VALUE_4_AND_5 0x10c0 337 338#define S_TIMERVALUE4 16 339#define M_TIMERVALUE4 0xffffU 340#define V_TIMERVALUE4(x) ((x) << S_TIMERVALUE4) 341#define G_TIMERVALUE4(x) (((x) >> S_TIMERVALUE4) & M_TIMERVALUE4) 342 343#define S_TIMERVALUE5 0 344#define M_TIMERVALUE5 0xffffU 345#define V_TIMERVALUE5(x) ((x) << S_TIMERVALUE5) 346#define G_TIMERVALUE5(x) (((x) >> S_TIMERVALUE5) & M_TIMERVALUE5) 347 348#define A_SGE_DEBUG_INDEX 0x10cc 349#define A_SGE_DEBUG_DATA_HIGH 0x10d0 350#define A_SGE_DEBUG_DATA_LOW 0x10d4 351#define A_SGE_STAT_CFG 0x10ec 352 353#define S_STATMODE 2 354#define M_STATMODE 0x3U 355#define V_STATMODE(x) ((x) << S_STATMODE) 356#define G_STATMODE(x) (((x) >> S_STATMODE) & M_STATMODE) 357 358#define S_STATSOURCE_T5 9 359#define M_STATSOURCE_T5 0xfU 360#define V_STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5) 361#define G_STATSOURCE_T5(x) (((x) >> S_STATSOURCE_T5) & M_STATSOURCE_T5) 362 363#define A_SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4 364#define A_SGE_INGRESS_QUEUES_PER_PAGE_VF 0x10f8 365 366#define A_SGE_CONTROL2 0x1124 367 368#define S_IDMAARBROUNDROBIN 19 369#define V_IDMAARBROUNDROBIN(x) ((x) << S_IDMAARBROUNDROBIN) 370#define F_IDMAARBROUNDROBIN V_IDMAARBROUNDROBIN(1U) 371 372#define S_INGPACKBOUNDARY 16 373#define M_INGPACKBOUNDARY 0x7U 374#define V_INGPACKBOUNDARY(x) ((x) << S_INGPACKBOUNDARY) 375#define G_INGPACKBOUNDARY(x) (((x) >> S_INGPACKBOUNDARY) & M_INGPACKBOUNDARY) 376 377#define S_BUSY 31 378#define V_BUSY(x) ((x) << S_BUSY) 379#define F_BUSY V_BUSY(1U) 380 381#define A_SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8 382#define A_SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8 383#define A_SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc 384 385/* registers for module PCIE */ 386#define PCIE_BASE_ADDR 0x3000 387 388#define A_PCIE_MEM_ACCESS_BASE_WIN 0x3068 389 390#define S_PCIEOFST 10 391#define M_PCIEOFST 0x3fffffU 392#define V_PCIEOFST(x) ((x) << S_PCIEOFST) 393#define G_PCIEOFST(x) (((x) >> S_PCIEOFST) & M_PCIEOFST) 394 395#define S_BIR 8 396#define M_BIR 0x3U 397#define V_BIR(x) ((x) << S_BIR) 398#define G_BIR(x) (((x) >> S_BIR) & M_BIR) 399 400#define S_WINDOW 0 401#define M_WINDOW 0xffU 402#define V_WINDOW(x) ((x) << S_WINDOW) 403#define G_WINDOW(x) (((x) >> S_WINDOW) & M_WINDOW) 404 405#define A_PCIE_MEM_ACCESS_OFFSET 0x306c 406 407#define S_PFNUM 0 408#define M_PFNUM 0x7U 409#define V_PFNUM(x) ((x) << S_PFNUM) 410#define G_PFNUM(x) (((x) >> S_PFNUM) & M_PFNUM) 411 412#define A_PCIE_FW 0x30b8 413#define A_PCIE_FW_PF 0x30bc 414 415#define A_PCIE_CFG2 0x3018 416 417#define S_TOTMAXTAG 0 418#define M_TOTMAXTAG 0x3U 419#define V_TOTMAXTAG(x) ((x) << S_TOTMAXTAG) 420 421#define S_T6_TOTMAXTAG 0 422#define M_T6_TOTMAXTAG 0x7U 423#define V_T6_TOTMAXTAG(x) ((x) << S_T6_TOTMAXTAG) 424 425#define A_PCIE_CMD_CFG 0x5980 426 427#define S_MINTAG 0 428#define M_MINTAG 0xffU 429#define V_MINTAG(x) ((x) << S_MINTAG) 430 431#define S_T6_MINTAG 0 432#define M_T6_MINTAG 0xffU 433#define V_T6_MINTAG(x) ((x) << S_T6_MINTAG) 434 435/* registers for module CIM */ 436#define CIM_BASE_ADDR 0x7b00 437 438#define A_CIM_VF_EXT_MAILBOX_CTRL 0x0 439 440#define A_CIM_PF_MAILBOX_DATA 0x240 441#define A_CIM_PF_MAILBOX_CTRL 0x280 442 443#define S_MBMSGVALID 3 444#define V_MBMSGVALID(x) ((x) << S_MBMSGVALID) 445#define F_MBMSGVALID V_MBMSGVALID(1U) 446 447#define S_MBOWNER 0 448#define M_MBOWNER 0x3U 449#define V_MBOWNER(x) ((x) << S_MBOWNER) 450#define G_MBOWNER(x) (((x) >> S_MBOWNER) & M_MBOWNER) 451 452#define A_CIM_PF_MAILBOX_CTRL_SHADOW_COPY 0x290 453#define A_CIM_BOOT_CFG 0x7b00 454 455#define S_UPCRST 0 456#define V_UPCRST(x) ((x) << S_UPCRST) 457#define F_UPCRST V_UPCRST(1U) 458 459#define NUM_CIM_PF_MAILBOX_DATA_INSTANCES 16 460 461/* registers for module TP */ 462#define A_TP_OUT_CONFIG 0x7d04 463 464#define S_CRXPKTENC 3 465#define V_CRXPKTENC(x) ((x) << S_CRXPKTENC) 466#define F_CRXPKTENC V_CRXPKTENC(1U) 467 468#define TP_BASE_ADDR 0x7d00 469#define A_TP_CMM_TCB_BASE 0x7d10 470 471#define A_TP_TIMER_RESOLUTION 0x7d90 472 473#define S_TIMERRESOLUTION 16 474#define M_TIMERRESOLUTION 0xffU 475#define V_TIMERRESOLUTION(x) ((x) << S_TIMERRESOLUTION) 476#define G_TIMERRESOLUTION(x) (((x) >> S_TIMERRESOLUTION) & M_TIMERRESOLUTION) 477 478#define S_DELAYEDACKRESOLUTION 0 479#define M_DELAYEDACKRESOLUTION 0xffU 480#define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION) 481#define G_DELAYEDACKRESOLUTION(x) (((x) >> S_DELAYEDACKRESOLUTION) & \ 482 M_DELAYEDACKRESOLUTION) 483 484#define A_TP_CCTRL_TABLE 0x7ddc 485 486#define A_TP_MTU_TABLE 0x7de4 487 488#define S_MTUINDEX 24 489#define M_MTUINDEX 0xffU 490#define V_MTUINDEX(x) ((x) << S_MTUINDEX) 491#define G_MTUINDEX(x) (((x) >> S_MTUINDEX) & M_MTUINDEX) 492 493#define S_MTUWIDTH 16 494#define M_MTUWIDTH 0xfU 495#define V_MTUWIDTH(x) ((x) << S_MTUWIDTH) 496#define G_MTUWIDTH(x) (((x) >> S_MTUWIDTH) & M_MTUWIDTH) 497 498#define S_MTUVALUE 0 499#define M_MTUVALUE 0x3fffU 500#define V_MTUVALUE(x) ((x) << S_MTUVALUE) 501#define G_MTUVALUE(x) (((x) >> S_MTUVALUE) & M_MTUVALUE) 502 503#define A_TP_RSS_CONFIG_VRT 0x7e00 504 505#define S_KEYMODE 6 506#define M_KEYMODE 0x3U 507#define G_KEYMODE(x) (((x) >> S_KEYMODE) & M_KEYMODE) 508 509#define S_KEYWRADDR 0 510#define V_KEYWRADDR(x) ((x) << S_KEYWRADDR) 511 512#define S_KEYWREN 4 513#define V_KEYWREN(x) ((x) << S_KEYWREN) 514#define F_KEYWREN V_KEYWREN(1U) 515 516#define S_KEYWRADDRX 30 517#define V_KEYWRADDRX(x) ((x) << S_KEYWRADDRX) 518 519#define S_KEYEXTEND 26 520#define V_KEYEXTEND(x) ((x) << S_KEYEXTEND) 521#define F_KEYEXTEND V_KEYEXTEND(1U) 522 523#define S_T6_VFWRADDR 8 524#define V_T6_VFWRADDR(x) ((x) << S_T6_VFWRADDR) 525 526#define A_TP_PIO_ADDR 0x7e40 527#define A_TP_PIO_DATA 0x7e44 528 529#define A_TP_RSS_SECRET_KEY0 0x40 530 531#define A_TP_VLAN_PRI_MAP 0x140 532 533#define S_FRAGMENTATION 9 534#define V_FRAGMENTATION(x) ((x) << S_FRAGMENTATION) 535#define F_FRAGMENTATION V_FRAGMENTATION(1U) 536 537#define S_MPSHITTYPE 8 538#define V_MPSHITTYPE(x) ((x) << S_MPSHITTYPE) 539#define F_MPSHITTYPE V_MPSHITTYPE(1U) 540 541#define S_MACMATCH 7 542#define V_MACMATCH(x) ((x) << S_MACMATCH) 543#define F_MACMATCH V_MACMATCH(1U) 544 545#define S_ETHERTYPE 6 546#define V_ETHERTYPE(x) ((x) << S_ETHERTYPE) 547#define F_ETHERTYPE V_ETHERTYPE(1U) 548 549#define S_PROTOCOL 5 550#define V_PROTOCOL(x) ((x) << S_PROTOCOL) 551#define F_PROTOCOL V_PROTOCOL(1U) 552 553#define S_TOS 4 554#define V_TOS(x) ((x) << S_TOS) 555#define F_TOS V_TOS(1U) 556 557#define S_VLAN 3 558#define V_VLAN(x) ((x) << S_VLAN) 559#define F_VLAN V_VLAN(1U) 560 561#define S_VNIC_ID 2 562#define V_VNIC_ID(x) ((x) << S_VNIC_ID) 563#define F_VNIC_ID V_VNIC_ID(1U) 564 565#define S_PORT 1 566#define V_PORT(x) ((x) << S_PORT) 567#define F_PORT V_PORT(1U) 568 569#define S_FCOE 0 570#define V_FCOE(x) ((x) << S_FCOE) 571#define F_FCOE V_FCOE(1U) 572 573#define A_TP_INGRESS_CONFIG 0x141 574 575#define S_USE_ENC_IDX 13 576#define V_USE_ENC_IDX(x) ((x) << S_USE_ENC_IDX) 577#define F_USE_ENC_IDX V_USE_ENC_IDX(1U) 578 579#define S_VNIC 11 580#define V_VNIC(x) ((x) << S_VNIC) 581#define F_VNIC V_VNIC(1U) 582 583#define S_CSUM_HAS_PSEUDO_HDR 10 584#define V_CSUM_HAS_PSEUDO_HDR(x) ((x) << S_CSUM_HAS_PSEUDO_HDR) 585#define F_CSUM_HAS_PSEUDO_HDR V_CSUM_HAS_PSEUDO_HDR(1U) 586 587#define S_RM_OVLAN 9 588#define V_RM_OVLAN(x) ((x) << S_RM_OVLAN) 589 590/* registers for module MA */ 591#define A_MA_EDRAM0_BAR 0x77c0 592 593#define S_EDRAM0_SIZE 0 594#define M_EDRAM0_SIZE 0xfffU 595#define V_EDRAM0_SIZE(x) ((x) << S_EDRAM0_SIZE) 596#define G_EDRAM0_SIZE(x) (((x) >> S_EDRAM0_SIZE) & M_EDRAM0_SIZE) 597 598#define A_MA_EXT_MEMORY0_BAR 0x77c8 599 600#define S_EXT_MEM0_SIZE 0 601#define M_EXT_MEM0_SIZE 0xfffU 602#define V_EXT_MEM0_SIZE(x) ((x) << S_EXT_MEM0_SIZE) 603#define G_EXT_MEM0_SIZE(x) (((x) >> S_EXT_MEM0_SIZE) & M_EXT_MEM0_SIZE) 604 605/* registers for module MPS */ 606#define MPS_BASE_ADDR 0x9000 607#define T4VF_MPS_BASE_ADDR 0x0100 608 609#define S_REPLICATE 11 610#define V_REPLICATE(x) ((x) << S_REPLICATE) 611#define F_REPLICATE V_REPLICATE(1U) 612 613#define S_PF 8 614#define M_PF 0x7U 615#define V_PF(x) ((x) << S_PF) 616#define G_PF(x) (((x) >> S_PF) & M_PF) 617 618#define S_VF_VALID 7 619#define V_VF_VALID(x) ((x) << S_VF_VALID) 620#define F_VF_VALID V_VF_VALID(1U) 621 622#define S_VF 0 623#define M_VF 0x7fU 624#define V_VF(x) ((x) << S_VF) 625#define G_VF(x) (((x) >> S_VF) & M_VF) 626 627#define A_MPS_STAT_CTL 0x9600 628 629#define S_COUNTPAUSEMCRX 5 630#define V_COUNTPAUSEMCRX(x) ((x) << S_COUNTPAUSEMCRX) 631#define F_COUNTPAUSEMCRX V_COUNTPAUSEMCRX(1U) 632 633#define S_COUNTPAUSESTATRX 4 634#define V_COUNTPAUSESTATRX(x) ((x) << S_COUNTPAUSESTATRX) 635#define F_COUNTPAUSESTATRX V_COUNTPAUSESTATRX(1U) 636 637#define S_COUNTPAUSEMCTX 3 638#define V_COUNTPAUSEMCTX(x) ((x) << S_COUNTPAUSEMCTX) 639#define F_COUNTPAUSEMCTX V_COUNTPAUSEMCTX(1U) 640 641#define S_COUNTPAUSESTATTX 2 642#define V_COUNTPAUSESTATTX(x) ((x) << S_COUNTPAUSESTATTX) 643#define F_COUNTPAUSESTATTX V_COUNTPAUSESTATTX(1U) 644 645#define A_MPS_PORT_STAT_TX_PORT_BYTES_L 0x400 646#define A_MPS_PORT_STAT_TX_PORT_BYTES_H 0x404 647#define A_MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408 648#define A_MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c 649#define A_MPS_PORT_STAT_TX_PORT_BCAST_L 0x410 650#define A_MPS_PORT_STAT_TX_PORT_BCAST_H 0x414 651#define A_MPS_PORT_STAT_TX_PORT_MCAST_L 0x418 652#define A_MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c 653#define A_MPS_PORT_STAT_TX_PORT_UCAST_L 0x420 654#define A_MPS_PORT_STAT_TX_PORT_UCAST_H 0x424 655#define A_MPS_PORT_STAT_TX_PORT_ERROR_L 0x428 656#define A_MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c 657#define A_MPS_PORT_STAT_TX_PORT_64B_L 0x430 658#define A_MPS_PORT_STAT_TX_PORT_64B_H 0x434 659#define A_MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438 660#define A_MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c 661#define A_MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440 662#define A_MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444 663#define A_MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448 664#define A_MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c 665#define A_MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450 666#define A_MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454 667#define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458 668#define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c 669#define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460 670#define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464 671#define A_MPS_PORT_STAT_TX_PORT_DROP_L 0x468 672#define A_MPS_PORT_STAT_TX_PORT_DROP_H 0x46c 673#define A_MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470 674#define A_MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474 675#define A_MPS_PORT_STAT_TX_PORT_PPP0_L 0x478 676#define A_MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c 677#define A_MPS_PORT_STAT_TX_PORT_PPP1_L 0x480 678#define A_MPS_PORT_STAT_TX_PORT_PPP1_H 0x484 679#define A_MPS_PORT_STAT_TX_PORT_PPP2_L 0x488 680#define A_MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c 681#define A_MPS_PORT_STAT_TX_PORT_PPP3_L 0x490 682#define A_MPS_PORT_STAT_TX_PORT_PPP3_H 0x494 683#define A_MPS_PORT_STAT_TX_PORT_PPP4_L 0x498 684#define A_MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c 685#define A_MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0 686#define A_MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4 687#define A_MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8 688#define A_MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac 689#define A_MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0 690#define A_MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4 691#define A_MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0 692#define A_MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4 693#define A_MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8 694#define A_MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc 695#define A_MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0 696#define A_MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4 697#define A_MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8 698#define A_MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc 699#define A_MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0 700#define A_MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4 701#define A_MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8 702#define A_MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec 703#define A_MPS_PORT_STAT_LB_PORT_64B_L 0x4f0 704#define A_MPS_PORT_STAT_LB_PORT_64B_H 0x4f4 705#define A_MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8 706#define A_MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc 707#define A_MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500 708#define A_MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504 709#define A_MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508 710#define A_MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c 711#define A_MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510 712#define A_MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514 713#define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518 714#define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c 715#define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520 716#define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524 717#define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528 718#define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x528 719#define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H 0x52c 720#define A_MPS_PORT_STAT_RX_PORT_BYTES_L 0x540 721#define A_MPS_PORT_STAT_RX_PORT_BYTES_H 0x544 722#define A_MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548 723#define A_MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c 724#define A_MPS_PORT_STAT_RX_PORT_BCAST_L 0x550 725#define A_MPS_PORT_STAT_RX_PORT_BCAST_H 0x554 726#define A_MPS_PORT_STAT_RX_PORT_MCAST_L 0x558 727#define A_MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c 728#define A_MPS_PORT_STAT_RX_PORT_UCAST_L 0x560 729#define A_MPS_PORT_STAT_RX_PORT_UCAST_H 0x564 730#define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568 731#define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c 732#define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570 733#define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574 734#define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578 735#define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c 736#define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580 737#define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584 738#define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588 739#define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c 740#define A_MPS_PORT_STAT_RX_PORT_64B_L 0x590 741#define A_MPS_PORT_STAT_RX_PORT_64B_H 0x594 742#define A_MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598 743#define A_MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c 744#define A_MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0 745#define A_MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4 746#define A_MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8 747#define A_MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac 748#define A_MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0 749#define A_MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4 750#define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8 751#define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc 752#define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0 753#define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4 754#define A_MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8 755#define A_MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc 756#define A_MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0 757#define A_MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4 758#define A_MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8 759#define A_MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc 760#define A_MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0 761#define A_MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4 762#define A_MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8 763#define A_MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec 764#define A_MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0 765#define A_MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4 766#define A_MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8 767#define A_MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc 768#define A_MPS_PORT_STAT_RX_PORT_PPP6_L 0x600 769#define A_MPS_PORT_STAT_RX_PORT_PPP6_H 0x604 770#define A_MPS_PORT_STAT_RX_PORT_PPP7_L 0x608 771#define A_MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c 772#define A_MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610 773#define A_MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614 774#define A_MPS_CMN_CTL 0x9000 775 776#define S_NUMPORTS 0 777#define M_NUMPORTS 0x3U 778#define V_NUMPORTS(x) ((x) << S_NUMPORTS) 779#define G_NUMPORTS(x) (((x) >> S_NUMPORTS) & M_NUMPORTS) 780 781#define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640 782#define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644 783#define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648 784#define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c 785#define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650 786#define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654 787#define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658 788#define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c 789#define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660 790#define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664 791#define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668 792#define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c 793#define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670 794#define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674 795#define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678 796#define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c 797#define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680 798#define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684 799#define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688 800#define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c 801#define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690 802#define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694 803#define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698 804#define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c 805#define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0 806#define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4 807#define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8 808#define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac 809#define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0 810#define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4 811#define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8 812#define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc 813 814#define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L 0x80 815#define A_MPS_VF_STAT_TX_VF_BCAST_FRAMES_L 0x88 816#define A_MPS_VF_STAT_TX_VF_MCAST_BYTES_L 0x90 817#define A_MPS_VF_STAT_TX_VF_MCAST_FRAMES_L 0x98 818#define A_MPS_VF_STAT_TX_VF_UCAST_BYTES_L 0xa0 819#define A_MPS_VF_STAT_TX_VF_UCAST_FRAMES_L 0xa8 820#define A_MPS_VF_STAT_TX_VF_DROP_FRAMES_L 0xb0 821#define A_MPS_VF_STAT_RX_VF_BCAST_FRAMES_L 0xd0 822#define A_MPS_VF_STAT_RX_VF_MCAST_FRAMES_L 0xe0 823#define A_MPS_VF_STAT_RX_VF_UCAST_FRAMES_L 0xf0 824#define A_MPS_VF_STAT_RX_VF_ERR_FRAMES_L 0xf8 825 826#define A_MPS_PORT0_RX_IVLAN 0x3011c 827 828#define S_IVLAN_ETYPE 0 829#define M_IVLAN_ETYPE 0xffffU 830#define V_IVLAN_ETYPE(x) ((x) << S_IVLAN_ETYPE) 831 832#define MPS_PORT_RX_IVLAN_STRIDE 0x4000 833#define MPS_PORT_RX_IVLAN(idx) \ 834 (A_MPS_PORT0_RX_IVLAN + (idx) * MPS_PORT_RX_IVLAN_STRIDE) 835 836#define A_MPS_PORT0_RX_OVLAN0 0x30120 837 838#define S_OVLAN_MASK 16 839#define M_OVLAN_MASK 0xffffU 840#define V_OVLAN_MASK(x) ((x) << S_OVLAN_MASK) 841 842#define S_OVLAN_ETYPE 0 843#define M_OVLAN_ETYPE 0xffffU 844#define V_OVLAN_ETYPE(x) ((x) << S_OVLAN_ETYPE) 845 846#define MPS_PORT_RX_OVLAN_STRIDE 0x4000 847#define MPS_PORT_RX_OVLAN_BASE(idx) \ 848(A_MPS_PORT0_RX_OVLAN0 + (idx) * MPS_PORT_RX_OVLAN_STRIDE) 849#define MPS_PORT_RX_OVLAN_REG(idx, reg) (MPS_PORT_RX_OVLAN_BASE(idx) + (reg)) 850 851#define A_RX_OVLAN0 0x0 852#define A_RX_OVLAN1 0x4 853#define A_RX_OVLAN2 0x8 854 855#define A_MPS_PORT0_RX_CTL 0x30100 856 857#define S_OVLAN_EN0 0 858#define V_OVLAN_EN0(x) ((x) << S_OVLAN_EN0) 859#define F_OVLAN_EN0 V_OVLAN_EN0(1) 860 861#define S_OVLAN_EN1 1 862#define V_OVLAN_EN1(x) ((x) << S_OVLAN_EN1) 863#define F_OVLAN_EN1 V_OVLAN_EN1(1) 864 865#define S_OVLAN_EN2 2 866#define V_OVLAN_EN2(x) ((x) << S_OVLAN_EN2) 867#define F_OVLAN_EN2 V_OVLAN_EN2(1) 868 869#define S_IVLAN_EN 4 870#define V_IVLAN_EN(x) ((x) << S_IVLAN_EN) 871#define F_IVLAN_EN V_IVLAN_EN(1) 872 873#define MPS_PORT_RX_CTL_STRIDE 0x4000 874#define MPS_PORT_RX_CTL(idx) \ 875 (A_MPS_PORT0_RX_CTL + (idx) * MPS_PORT_RX_CTL_STRIDE) 876 877/* registers for module ULP_RX */ 878#define ULP_RX_BASE_ADDR 0x19150 879 880#define S_HPZ0 0 881#define M_HPZ0 0xfU 882#define V_HPZ0(x) ((x) << S_HPZ0) 883#define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0) 884 885#define A_ULP_RX_TDDP_PSZ 0x19178 886 887/* registers for module SF */ 888#define SF_BASE_ADDR 0x193f8 889 890#define A_SF_DATA 0x193f8 891#define A_SF_OP 0x193fc 892 893#define S_SF_LOCK 4 894#define V_SF_LOCK(x) ((x) << S_SF_LOCK) 895#define F_SF_LOCK V_SF_LOCK(1U) 896 897#define S_CONT 3 898#define V_CONT(x) ((x) << S_CONT) 899#define F_CONT V_CONT(1U) 900 901#define S_BYTECNT 1 902#define M_BYTECNT 0x3U 903#define V_BYTECNT(x) ((x) << S_BYTECNT) 904#define G_BYTECNT(x) (((x) >> S_BYTECNT) & M_BYTECNT) 905 906#define S_OP 0 907#define V_OP(x) ((x) << S_OP) 908#define F_OP V_OP(1U) 909 910/* registers for module PL */ 911#define PL_BASE_ADDR 0x19400 912 913#define S_SOURCEPF 8 914#define M_SOURCEPF 0x7U 915#define V_SOURCEPF(x) ((x) << S_SOURCEPF) 916#define G_SOURCEPF(x) (((x) >> S_SOURCEPF) & M_SOURCEPF) 917 918#define S_T6_SOURCEPF 9 919#define M_T6_SOURCEPF 0x7U 920#define V_T6_SOURCEPF(x) ((x) << S_T6_SOURCEPF) 921#define G_T6_SOURCEPF(x) (((x) >> S_T6_SOURCEPF) & M_T6_SOURCEPF) 922 923#define A_PL_PF_INT_ENABLE 0x3c4 924 925#define S_PFSW 3 926#define V_PFSW(x) ((x) << S_PFSW) 927#define F_PFSW V_PFSW(1U) 928 929#define S_PFCIM 1 930#define V_PFCIM(x) ((x) << S_PFCIM) 931#define F_PFCIM V_PFCIM(1U) 932 933#define A_PL_WHOAMI 0x19400 934#define A_PL_VF_WHOAMI 0x0 935 936#define A_PL_RST 0x19428 937 938#define A_PL_INT_MAP0 0x19414 939 940#define S_PIORST 1 941#define V_PIORST(x) ((x) << S_PIORST) 942#define F_PIORST V_PIORST(1U) 943 944#define S_PIORSTMODE 0 945#define V_PIORSTMODE(x) ((x) << S_PIORSTMODE) 946#define F_PIORSTMODE V_PIORSTMODE(1U) 947 948#define A_PL_REV 0x1943c 949#define A_PL_VF_REV 0x4 950 951#define S_REV 0 952#define M_REV 0xfU 953#define V_REV(x) ((x) << S_REV) 954#define G_REV(x) (((x) >> S_REV) & M_REV) 955 956/* registers for module LE */ 957#define A_LE_DB_CONFIG 0x19c04 958 959#define S_HASHEN 20 960#define V_HASHEN(x) ((x) << S_HASHEN) 961#define F_HASHEN V_HASHEN(1U) 962 963#define A_LE_DB_RSP_CODE_0 0x19c74 964 965#define S_TCAM_ACTV_HIT 0 966#define M_TCAM_ACTV_HIT 0x1fU 967#define G_TCAM_ACTV_HIT(x) (((x) >> S_TCAM_ACTV_HIT) & M_TCAM_ACTV_HIT) 968 969#define A_LE_DB_RSP_CODE_1 0x19c78 970 971#define S_HASH_ACTV_HIT 25 972#define M_HASH_ACTV_HIT 0x1fU 973#define G_HASH_ACTV_HIT(x) (((x) >> S_HASH_ACTV_HIT) & M_HASH_ACTV_HIT) 974 975#define A_LE_DB_TID_HASHBASE 0x19df8 976 977#define LE_3_DB_HASH_MASK_GEN_IPV4_T6_A 0x19eac 978#define LE_4_DB_HASH_MASK_GEN_IPV4_T6_A 0x19eb0 979