/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2001-2020 Intel Corporation
 */

/* 82562G 10/100 Network Connection
 * 82562G-2 10/100 Network Connection
 * 82562GT 10/100 Network Connection
 * 82562GT-2 10/100 Network Connection
 * 82562V 10/100 Network Connection
 * 82562V-2 10/100 Network Connection
 * 82566DC-2 Gigabit Network Connection
 * 82566DC Gigabit Network Connection
 * 82566DM-2 Gigabit Network Connection
 * 82566DM Gigabit Network Connection
 * 82566MC Gigabit Network Connection
 * 82566MM Gigabit Network Connection
 * 82567LM Gigabit Network Connection
 * 82567LF Gigabit Network Connection
 * 82567V Gigabit Network Connection
 * 82567LM-2 Gigabit Network Connection
 * 82567LF-2 Gigabit Network Connection
 * 82567V-2 Gigabit Network Connection
 * 82567LF-3 Gigabit Network Connection
 * 82567LM-3 Gigabit Network Connection
 * 82567LM-4 Gigabit Network Connection
 * 82577LM Gigabit Network Connection
 * 82577LC Gigabit Network Connection
 * 82578DM Gigabit Network Connection
 * 82578DC Gigabit Network Connection
 * 82579LM Gigabit Network Connection
 * 82579V Gigabit Network Connection
 * Ethernet Connection I217-LM
 * Ethernet Connection I217-V
 * Ethernet Connection I218-V
 * Ethernet Connection I218-LM
 * Ethernet Connection (2) I218-LM
 * Ethernet Connection (2) I218-V
 * Ethernet Connection (3) I218-LM
 * Ethernet Connection (3) I218-V
 */

#include "e1000_api.h"

STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
STATIC s32  e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
STATIC s32  e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
STATIC int  e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
STATIC int  e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
                                              u8 *mc_addr_list,
                                              u32 mc_addr_count);
STATIC s32  e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
STATIC s32  e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
STATIC s32  e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
STATIC s32  e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
                                            bool active);
STATIC s32  e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
                                            bool active);
STATIC s32  e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
                                   u16 words, u16 *data);
STATIC s32  e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
                               u16 *data);
STATIC s32  e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
                                    u16 words, u16 *data);
STATIC s32  e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
STATIC s32  e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
STATIC s32  e1000_update_nvm_checksum_spt(struct e1000_hw *hw);
STATIC s32  e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
                                            u16 *data);
STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
STATIC s32  e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
STATIC s32  e1000_reset_hw_ich8lan(struct e1000_hw *hw);
STATIC s32  e1000_init_hw_ich8lan(struct e1000_hw *hw);
STATIC s32  e1000_setup_link_ich8lan(struct e1000_hw *hw);
STATIC s32  e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
STATIC s32  e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
STATIC s32  e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
                                           u16 *speed, u16 *duplex);
STATIC s32  e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
STATIC s32  e1000_led_on_ich8lan(struct e1000_hw *hw);
STATIC s32  e1000_led_off_ich8lan(struct e1000_hw *hw);
STATIC s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
STATIC s32  e1000_setup_led_pchlan(struct e1000_hw *hw);
STATIC s32  e1000_cleanup_led_pchlan(struct e1000_hw *hw);
STATIC s32  e1000_led_on_pchlan(struct e1000_hw *hw);
STATIC s32  e1000_led_off_pchlan(struct e1000_hw *hw);
STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
STATIC s32  e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
STATIC s32  e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
STATIC s32  e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
                                          u32 offset, u8 *data);
STATIC s32  e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
                                          u8 size, u16 *data);
STATIC s32  e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
                                            u32 *data);
STATIC s32  e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
                                           u32 offset, u32 *data);
STATIC s32  e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
                                             u32 offset, u32 data);
STATIC s32  e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
                                                  u32 offset, u32 dword);
STATIC s32  e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
                                          u32 offset, u16 *data);
STATIC s32  e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
                                                 u32 offset, u8 byte);
STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);

/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
/* Offset 04h HSFSTS */
union ich8_hws_flash_status {
        struct ich8_hsfsts {
                u16 flcdone:1; /* bit 0 Flash Cycle Done */
                u16 flcerr:1; /* bit 1 Flash Cycle Error */
                u16 dael:1; /* bit 2 Direct Access error Log */
                u16 berasesz:2; /* bit 4:3 Sector Erase Size */
                u16 flcinprog:1; /* bit 5 flash cycle in Progress */
                u16 reserved1:2; /* bit 13:6 Reserved */
                u16 reserved2:6; /* bit 13:6 Reserved */
                u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
                u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
        } hsf_status;
        u16 regval;
};

/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
/* Offset 06h FLCTL */
union ich8_hws_flash_ctrl {
        struct ich8_hsflctl {
                u16 flcgo:1;   /* 0 Flash Cycle Go */
                u16 flcycle:2;   /* 2:1 Flash Cycle */
                u16 reserved:5;   /* 7:3 Reserved  */
                u16 fldbcount:2;   /* 9:8 Flash Data Byte Count */
                u16 flockdn:6;   /* 15:10 Reserved */
        } hsf_ctrl;
        u16 regval;
};

/* ICH Flash Region Access Permissions */
union ich8_hws_flash_regacc {
        struct ich8_flracc {
                u32 grra:8; /* 0:7 GbE region Read Access */
                u32 grwa:8; /* 8:15 GbE region Write Access */
                u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
                u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
        } hsf_flregacc;
        u16 regval;
};

/**
 *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 *  @hw: pointer to the HW structure
 *
 *  Test access to the PHY registers by reading the PHY ID registers.  If
 *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 *  otherwise assume the read PHY ID is correct if it is valid.
 *
 *  Assumes the sw/fw/hw semaphore is already acquired.
 **/
STATIC bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
{
        u16 phy_reg = 0;
        u32 phy_id = 0;
        s32 ret_val = 0;
        u16 retry_count;
        u32 mac_reg = 0;

        for (retry_count = 0; retry_count < 2; retry_count++) {
                ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
                if (ret_val || (phy_reg == 0xFFFF))
                        continue;
                phy_id = (u32)(phy_reg << 16);

                ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
                if (ret_val || (phy_reg == 0xFFFF)) {
                        phy_id = 0;
                        continue;
                }
                phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
                break;
        }

        if (hw->phy.id) {
                if  (hw->phy.id == phy_id)
                        goto out;
        } else if (phy_id) {
                hw->phy.id = phy_id;
                hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
                goto out;
        }

        /* In case the PHY needs to be in mdio slow mode,
         * set slow mode and try to get the PHY id again.
         */
        if (hw->mac.type < e1000_pch_lpt) {
                hw->phy.ops.release(hw);
                ret_val = e1000_set_mdio_slow_mode_hv(hw);
                if (!ret_val)
                        ret_val = e1000_get_phy_id(hw);
                hw->phy.ops.acquire(hw);
        }

        if (ret_val)
                return false;
out:
        if (hw->mac.type >= e1000_pch_lpt) {
                /* Only unforce SMBus if ME is not active */
                if (!(E1000_READ_REG(hw, E1000_FWSM) &
                    E1000_ICH_FWSM_FW_VALID)) {
                        /* Unforce SMBus mode in PHY */
                        hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
                        phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
                        hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);

                        /* Unforce SMBus mode in MAC */
                        mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
                        mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
                        E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
                }
        }

        return true;
}

/**
 *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
 *  @hw: pointer to the HW structure
 *
 *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
 *  used to reset the PHY to a quiescent state when necessary.
 **/
STATIC void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
{
        u32 mac_reg;

        DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");

        /* Set Phy Config Counter to 50msec */
        mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
        mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
        mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
        E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);

        /* Toggle LANPHYPC Value bit */
        mac_reg = E1000_READ_REG(hw, E1000_CTRL);
        mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
        mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
        E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
        E1000_WRITE_FLUSH(hw);
        msec_delay(1);
        mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
        E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
        E1000_WRITE_FLUSH(hw);

        if (hw->mac.type < e1000_pch_lpt) {
                msec_delay(50);
        } else {
                u16 count = 20;

                do {
                        msec_delay(5);
                } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
                           E1000_CTRL_EXT_LPCD) && count--);

                msec_delay(30);
        }
}

/**
 *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 *  @hw: pointer to the HW structure
 *
 *  Workarounds/flow necessary for PHY initialization during driver load
 *  and resume paths.
 **/
STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
{
        u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
        s32 ret_val;

        DEBUGFUNC("e1000_init_phy_workarounds_pchlan");

        /* Gate automatic PHY configuration by hardware on managed and
         * non-managed 82579 and newer adapters.
         */
        e1000_gate_hw_phy_config_ich8lan(hw, true);

        /* It is not possible to be certain of the current state of ULP
         * so forcibly disable it.
         */
        hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;

        ret_val = hw->phy.ops.acquire(hw);
        if (ret_val) {
                DEBUGOUT("Failed to initialize PHY flow\n");
                goto out;
        }

        /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
         * inaccessible and resetting the PHY is not blocked, toggle the
         * LANPHYPC Value bit to force the interconnect to PCIe mode.
         */
        switch (hw->mac.type) {
        case e1000_pch_lpt:
        case e1000_pch_spt:
        case e1000_pch_cnp:
        case e1000_pch_adp:
                if (e1000_phy_is_accessible_pchlan(hw))
                        break;

                /* Before toggling LANPHYPC, see if PHY is accessible by
                 * forcing MAC to SMBus mode first.
                 */
                mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
                mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
                E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);

                /* Wait 50 milliseconds for MAC to finish any retries
                 * that it might be trying to perform from previous
                 * attempts to acknowledge any phy read requests.
                 */
                 msec_delay(50);

                /* fall-through */
        case e1000_pch2lan:
                if (e1000_phy_is_accessible_pchlan(hw))
                        break;

                /* fall-through */
        case e1000_pchlan:
                if ((hw->mac.type == e1000_pchlan) &&
                    (fwsm & E1000_ICH_FWSM_FW_VALID))
                        break;

                if (hw->phy.ops.check_reset_block(hw)) {
                        DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
                        ret_val = -E1000_ERR_PHY;
                        break;
                }

                /* Toggle LANPHYPC Value bit */
                e1000_toggle_lanphypc_pch_lpt(hw);
                if (hw->mac.type >= e1000_pch_lpt) {
                        if (e1000_phy_is_accessible_pchlan(hw))
                                break;

                        /* Toggling LANPHYPC brings the PHY out of SMBus mode
                         * so ensure that the MAC is also out of SMBus mode
                         */
                        mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
                        mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
                        E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);

                        if (e1000_phy_is_accessible_pchlan(hw))
                                break;

                        ret_val = -E1000_ERR_PHY;
                }
                break;
        default:
                break;
        }

        hw->phy.ops.release(hw);
        if (!ret_val) {

                /* Check to see if able to reset PHY.  Print error if not */
                if (hw->phy.ops.check_reset_block(hw)) {
                        ERROR_REPORT("Reset blocked by ME\n");
                        goto out;
                }

                /* Reset the PHY before any access to it.  Doing so, ensures
                 * that the PHY is in a known good state before we read/write
                 * PHY registers.  The generic reset is sufficient here,
                 * because we haven't determined the PHY type yet.
                 */
                ret_val = e1000_phy_hw_reset_generic(hw);
                if (ret_val)
                        goto out;

                /* On a successful reset, possibly need to wait for the PHY
                 * to quiesce to an accessible state before returning control
                 * to the calling function.  If the PHY does not quiesce, then
                 * return E1000E_BLK_PHY_RESET, as this is the condition that
                 *  the PHY is in.
                 */
                ret_val = hw->phy.ops.check_reset_block(hw);
                if (ret_val)
                        ERROR_REPORT("ME blocked access to PHY after reset\n");
        }

out:
        /* Ungate automatic PHY configuration on non-managed 82579 */
        if ((hw->mac.type == e1000_pch2lan) &&
            !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
                msec_delay(10);
                e1000_gate_hw_phy_config_ich8lan(hw, false);
        }

        return ret_val;
}

/**
 *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 *  @hw: pointer to the HW structure
 *
 *  Initialize family-specific PHY parameters and function pointers.
 **/
STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
{
        struct e1000_phy_info *phy = &hw->phy;
        s32 ret_val;

        DEBUGFUNC("e1000_init_phy_params_pchlan");

        phy->addr               = 1;
        phy->reset_delay_us     = 100;

        phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
        phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
        phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
        phy->ops.set_page       = e1000_set_page_igp;
        phy->ops.read_reg       = e1000_read_phy_reg_hv;
        phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
        phy->ops.read_reg_page  = e1000_read_phy_reg_page_hv;
        phy->ops.release        = e1000_release_swflag_ich8lan;
        phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
        phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
        phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
        phy->ops.write_reg      = e1000_write_phy_reg_hv;
        phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
        phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
        phy->ops.power_up       = e1000_power_up_phy_copper;
        phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
        phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;

        phy->id = e1000_phy_unknown;

        ret_val = e1000_init_phy_workarounds_pchlan(hw);
        if (ret_val)
                return ret_val;

        if (phy->id == e1000_phy_unknown)
                switch (hw->mac.type) {
                default:
                        ret_val = e1000_get_phy_id(hw);
                        if (ret_val)
                                return ret_val;
                        if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
                                break;
                        /* fall-through */
                case e1000_pch2lan:
                case e1000_pch_lpt:
                case e1000_pch_spt:
                case e1000_pch_cnp:
                case e1000_pch_adp:
                        /* In case the PHY needs to be in mdio slow mode,
                         * set slow mode and try to get the PHY id again.
                         */
                        ret_val = e1000_set_mdio_slow_mode_hv(hw);
                        if (ret_val)
                                return ret_val;
                        ret_val = e1000_get_phy_id(hw);
                        if (ret_val)
                                return ret_val;
                        break;
                }
        phy->type = e1000_get_phy_type_from_id(phy->id);

        switch (phy->type) {
        case e1000_phy_82577:
        case e1000_phy_82579:
        case e1000_phy_i217:
                phy->ops.check_polarity = e1000_check_polarity_82577;
                phy->ops.force_speed_duplex =
                        e1000_phy_force_speed_duplex_82577;
                phy->ops.get_cable_length = e1000_get_cable_length_82577;
                phy->ops.get_info = e1000_get_phy_info_82577;
                phy->ops.commit = e1000_phy_sw_reset_generic;
                break;
        case e1000_phy_82578:
                phy->ops.check_polarity = e1000_check_polarity_m88;
                phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
                phy->ops.get_cable_length = e1000_get_cable_length_m88;
                phy->ops.get_info = e1000_get_phy_info_m88;
                break;
        default:
                ret_val = -E1000_ERR_PHY;
                break;
        }

        return ret_val;
}

/**
 *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 *  @hw: pointer to the HW structure
 *
 *  Initialize family-specific PHY parameters and function pointers.
 **/
STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
{
        struct e1000_phy_info *phy = &hw->phy;
        s32 ret_val;
        u16 i = 0;

        DEBUGFUNC("e1000_init_phy_params_ich8lan");

        phy->addr               = 1;
        phy->reset_delay_us     = 100;

        phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
        phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
        phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
        phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
        phy->ops.read_reg       = e1000_read_phy_reg_igp;
        phy->ops.release        = e1000_release_swflag_ich8lan;
        phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
        phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
        phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
        phy->ops.write_reg      = e1000_write_phy_reg_igp;
        phy->ops.power_up       = e1000_power_up_phy_copper;
        phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;

        /* We may need to do this twice - once for IGP and if that fails,
         * we'll set BM func pointers and try again
         */
        ret_val = e1000_determine_phy_address(hw);
        if (ret_val) {
                phy->ops.write_reg = e1000_write_phy_reg_bm;
                phy->ops.read_reg  = e1000_read_phy_reg_bm;
                ret_val = e1000_determine_phy_address(hw);
                if (ret_val) {
                        DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
                        return ret_val;
                }
        }

        phy->id = 0;
        while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
               (i++ < 100)) {
                msec_delay(1);
                ret_val = e1000_get_phy_id(hw);
                if (ret_val)
                        return ret_val;
        }

        /* Verify phy id */
        switch (phy->id) {
        case IGP03E1000_E_PHY_ID:
                phy->type = e1000_phy_igp_3;
                phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
                phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
                phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
                phy->ops.get_info = e1000_get_phy_info_igp;
                phy->ops.check_polarity = e1000_check_polarity_igp;
                phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
                break;
        case IFE_E_PHY_ID:
        case IFE_PLUS_E_PHY_ID:
        case IFE_C_E_PHY_ID:
                phy->type = e1000_phy_ife;
                phy->autoneg_mask = E1000_ALL_NOT_GIG;
                phy->ops.get_info = e1000_get_phy_info_ife;
                phy->ops.check_polarity = e1000_check_polarity_ife;
                phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
                break;
        case BME1000_E_PHY_ID:
                phy->type = e1000_phy_bm;
                phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
                phy->ops.read_reg = e1000_read_phy_reg_bm;
                phy->ops.write_reg = e1000_write_phy_reg_bm;
                phy->ops.commit = e1000_phy_sw_reset_generic;
                phy->ops.get_info = e1000_get_phy_info_m88;
                phy->ops.check_polarity = e1000_check_polarity_m88;
                phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
                break;
        default:
                return -E1000_ERR_PHY;
                break;
        }

        return E1000_SUCCESS;
}

/**
 *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 *  @hw: pointer to the HW structure
 *
 *  Initialize family-specific NVM parameters and function
 *  pointers.
 **/
STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
{
        struct e1000_nvm_info *nvm = &hw->nvm;
        struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
        u32 gfpreg, sector_base_addr, sector_end_addr;
        u16 i;
        u32 nvm_size;

        DEBUGFUNC("e1000_init_nvm_params_ich8lan");

        nvm->type = e1000_nvm_flash_sw;

        if (hw->mac.type >= e1000_pch_spt) {
                /* in SPT, gfpreg doesn't exist. NVM size is taken from the
                 * STRAP register. This is because in SPT the GbE Flash region
                 * is no longer accessed through the flash registers. Instead,
                 * the mechanism has changed, and the Flash region access
                 * registers are now implemented in GbE memory space.
                 */
                nvm->flash_base_addr = 0;
                nvm_size =
                    (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1)
                    * NVM_SIZE_MULTIPLIER;
                nvm->flash_bank_size = nvm_size / 2;
                /* Adjust to word count */
                nvm->flash_bank_size /= sizeof(u16);
                /* Set the base address for flash register access */
                hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
        } else {
                /* Can't read flash registers if register set isn't mapped. */
                if (!hw->flash_address) {
                        DEBUGOUT("ERROR: Flash registers not mapped\n");
                        return -E1000_ERR_CONFIG;
                }

                gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);

                /* sector_X_addr is a "sector"-aligned address (4096 bytes)
                 * Add 1 to sector_end_addr since this sector is included in
                 * the overall size.
                 */
                sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
                sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;

                /* flash_base_addr is byte-aligned */
                nvm->flash_base_addr = sector_base_addr
                                       << FLASH_SECTOR_ADDR_SHIFT;

                /* find total size of the NVM, then cut in half since the total
                 * size represents two separate NVM banks.
                 */
                nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
                                        << FLASH_SECTOR_ADDR_SHIFT);
                nvm->flash_bank_size /= 2;
                /* Adjust to word count */
                nvm->flash_bank_size /= sizeof(u16);
        }

        nvm->word_size = E1000_SHADOW_RAM_WORDS;

        /* Clear shadow ram */
        for (i = 0; i < nvm->word_size; i++) {
                dev_spec->shadow_ram[i].modified = false;
                dev_spec->shadow_ram[i].value    = 0xFFFF;
        }

        E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
        E1000_MUTEX_INIT(&dev_spec->swflag_mutex);

        /* Function Pointers */
        nvm->ops.acquire        = e1000_acquire_nvm_ich8lan;
        nvm->ops.release        = e1000_release_nvm_ich8lan;
        if (hw->mac.type >= e1000_pch_spt) {
                nvm->ops.read   = e1000_read_nvm_spt;
                nvm->ops.update = e1000_update_nvm_checksum_spt;
        } else {
                nvm->ops.read   = e1000_read_nvm_ich8lan;
                nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
        }
        nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
        nvm->ops.validate       = e1000_validate_nvm_checksum_ich8lan;
        nvm->ops.write          = e1000_write_nvm_ich8lan;

        return E1000_SUCCESS;
}

/**
 *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 *  @hw: pointer to the HW structure
 *
 *  Initialize family-specific MAC parameters and function
 *  pointers.
 **/
STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
{
        struct e1000_mac_info *mac = &hw->mac;
        u16 pci_cfg;

        DEBUGFUNC("e1000_init_mac_params_ich8lan");

        /* Set media type function pointer */
        hw->phy.media_type = e1000_media_type_copper;

        /* Set mta register count */
        mac->mta_reg_count = 32;
        /* Set rar entry count */
        mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
        if (mac->type == e1000_ich8lan)
                mac->rar_entry_count--;
        /* Set if part includes ASF firmware */
        mac->asf_firmware_present = true;
        /* FWSM register */
        mac->has_fwsm = true;
        /* ARC subsystem not supported */
        mac->arc_subsystem_valid = false;
        /* Adaptive IFS supported */
        mac->adaptive_ifs = true;

        /* Function pointers */

        /* bus type/speed/width */
        mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
        /* function id */
        mac->ops.set_lan_id = e1000_set_lan_id_single_port;
        /* reset */
        mac->ops.reset_hw = e1000_reset_hw_ich8lan;
        /* hw initialization */
        mac->ops.init_hw = e1000_init_hw_ich8lan;
        /* link setup */
        mac->ops.setup_link = e1000_setup_link_ich8lan;
        /* physical interface setup */
        mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
        /* check for link */
        mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
        /* link info */
        mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
        /* multicast address update */
        mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
        /* clear hardware counters */
        mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;

        /* LED and other operations */
        switch (mac->type) {
        case e1000_ich8lan:
        case e1000_ich9lan:
        case e1000_ich10lan:
                /* check management mode */
                mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
                /* ID LED init */
                mac->ops.id_led_init = e1000_id_led_init_generic;
                /* blink LED */
                mac->ops.blink_led = e1000_blink_led_generic;
                /* setup LED */
                mac->ops.setup_led = e1000_setup_led_generic;
                /* cleanup LED */
                mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
                /* turn on/off LED */
                mac->ops.led_on = e1000_led_on_ich8lan;
                mac->ops.led_off = e1000_led_off_ich8lan;
                break;
        case e1000_pch2lan:
                mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
                mac->ops.rar_set = e1000_rar_set_pch2lan;
                /* fall-through */
        case e1000_pch_lpt:
        case e1000_pch_spt:
        case e1000_pch_cnp:
        case e1000_pch_adp:
                /* multicast address update for pch2 */
                mac->ops.update_mc_addr_list =
                        e1000_update_mc_addr_list_pch2lan;
                /* fall-through */
        case e1000_pchlan:
                /* save PCH revision_id */
                e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);
                /* SPT uses full byte for revision ID,
                 * as opposed to previous generations
                 */
                if (hw->mac.type >= e1000_pch_spt)
                        hw->revision_id = (u8)(pci_cfg &= 0x00FF);
                else
                        hw->revision_id = (u8)(pci_cfg &= 0x000F);
                /* check management mode */
                mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
                /* ID LED init */
                mac->ops.id_led_init = e1000_id_led_init_pchlan;
                /* setup LED */
                mac->ops.setup_led = e1000_setup_led_pchlan;
                /* cleanup LED */
                mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
                /* turn on/off LED */
                mac->ops.led_on = e1000_led_on_pchlan;
                mac->ops.led_off = e1000_led_off_pchlan;
                break;
        default:
                break;
        }

        if (mac->type >= e1000_pch_lpt) {
                mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
                mac->ops.rar_set = e1000_rar_set_pch_lpt;
                mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
        }

        /* Enable PCS Lock-loss workaround for ICH8 */
        if (mac->type == e1000_ich8lan)
                e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, true);

        return E1000_SUCCESS;
}

/**
 *  __e1000_access_emi_reg_locked - Read/write EMI register
 *  @hw: pointer to the HW structure
 *  @address: EMI address to program
 *  @data: pointer to value to read/write from/to the EMI address
 *  @read: boolean flag to indicate read or write
 *
 *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 **/
STATIC s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
                                         u16 *data, bool read)
{
        s32 ret_val;

        DEBUGFUNC("__e1000_access_emi_reg_locked");

        ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
        if (ret_val)
                return ret_val;

        if (read)
                ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
                                                      data);
        else
                ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
                                                       *data);

        return ret_val;
}

/**
 *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 *  @hw: pointer to the HW structure
 *  @addr: EMI address to program
 *  @data: value to be read from the EMI address
 *
 *  Assumes the SW/FW/HW Semaphore is already acquired.
 **/
s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
{
        DEBUGFUNC("e1000_read_emi_reg_locked");

        return __e1000_access_emi_reg_locked(hw, addr, data, true);
}

/**
 *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 *  @hw: pointer to the HW structure
 *  @addr: EMI address to program
 *  @data: value to be written to the EMI address
 *
 *  Assumes the SW/FW/HW Semaphore is already acquired.
 **/
s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
{
        DEBUGFUNC("e1000_read_emi_reg_locked");

        return __e1000_access_emi_reg_locked(hw, addr, &data, false);
}

/**
 *  e1000_set_eee_pchlan - Enable/disable EEE support
 *  @hw: pointer to the HW structure
 *
 *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 *  the link and the EEE capabilities of the link partner.  The LPI Control
 *  register bits will remain set only if/when link is up.
 *
 *  EEE LPI must not be asserted earlier than one second after link is up.
 *  On 82579, EEE LPI should not be enabled until such time otherwise there
 *  can be link issues with some switches.  Other devices can have EEE LPI
 *  enabled immediately upon link up since they have a timer in hardware which
 *  prevents LPI from being asserted too early.
 **/
s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
{
        struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
        s32 ret_val;
        u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;

        DEBUGFUNC("e1000_set_eee_pchlan");

        switch (hw->phy.type) {
        case e1000_phy_82579:
                lpa = I82579_EEE_LP_ABILITY;
                pcs_status = I82579_EEE_PCS_STATUS;
                adv_addr = I82579_EEE_ADVERTISEMENT;
                break;
        case e1000_phy_i217:
                lpa = I217_EEE_LP_ABILITY;
                pcs_status = I217_EEE_PCS_STATUS;
                adv_addr = I217_EEE_ADVERTISEMENT;
                break;
        default:
                return E1000_SUCCESS;
        }

        ret_val = hw->phy.ops.acquire(hw);
        if (ret_val)
                return ret_val;

        ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
        if (ret_val)
                goto release;

        /* Clear bits that enable EEE in various speeds */
        lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;

        /* Enable EEE if not disabled by user */
        if (!dev_spec->eee_disable) {
                /* Save off link partner's EEE ability */
                ret_val = e1000_read_emi_reg_locked(hw, lpa,
                                                    &dev_spec->eee_lp_ability);
                if (ret_val)
                        goto release;

                /* Read EEE advertisement */
                ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
                if (ret_val)
                        goto release;

                /* Enable EEE only for speeds in which the link partner is
                 * EEE capable and for which we advertise EEE.
                 */
                if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
                        lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;

                if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
                        hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
                        if (data & NWAY_LPAR_100TX_FD_CAPS)
                                lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
                        else
                                /* EEE is not supported in 100Half, so ignore
                                 * partner's EEE in 100 ability if full-duplex
                                 * is not advertised.
                                 */
                                dev_spec->eee_lp_ability &=
                                    ~I82579_EEE_100_SUPPORTED;
                }
        }

        if (hw->phy.type == e1000_phy_82579) {
                ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
                                                    &data);
                if (ret_val)
                        goto release;

                data &= ~I82579_LPI_100_PLL_SHUT;
                ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
                                                     data);
        }

        /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
        ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
        if (ret_val)
                goto release;

        ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
release:
        hw->phy.ops.release(hw);

        return ret_val;
}

/**
 *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
 *  @hw:   pointer to the HW structure
 *  @link: link up bool flag
 *
 *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
 *  preventing further DMA write requests.  Workaround the issue by disabling
 *  the de-assertion of the clock request when in 1Gpbs mode.
 *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
 *  speeds in order to avoid Tx hangs.
 **/
STATIC s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
{
        u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
        u32 status = E1000_READ_REG(hw, E1000_STATUS);
        s32 ret_val = E1000_SUCCESS;
        u16 reg;

        if (link && (status & E1000_STATUS_SPEED_1000)) {
                ret_val = hw->phy.ops.acquire(hw);
                if (ret_val)
                        return ret_val;

                ret_val =
                    e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
                                               &reg);
                if (ret_val)
                        goto release;

                ret_val =
                    e1000_write_kmrn_reg_locked(hw,
                                                E1000_KMRNCTRLSTA_K1_CONFIG,
                                                reg &
                                                ~E1000_KMRNCTRLSTA_K1_ENABLE);
                if (ret_val)
                        goto release;

                usec_delay(10);

                E1000_WRITE_REG(hw, E1000_FEXTNVM6,
                                fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);

                ret_val =
                    e1000_write_kmrn_reg_locked(hw,
                                                E1000_KMRNCTRLSTA_K1_CONFIG,
                                                reg);
release:
                hw->phy.ops.release(hw);
        } else {
                /* clear FEXTNVM6 bit 8 on link down or 10/100 */
                fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;

                if ((hw->phy.revision > 5) || !link ||
                    ((status & E1000_STATUS_SPEED_100) &&
                     (status & E1000_STATUS_FD)))
                        goto update_fextnvm6;

                ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, &reg);
                if (ret_val)
                        return ret_val;

                /* Clear link status transmit timeout */
                reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;

                if (status & E1000_STATUS_SPEED_100) {
                        /* Set inband Tx timeout to 5x10us for 100Half */
                        reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;

                        /* Do not extend the K1 entry latency for 100Half */
                        fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
                } else {
                        /* Set inband Tx timeout to 50x10us for 10Full/Half */
                        reg |= 50 <<
                               I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;

                        /* Extend the K1 entry latency for 10 Mbps */
                        fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
                }

                ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
                if (ret_val)
                        return ret_val;

update_fextnvm6:
                E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
        }

        return ret_val;
}

/**
 *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
 *  @hw: pointer to the HW structure
 *  @to_sx: boolean indicating a system power state transition to Sx
 *
 *  When link is down, configure ULP mode to significantly reduce the power
 *  to the PHY.  If on a Manageability Engine (ME) enabled system, tell the
 *  ME firmware to start the ULP configuration.  If not on an ME enabled
 *  system, configure the ULP mode by software.
 */
s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
{
        u32 mac_reg;
        s32 ret_val = E1000_SUCCESS;
        u16 phy_reg;
        u16 oem_reg = 0;

        if ((hw->mac.type < e1000_pch_lpt) ||
            (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
            (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
            (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
            (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
            (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
                return 0;

        if (!to_sx) {
                int i = 0;
                /* Poll up to 5 seconds for Cable Disconnected indication */
                while (!(E1000_READ_REG(hw, E1000_FEXT) &
                         E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
                        /* Bail if link is re-acquired */
                        if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
                                return -E1000_ERR_PHY;
                        if (i++ == 100)
                                break;

                        msec_delay(50);
                }
                DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
                          (E1000_READ_REG(hw, E1000_FEXT) &
                           E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
                          i * 50);
                if (!(E1000_READ_REG(hw, E1000_FEXT) &
                    E1000_FEXT_PHY_CABLE_DISCONNECTED))
                        return 0;
        }

        if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
                /* Request ME configure ULP mode in the PHY */
                mac_reg = E1000_READ_REG(hw, E1000_H2ME);
                mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
                E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);

                goto out;
        }

        ret_val = hw->phy.ops.acquire(hw);
        if (ret_val)
                goto out;

        /* During S0 Idle keep the phy in PCI-E mode */
        if (hw->dev_spec.ich8lan.smbus_disable)
                goto skip_smbus;

        /* Force SMBus mode in PHY */
        ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
        if (ret_val)
                goto release;
        phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
        e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);

        /* Force SMBus mode in MAC */
        mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
        mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
        E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);

        /* Si workaround for ULP entry flow on i127/rev6 h/w.  Enable
         * LPLU and disable Gig speed when entering ULP
         */
        if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
                ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
                                                       &oem_reg);
                if (ret_val)
                        goto release;

                phy_reg = oem_reg;
                phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;

                ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
                                                        phy_reg);

                if (ret_val)
                        goto release;
        }

skip_smbus:
        if (!to_sx) {
                /* Change the 'Link Status Change' interrupt to trigger
                 * on 'Cable Status Change'
                 */
                ret_val = e1000_read_kmrn_reg_locked(hw,
                                                     E1000_KMRNCTRLSTA_OP_MODES,
                                                     &phy_reg);
                if (ret_val)
                        goto release;
                phy_reg |= E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
                e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
                                            phy_reg);
        }

        /* Set Inband ULP Exit, Reset to SMBus mode and
         * Disable SMBus Release on PERST# in PHY
         */
        ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
        if (ret_val)
                goto release;
        phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
                    I218_ULP_CONFIG1_DISABLE_SMB_PERST);
        if (to_sx) {
                if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
                        phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
                else
                        phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;

                phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
                phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
        } else {
                phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
                phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
                phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
        }
        e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);

        /* Set Disable SMBus Release on PERST# in MAC */
        mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
        mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
        E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);

        /* Commit ULP changes in PHY by starting auto ULP configuration */
        phy_reg |= I218_ULP_CONFIG1_START;
        e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);

        if (!to_sx) {
                /* Disable Tx so that the MAC doesn't send any (buffered)
                 * packets to the PHY.
                 */
                mac_reg = E1000_READ_REG(hw, E1000_TCTL);
                mac_reg &= ~E1000_TCTL_EN;
                E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
        }

        if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
            to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
                ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
                                                        oem_reg);
                if (ret_val)
                        goto release;
        }

release:
        hw->phy.ops.release(hw);
out:
        if (ret_val)
                DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
        else
                hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;

        return ret_val;
}

/**
 *  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
 *  @hw: pointer to the HW structure
 *  @force: boolean indicating whether or not to force disabling ULP
 *
 *  Un-configure ULP mode when link is up, the system is transitioned from
 *  Sx or the driver is unloaded.  If on a Manageability Engine (ME) enabled
 *  system, poll for an indication from ME that ULP has been un-configured.
 *  If not on an ME enabled system, un-configure the ULP mode by software.
 *
 *  During nominal operation, this function is called when link is acquired
 *  to disable ULP mode (force=false); otherwise, for example when unloading
 *  the driver or during Sx->S0 transitions, this is called with force=true
 *  to forcibly disable ULP.

 *  When the cable is plugged in while the device is in D0, a Cable Status
 *  Change interrupt is generated which causes this function to be called
 *  to partially disable ULP mode and restart autonegotiation.  This function
 *  is then called again due to the resulting Link Status Change interrupt
 *  to finish cleaning up after the ULP flow.
 */
s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
{
        s32 ret_val = E1000_SUCCESS;
        u8 ulp_exit_timeout = 30;
        u32 mac_reg;
        u16 phy_reg;
        int i = 0;

        if ((hw->mac.type < e1000_pch_lpt) ||
            (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
            (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
            (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
            (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
            (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
                return 0;

        if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
                if (force) {
                        /* Request ME un-configure ULP mode in the PHY */
                        mac_reg = E1000_READ_REG(hw, E1000_H2ME);
                        mac_reg &= ~E1000_H2ME_ULP;
                        mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
                        E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
                }

                if (hw->mac.type == e1000_pch_cnp)
                        ulp_exit_timeout = 100;

                while (E1000_READ_REG(hw, E1000_FWSM) &
                       E1000_FWSM_ULP_CFG_DONE) {
                        if (i++ == ulp_exit_timeout) {
                                ret_val = -E1000_ERR_PHY;
                                goto out;
                        }

                        msec_delay(10);
                }
                DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);

                if (force) {
                        mac_reg = E1000_READ_REG(hw, E1000_H2ME);
                        mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
                        E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
                } else {
                        /* Clear H2ME.ULP after ME ULP configuration */
                        mac_reg = E1000_READ_REG(hw, E1000_H2ME);
                        mac_reg &= ~E1000_H2ME_ULP;
                        E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);

                        /* Restore link speed advertisements and restart
                         * Auto-negotiation
                         */
                        if (hw->mac.autoneg) {
                                ret_val = e1000_phy_setup_autoneg(hw);
                                if (ret_val)
                                        goto out;
                        } else {
                                ret_val = e1000_setup_copper_link_generic(hw);
                                if (ret_val)
                                        goto out;
                        }
                        ret_val = e1000_oem_bits_config_ich8lan(hw, true);
                }

                goto out;
        }

        ret_val = hw->phy.ops.acquire(hw);
        if (ret_val)
                goto out;

        /* Revert the change to the 'Link Status Change'
         * interrupt to trigger on 'Cable Status Change'
         */
        ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
                                             &phy_reg);
        if (ret_val)
                goto release;
        phy_reg &= ~E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
        e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES, phy_reg);

        if (force)
                /* Toggle LANPHYPC Value bit */
                e1000_toggle_lanphypc_pch_lpt(hw);

        /* Unforce SMBus mode in PHY */
        ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
        if (ret_val) {
                /* The MAC might be in PCIe mode, so temporarily force to
                 * SMBus mode in order to access the PHY.
                 */
                mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
                mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
                E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);

                msec_delay(50);

                ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
                                                       &phy_reg);
                if (ret_val)
                        goto release;
        }
        phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
        e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);

        /* Unforce SMBus mode in MAC */
        mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
        mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
        E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);

        /* When ULP mode was previously entered, K1 was disabled by the
         * hardware.  Re-Enable K1 in the PHY when exiting ULP.
         */
        ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
        if (ret_val)
                goto release;
        phy_reg |= HV_PM_CTRL_K1_ENABLE;
        e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);

        /* Clear ULP enabled configuration */
        ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
        if (ret_val)
                goto release;
        /* CSC interrupt received due to ULP Indication */
        if ((phy_reg & I218_ULP_CONFIG1_IND) || force) {
                phy_reg &= ~(I218_ULP_CONFIG1_IND |
                             I218_ULP_CONFIG1_STICKY_ULP |
                             I218_ULP_CONFIG1_RESET_TO_SMBUS |
                             I218_ULP_CONFIG1_WOL_HOST |
                             I218_ULP_CONFIG1_INBAND_EXIT |
                             I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
                             I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
                             I218_ULP_CONFIG1_DISABLE_SMB_PERST);
                e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);

                /* Commit ULP changes by starting auto ULP configuration */
                phy_reg |= I218_ULP_CONFIG1_START;
                e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);

                /* Clear Disable SMBus Release on PERST# in MAC */
                mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
                mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
                E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);

                if (!force) {
                        hw->phy.ops.release(hw);

                        if (hw->mac.autoneg)
                                e1000_phy_setup_autoneg(hw);
                        else
                                e1000_setup_copper_link_generic(hw);

                        e1000_sw_lcd_config_ich8lan(hw);

                        e1000_oem_bits_config_ich8lan(hw, true);

                        /* Set ULP state to unknown and return non-zero to
                         * indicate no link (yet) and re-enter on the next LSC
                         * to finish disabling ULP flow.
                         */
                        hw->dev_spec.ich8lan.ulp_state =
                            e1000_ulp_state_unknown;

                        return 1;
                }
        }

        /* Re-enable Tx */
        mac_reg = E1000_READ_REG(hw, E1000_TCTL);
        mac_reg |= E1000_TCTL_EN;
        E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);

release:
        hw->phy.ops.release(hw);
        if (force) {
                hw->phy.ops.reset(hw);
                msec_delay(50);
        }
out:
        if (ret_val)
                DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
        else
                hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;

        return ret_val;
}



/**
 *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 *  @hw: pointer to the HW structure
 *
 *  Checks to see of the link status of the hardware has changed.  If a
 *  change in link status has been detected, then we read the PHY registers
 *  to get the current speed/duplex if link exists.
 **/
STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
{
        struct e1000_mac_info *mac = &hw->mac;
        s32 ret_val, tipg_reg = 0;
        u16 emi_addr, emi_val = 0;
        bool link = false;
        u16 phy_reg;

        DEBUGFUNC("e1000_check_for_copper_link_ich8lan");

        /* We only want to go out to the PHY registers to see if Auto-Neg
         * has completed and/or if our link status has changed.  The
         * get_link_status flag is set upon receiving a Link Status
         * Change or Rx Sequence Error interrupt.
         */
        if (!mac->get_link_status)
                return E1000_SUCCESS;

        if ((hw->mac.type < e1000_pch_lpt) ||
            (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
            (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V)) {
                /* First we want to see if the MII Status Register reports
                 * link.  If so, then we want to get the current speed/duplex
                 * of the PHY.
                 */
                ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
                if (ret_val)
                        return ret_val;
        } else {
                /* Check the MAC's STATUS register to determine link state
                 * since the PHY could be inaccessible while in ULP mode.
                 */
                link = !!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);
                if (link)
                        ret_val = e1000_disable_ulp_lpt_lp(hw, false);
                else
                        ret_val = e1000_enable_ulp_lpt_lp(hw, false);
                if (ret_val)
                        return ret_val;
        }

        if (hw->mac.type == e1000_pchlan) {
                ret_val = e1000_k1_gig_workaround_hv(hw, link);
                if (ret_val)
                        return ret_val;
        }

        /* When connected at 10Mbps half-duplex, some parts are excessively
         * aggressive resulting in many collisions. To avoid this, increase
         * the IPG and reduce Rx latency in the PHY.
         */
        if ((hw->mac.type >= e1000_pch2lan) && link) {
                u16 speed, duplex;

                e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex);
                tipg_reg = E1000_READ_REG(hw, E1000_TIPG);
                tipg_reg &= ~E1000_TIPG_IPGT_MASK;

                if (duplex == HALF_DUPLEX && speed == SPEED_10) {
                        tipg_reg |= 0xFF;
                        /* Reduce Rx latency in analog PHY */
                        emi_val = 0;
                } else if (hw->mac.type >= e1000_pch_spt &&
                           duplex == FULL_DUPLEX && speed != SPEED_1000) {
                        tipg_reg |= 0xC;
                        emi_val = 1;
                } else {
                        /* Roll back the default values */
                        tipg_reg |= 0x08;
                        emi_val = 1;
                }

                E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg);

                ret_val = hw->phy.ops.acquire(hw);
                if (ret_val)
                        return ret_val;

                if (hw->mac.type == e1000_pch2lan)
                        emi_addr = I82579_RX_CONFIG;
                else
                        emi_addr = I217_RX_CONFIG;
                ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);


                if (hw->mac.type >= e1000_pch_lpt) {
                        hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG,
                                                    &phy_reg);
                        phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
                        if (speed == SPEED_100 || speed == SPEED_10)
                                phy_reg |= 0x3E8;
                        else
                                phy_reg |= 0xFA;
                        hw->phy.ops.write_reg_locked(hw,
                                                     I217_PLL_CLOCK_GATE_REG,
                                                     phy_reg);

                        if (speed == SPEED_1000) {
                                hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
                                                            &phy_reg);

                                phy_reg |= HV_PM_CTRL_K1_CLK_REQ;

                                hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
                                                             phy_reg);
                                }
                 }
                hw->phy.ops.release(hw);

                if (ret_val)
                        return ret_val;

                if (hw->mac.type >= e1000_pch_spt) {
                        u16 data;
                        u16 ptr_gap;

                        if (speed == SPEED_1000) {
                                ret_val = hw->phy.ops.acquire(hw);
                                if (ret_val)
                                        return ret_val;

                                ret_val = hw->phy.ops.read_reg_locked(hw,
                                                              PHY_REG(776, 20),
                                                              &data);
                                if (ret_val) {
                                        hw->phy.ops.release(hw);
                                        return ret_val;
                                }

                                ptr_gap = (data & (0x3FF << 2)) >> 2;
                                if (ptr_gap < 0x18) {
                                        data &= ~(0x3FF << 2);
                                        data |= (0x18 << 2);
                                        ret_val =
                                                hw->phy.ops.write_reg_locked(hw,
                                                        PHY_REG(776, 20), data);
                                }
                                hw->phy.ops.release(hw);
                                if (ret_val)
                                        return ret_val;
                        } else {
                                ret_val = hw->phy.ops.acquire(hw);
                                if (ret_val)
                                        return ret_val;

                                ret_val = hw->phy.ops.write_reg_locked(hw,
                                                             PHY_REG(776, 20),
                                                             0xC023);
                                hw->phy.ops.release(hw);
                                if (ret_val)
                                        return ret_val;

                        }
                }
        }

        /* I217 Packet Loss issue:
         * ensure that FEXTNVM4 Beacon Duration is set correctly
         * on power up.
         * Set the Beacon Duration for I217 to 8 usec
         */
        if (hw->mac.type >= e1000_pch_lpt) {
                u32 mac_reg;

                mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
                mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
                mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
                E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
        }

        /* Work-around I218 hang issue */
        if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
            (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
            (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
            (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
                ret_val = e1000_k1_workaround_lpt_lp(hw, link);
                if (ret_val)
                        return ret_val;
        }
        /* Clear link partner's EEE ability */
        hw->dev_spec.ich8lan.eee_lp_ability = 0;

        /* Configure K0s minimum time */
        if (hw->mac.type >= e1000_pch_lpt) {
                e1000_configure_k0s_lpt(hw, K1_ENTRY_LATENCY, K1_MIN_TIME);
        }

        if (hw->mac.type >= e1000_pch_lpt) {
                u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);

                if (hw->mac.type == e1000_pch_spt) {
                        /* FEXTNVM6 K1-off workaround - for SPT only */
                        u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG);

                        if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
                                fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
                        else
                                fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
                }

                if (hw->dev_spec.ich8lan.disable_k1_off == true)
                        fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;

                E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
        }

        if (!link)
                return E1000_SUCCESS; /* No link detected */

        mac->get_link_status = false;

        switch (hw->mac.type) {
        case e1000_pch2lan:
                ret_val = e1000_k1_workaround_lv(hw);
                if (ret_val)
                        return ret_val;
                /* fall-thru */
        case e1000_pchlan:
                if (hw->phy.type == e1000_phy_82578) {
                        ret_val = e1000_link_stall_workaround_hv(hw);
                        if (ret_val)
                                return ret_val;
                }

                /* Workaround for PCHx parts in half-duplex:
                 * Set the number of preambles removed from the packet
                 * when it is passed from the PHY to the MAC to prevent
                 * the MAC from misinterpreting the packet type.
                 */
                hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
                phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;

                if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
                    E1000_STATUS_FD)
                        phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);

                hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
                break;
        default:
                break;
        }

        /* Check if there was DownShift, must be checked
         * immediately after link-up
         */
        e1000_check_downshift_generic(hw);

        /* Enable/Disable EEE after link up */
        if (hw->phy.type > e1000_phy_82579) {
                ret_val = e1000_set_eee_pchlan(hw);
                if (ret_val)
                        return ret_val;
        }

        /* If we are forcing speed/duplex, then we simply return since
         * we have already determined whether we have link or not.
         */
        if (!mac->autoneg)
                return -E1000_ERR_CONFIG;

        /* Auto-Neg is enabled.  Auto Speed Detection takes care
         * of MAC speed/duplex configuration.  So we only need to
         * configure Collision Distance in the MAC.
         */
        mac->ops.config_collision_dist(hw);

        /* Configure Flow Control now that Auto-Neg has completed.
         * First, we need to restore the desired flow control
         * settings because we may have had to re-autoneg with a
         * different link partner.
         */
        ret_val = e1000_config_fc_after_link_up_generic(hw);
        if (ret_val)
                DEBUGOUT("Error configuring flow control\n");

        return ret_val;
}

/**
 *  e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
 *  @hw: pointer to the HW structure
 *
 *  Initialize family-specific function pointers for PHY, MAC, and NVM.
 **/
void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
{
        DEBUGFUNC("e1000_init_function_pointers_ich8lan");

        hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
        hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
        switch (hw->mac.type) {
        case e1000_ich8lan:
        case e1000_ich9lan:
        case e1000_ich10lan:
                hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
                break;
        case e1000_pchlan:
        case e1000_pch2lan:
        case e1000_pch_lpt:
        case e1000_pch_spt:
        case e1000_pch_cnp:
        case e1000_pch_adp:
                hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
                break;
        default:
                break;
        }
}

/**
 *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
 *  @hw: pointer to the HW structure
 *
 *  Acquires the mutex for performing NVM operations.
 **/
STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
{
        DEBUGFUNC("e1000_acquire_nvm_ich8lan");

        E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);

        return E1000_SUCCESS;
}

/**
 *  e1000_release_nvm_ich8lan - Release NVM mutex
 *  @hw: pointer to the HW structure
 *
 *  Releases the mutex used while performing NVM operations.
 **/
STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
{
        DEBUGFUNC("e1000_release_nvm_ich8lan");

        E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);

        return;
}

/**
 *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 *  @hw: pointer to the HW structure
 *
 *  Acquires the software control flag for performing PHY and select
 *  MAC CSR accesses.
 **/
STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
{
        u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
        s32 ret_val = E1000_SUCCESS;

        DEBUGFUNC("e1000_acquire_swflag_ich8lan");

        E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);

        while (timeout) {
                extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
                if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
                        break;

                msec_delay_irq(1);
                timeout--;
        }

        if (!timeout) {
                DEBUGOUT("SW has already locked the resource.\n");
                ret_val = -E1000_ERR_CONFIG;
                goto out;
        }

        timeout = SW_FLAG_TIMEOUT;

        extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
        E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);

        while (timeout) {
                extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
                if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
                        break;

                msec_delay_irq(1);
                timeout--;
        }

        if (!timeout) {
                DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
                          E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
                extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
                E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
                ret_val = -E1000_ERR_CONFIG;
                goto out;
        }

out:
        if (ret_val)
                E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);

        return ret_val;
}

/**
 *  e1000_release_swflag_ich8lan - Release software control flag
 *  @hw: pointer to the HW structure
 *
 *  Releases the software control flag for performing PHY and select
 *  MAC CSR accesses.
 **/
STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
{
        u32 extcnf_ctrl;

        DEBUGFUNC("e1000_release_swflag_ich8lan");

        extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);

        if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
                extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
                E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
        } else {
                DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
        }

        E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);

        return;
}

/**
 *  e1000_check_mng_mode_ich8lan - Checks management mode
 *  @hw: pointer to the HW structure
 *
 *  This checks if the adapter has any manageability enabled.
 *  This is a function pointer entry point only called by read/write
 *  routines for the PHY and NVM parts.
 **/
STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
{
        u32 fwsm;

        DEBUGFUNC("e1000_check_mng_mode_ich8lan");

        fwsm = E1000_READ_REG(hw, E1000_FWSM);

        return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
               ((fwsm & E1000_FWSM_MODE_MASK) ==
                (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
}

/**
 *  e1000_check_mng_mode_pchlan - Checks management mode
 *  @hw: pointer to the HW structure
 *
 *  This checks if the adapter has iAMT enabled.
 *  This is a function pointer entry point only called by read/write
 *  routines for the PHY and NVM parts.
 **/
STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
{
        u32 fwsm;

        DEBUGFUNC("e1000_check_mng_mode_pchlan");

        fwsm = E1000_READ_REG(hw, E1000_FWSM);

        return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
               (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
}

/**
 *  e1000_rar_set_pch2lan - Set receive address register
 *  @hw: pointer to the HW structure
 *  @addr: pointer to the receive address
 *  @index: receive address array register
 *
 *  Sets the receive address array register at index to the address passed
 *  in by addr.  For 82579, RAR[0] is the base address register that is to
 *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
 *  Use SHRA[0-3] in place of those reserved for ME.
 **/
STATIC int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
{
        u32 rar_low, rar_high;

        DEBUGFUNC("e1000_rar_set_pch2lan");

        /* HW expects these in little endian so we reverse the byte order
         * from network order (big endian) to little endian
         */
        rar_low = ((u32) addr[0] |
                   ((u32) addr[1] << 8) |
                   ((u32) addr[2] << 16) | ((u32) addr[3] << 24));

        rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));

        /* If MAC address zero, no need to set the AV bit */
        if (rar_low || rar_high)
                rar_high |= E1000_RAH_AV;

        if (index == 0) {
                E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
                E1000_WRITE_FLUSH(hw);
                E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
                E1000_WRITE_FLUSH(hw);
                return E1000_SUCCESS;
        }

        /* RAR[1-6] are owned by manageability.  Skip those and program the
         * next address into the SHRA register array.
         */
        if (index < (u32) (hw->mac.rar_entry_count)) {
                s32 ret_val;

                ret_val = e1000_acquire_swflag_ich8lan(hw);
                if (ret_val)
                        goto out;

                E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
                E1000_WRITE_FLUSH(hw);
                E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
                E1000_WRITE_FLUSH(hw);

                e1000_release_swflag_ich8lan(hw);

                /* verify the register updates */
                if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
                    (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
                        return E1000_SUCCESS;

                DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
                         (index - 1), E1000_READ_REG(hw, E1000_FWSM));
        }

out:
        DEBUGOUT1("Failed to write receive address at index %d\n", index);
        return -E1000_ERR_CONFIG;
}

/**
 *  e1000_rar_set_pch_lpt - Set receive address registers
 *  @hw: pointer to the HW structure
 *  @addr: pointer to the receive address
 *  @index: receive address array register
 *
 *  Sets the receive address register array at index to the address passed

 *  in by addr. For LPT, RAR[0] is the base address register that is to
 *  contain the MAC address. SHRA[0-10] are the shared receive address
 *  registers that are shared between the Host and manageability engine (ME).
 **/
STATIC int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
{
        u32 rar_low, rar_high;
        u32 wlock_mac;

        DEBUGFUNC("e1000_rar_set_pch_lpt");

        /* HW expects these in little endian so we reverse the byte order
         * from network order (big endian) to little endian
         */
        rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
                   ((u32) addr[2] << 16) | ((u32) addr[3] << 24));

        rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));

        /* If MAC address zero, no need to set the AV bit */
        if (rar_low || rar_high)
                rar_high |= E1000_RAH_AV;

        if (index == 0) {
                E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
                E1000_WRITE_FLUSH(hw);
                E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
                E1000_WRITE_FLUSH(hw);
                return E1000_SUCCESS;
        }

        /* The manageability engine (ME) can lock certain SHRAR registers that
         * it is using - those registers are unavailable for use.
         */
        if (index < hw->mac.rar_entry_count) {
                wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
                            E1000_FWSM_WLOCK_MAC_MASK;
                wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;

                /* Check if all SHRAR registers are locked */
                if (wlock_mac == 1)
                        goto out;

                if ((wlock_mac == 0) || (index <= wlock_mac)) {
                        s32 ret_val;

                        ret_val = e1000_acquire_swflag_ich8lan(hw);

                        if (ret_val)
                                goto out;

                        E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
                                        rar_low);
                        E1000_WRITE_FLUSH(hw);
                        E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
                                        rar_high);
                        E1000_WRITE_FLUSH(hw);

                        e1000_release_swflag_ich8lan(hw);

                        /* verify the register updates */
                        if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
                            (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
                                return E1000_SUCCESS;
                }
        }

out:
        DEBUGOUT1("Failed to write receive address at index %d\n", index);
        return -E1000_ERR_CONFIG;
}

/**
 *  e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
 *  @hw: pointer to the HW structure
 *  @mc_addr_list: array of multicast addresses to program
 *  @mc_addr_count: number of multicast addresses to program
 *
 *  Updates entire Multicast Table Array of the PCH2 MAC and PHY.
 *  The caller must have a packed mc_addr_list of multicast addresses.
 **/
STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
                                              u8 *mc_addr_list,
                                              u32 mc_addr_count)
{
        u16 phy_reg = 0;
        int i;
        s32 ret_val;

        DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");

        e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);

        ret_val = hw->phy.ops.acquire(hw);
        if (ret_val)
                return;

        ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
        if (ret_val)
                goto release;

        for (i = 0; i < hw->mac.mta_reg_count; i++) {
                hw->phy.ops.write_reg_page(hw, BM_MTA(i),
                                           (u16)(hw->mac.mta_shadow[i] &
                                                 0xFFFF));
                hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
                                           (u16)((hw->mac.mta_shadow[i] >> 16) &
                                                 0xFFFF));
        }

        e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);

release:
        hw->phy.ops.release(hw);
}

/**
 *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 *  @hw: pointer to the HW structure
 *
 *  Checks if firmware is blocking the reset of the PHY.
 *  This is a function pointer entry point only called by
 *  reset routines.
 **/
STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
{
        u32 fwsm;
        bool blocked = false;
        int i = 0;

        DEBUGFUNC("e1000_check_reset_block_ich8lan");

        do {
                fwsm = E1000_READ_REG(hw, E1000_FWSM);
                if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
                        blocked = true;
                        msec_delay(10);
                        continue;
                }
                blocked = false;
        } while (blocked && (i++ < 30));
        return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
}

/**
 *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
 *  @hw: pointer to the HW structure
 *
 *  Assumes semaphore already acquired.
 *
 **/
STATIC s32 e1000_write_smbus_addr(struct e1000_hw *hw)
{
        u16 phy_data;
        u32 strap = E1000_READ_REG(hw, E1000_STRAP);
        u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
                E1000_STRAP_SMT_FREQ_SHIFT;
        s32 ret_val;

        strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;

        ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
        if (ret_val)
                return ret_val;

        phy_data &= ~HV_SMB_ADDR_MASK;
        phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
        phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;

        if (hw->phy.type == e1000_phy_i217) {
                /* Restore SMBus frequency */
                if (freq--) {
                        phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
                        phy_data |= (freq & (1 << 0)) <<
                                HV_SMB_ADDR_FREQ_LOW_SHIFT;
                        phy_data |= (freq & (1 << 1)) <<
                                (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
                } else {
                        DEBUGOUT("Unsupported SMB frequency in PHY\n");
                }
        }

        return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
}

/**
 *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
 *  @hw:   pointer to the HW structure
 *
 *  SW should configure the LCD from the NVM extended configuration region
 *  as a workaround for certain parts.
 **/
STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
{
        struct e1000_phy_info *phy = &hw->phy;
        u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
        s32 ret_val = E1000_SUCCESS;
        u16 word_addr, reg_data, reg_addr, phy_page = 0;

        DEBUGFUNC("e1000_sw_lcd_config_ich8lan");

        /* Initialize the PHY from the NVM on ICH platforms.  This
         * is needed due to an issue where the NVM configuration is
         * not properly autoloaded after power transitions.
         * Therefore, after each PHY reset, we will load the
         * configuration data out of the NVM manually.
         */
        switch (hw->mac.type) {
        case e1000_ich8lan:
                if (phy->type != e1000_phy_igp_3)
                        return ret_val;

                if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
                    (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
                        sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
                        break;
                }
                /* Fall-thru */
        case e1000_pchlan:
        case e1000_pch2lan:
        case e1000_pch_lpt:
        case e1000_pch_spt:
        case e1000_pch_cnp:
        case e1000_pch_adp:
                sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
                break;
        default:
                return ret_val;
        }

        ret_val = hw->phy.ops.acquire(hw);
        if (ret_val)
                return ret_val;

        data = E1000_READ_REG(hw, E1000_FEXTNVM);
        if (!(data & sw_cfg_mask))
                goto release;

        /* Make sure HW does not configure LCD from PHY
         * extended configuration before SW configuration
         */
        data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
        if ((hw->mac.type < e1000_pch2lan) &&
            (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
                        goto release;

        cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
        cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
        cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
        if (!cnf_size)
                goto release;

        cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
        cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;

        if (((hw->mac.type == e1000_pchlan) &&
             !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
            (hw->mac.type > e1000_pchlan)) {
                /* HW configures the SMBus address and LEDs when the
                 * OEM and LCD Write Enable bits are set in the NVM.
                 * When both NVM bits are cleared, SW will configure
                 * them instead.
                 */
                ret_val = e1000_write_smbus_addr(hw);
                if (ret_val)
                        goto release;

                data = E1000_READ_REG(hw, E1000_LEDCTL);
                ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
                                                        (u16)data);
                if (ret_val)
                        goto release;
        }

        /* Configure LCD from extended configuration region. */

        /* cnf_base_addr is in DWORD */
        word_addr = (u16)(cnf_base_addr << 1);

        for (i = 0; i < cnf_size; i++) {
                ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
                                           &reg_data);
                if (ret_val)
                        goto release;

                ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
                                           1, &reg_addr);
                if (ret_val)
                        goto release;

                /* Save off the PHY page for future writes. */
                if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
                        phy_page = reg_data;
                        continue;
                }

                reg_addr &= PHY_REG_MASK;
                reg_addr |= phy_page;

                ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
                                                    reg_data);
                if (ret_val)
                        goto release;
        }

release:
        hw->phy.ops.release(hw);
        return ret_val;
}

/**
 *  e1000_k1_gig_workaround_hv - K1 Si workaround
 *  @hw:   pointer to the HW structure
 *  @link: link up bool flag
 *
 *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
 *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
 *  If link is down, the function will restore the default K1 setting located
 *  in the NVM.
 **/
STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
{
        s32 ret_val = E1000_SUCCESS;
        u16 status_reg = 0;
        bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;

        DEBUGFUNC("e1000_k1_gig_workaround_hv");

        if (hw->mac.type != e1000_pchlan)
                return E1000_SUCCESS;

        /* Wrap the whole flow with the sw flag */
        ret_val = hw->phy.ops.acquire(hw);
        if (ret_val)
                return ret_val;

        /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
        if (link) {
                if (hw->phy.type == e1000_phy_82578) {
                        ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
                                                              &status_reg);
                        if (ret_val)
                                goto release;

                        status_reg &= (BM_CS_STATUS_LINK_UP |
                                       BM_CS_STATUS_RESOLVED |
                                       BM_CS_STATUS_SPEED_MASK);

                        if (status_reg == (BM_CS_STATUS_LINK_UP |
                                           BM_CS_STATUS_RESOLVED |
                                           BM_CS_STATUS_SPEED_1000))
                                k1_enable = false;
                }

                if (hw->phy.type == e1000_phy_82577) {
                        ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
                                                              &status_reg);
                        if (ret_val)
                                goto release;

                        status_reg &= (HV_M_STATUS_LINK_UP |
                                       HV_M_STATUS_AUTONEG_COMPLETE |
                                       HV_M_STATUS_SPEED_MASK);

                        if (status_reg == (HV_M_STATUS_LINK_UP |
                                           HV_M_STATUS_AUTONEG_COMPLETE |
                                           HV_M_STATUS_SPEED_1000))
                                k1_enable = false;
                }

                /* Link stall fix for link up */
                ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
                                                       0x0100);
                if (ret_val)
                        goto release;

        } else {
                /* Link stall fix for link down */
                ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
                                                       0x4100);
                if (ret_val)
                        goto release;
        }

        ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);

release:
        hw->phy.ops.release(hw);

        return ret_val;
}

/**
 *  e1000_configure_k1_ich8lan - Configure K1 power state
 *  @hw: pointer to the HW structure
 *  @k1_enable: K1 state to configure
 *
 *  Configure the K1 power state based on the provided parameter.
 *  Assumes semaphore already acquired.
 *
 *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
 **/
s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
{
        s32 ret_val;
        u32 ctrl_reg = 0;
        u32 ctrl_ext = 0;
        u32 reg = 0;
        u16 kmrn_reg = 0;

        DEBUGFUNC("e1000_configure_k1_ich8lan");

        ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
                                             &kmrn_reg);
        if (ret_val)
                return ret_val;

        if (k1_enable)
                kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
        else
                kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;

        ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
                                              kmrn_reg);
        if (ret_val)
                return ret_val;

        usec_delay(20);
        ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
        ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);

        reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
        reg |= E1000_CTRL_FRCSPD;
        E1000_WRITE_REG(hw, E1000_CTRL, reg);

        E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
        E1000_WRITE_FLUSH(hw);
        usec_delay(20);
        E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
        E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
        E1000_WRITE_FLUSH(hw);
        usec_delay(20);

        return E1000_SUCCESS;
}

/**
 *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
 *  @hw:       pointer to the HW structure
 *  @d0_state: boolean if entering d0 or d3 device state
 *
 *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
 *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
 *  in NVM determines whether HW should configure LPLU and Gbe Disable.
 **/
STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
{
        s32 ret_val = 0;
        u32 mac_reg;
        u16 oem_reg;

        DEBUGFUNC("e1000_oem_bits_config_ich8lan");

        if (hw->mac.type < e1000_pchlan)
                return ret_val;

        ret_val = hw->phy.ops.acquire(hw);
        if (ret_val)
                return ret_val;

        if (hw->mac.type == e1000_pchlan) {
                mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
                if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
                        goto release;
        }

        mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
        if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
                goto release;

        mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);

        ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
        if (ret_val)
                goto release;

        oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);

        if (d0_state) {
                if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
                        oem_reg |= HV_OEM_BITS_GBE_DIS;

                if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
                        oem_reg |= HV_OEM_BITS_LPLU;
        } else {
                if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
                    E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
                        oem_reg |= HV_OEM_BITS_GBE_DIS;

                if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
                    E1000_PHY_CTRL_NOND0A_LPLU))
                        oem_reg |= HV_OEM_BITS_LPLU;
        }

        /* Set Restart auto-neg to activate the bits */
        if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
            !hw->phy.ops.check_reset_block(hw))
                oem_reg |= HV_OEM_BITS_RESTART_AN;

        ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);

release:
        hw->phy.ops.release(hw);

        return ret_val;
}


/**
 *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
 *  @hw:   pointer to the HW structure
 **/
STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
{
        s32 ret_val;
        u16 data;

        DEBUGFUNC("e1000_set_mdio_slow_mode_hv");

        ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
        if (ret_val)
                return ret_val;

        data |= HV_KMRN_MDIO_SLOW;

        ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);

        return ret_val;
}

/**
 *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
 *  done after every PHY reset.
 *  @hw: pointer to the HW structure
 **/
STATIC s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
{
        s32 ret_val = E1000_SUCCESS;
        u16 phy_data;

        DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");

        if (hw->mac.type != e1000_pchlan)
                return E1000_SUCCESS;

        /* Set MDIO slow mode before any other MDIO access */
        if (hw->phy.type == e1000_phy_82577) {
                ret_val = e1000_set_mdio_slow_mode_hv(hw);
                if (ret_val)
                        return ret_val;
        }

        if (((hw->phy.type == e1000_phy_82577) &&
             ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
            ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
                /* Disable generation of early preamble */
                ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
                if (ret_val)
                        return ret_val;

                /* Preamble tuning for SSC */
                ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
                                                0xA204);
                if (ret_val)
                        return ret_val;
        }

        if (hw->phy.type == e1000_phy_82578) {
                /* Return registers to default by doing a soft reset then
                 * writing 0x3140 to the control register.
                 */
                if (hw->phy.revision < 2) {
                        e1000_phy_sw_reset_generic(hw);
                        ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
                                                        0x3140);
                }
        }

        /* Select page 0 */
        ret_val = hw->phy.ops.acquire(hw);
        if (ret_val)
                return ret_val;

        hw->phy.addr = 1;
        ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
        hw->phy.ops.release(hw);
        if (ret_val)
                return ret_val;

        /* Configure the K1 Si workaround during phy reset assuming there is
         * link so that it disables K1 if link is in 1Gbps.
         */
        ret_val = e1000_k1_gig_workaround_hv(hw, true);
        if (ret_val)
                return ret_val;

        /* Workaround for link disconnects on a busy hub in half duplex */
        ret_val = hw->phy.ops.acquire(hw);
        if (ret_val)
                return ret_val;
        ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
        if (ret_val)
                goto release;
        ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
                                               phy_data & 0x00FF);
        if (ret_val)
                goto release;

        /* set MSE higher to enable link to stay up when noise is high */
        ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
release:
        hw->phy.ops.release(hw);

        return ret_val;
}

/**
 *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
 *  @hw:   pointer to the HW structure
 **/
void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
{
        u32 mac_reg;
        u16 i, phy_reg = 0;
        s32 ret_val;

        DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");

        ret_val = hw->phy.ops.acquire(hw);
        if (ret_val)
                return;
        ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
        if (ret_val)
                goto release;

        /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
        for (i = 0; i < (hw->mac.rar_entry_count); i++) {
                mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
                hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
                                           (u16)(mac_reg & 0xFFFF));
                hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
                                           (u16)((mac_reg >> 16) & 0xFFFF));

                mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
                hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
                                           (u16)(mac_reg & 0xFFFF));
                hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
                                           (u16)((mac_reg & E1000_RAH_AV)
                                                 >> 16));
        }

        e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);

release:
        hw->phy.ops.release(hw);
}

STATIC u32 e1000_calc_rx_da_crc(u8 mac[])
{
        u32 poly = 0xEDB88320;  /* Polynomial for 802.3 CRC calculation */
        u32 i, j, mask, crc;

        DEBUGFUNC("e1000_calc_rx_da_crc");

        crc = 0xffffffff;
        for (i = 0; i < 6; i++) {
                crc = crc ^ mac[i];
                for (j = 8; j > 0; j--) {
                        mask = (crc & 1) * (-1);
                        crc = (crc >> 1) ^ (poly & mask);
                }
        }
        return ~crc;
}

/**
 *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
 *  with 82579 PHY
 *  @hw: pointer to the HW structure
 *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
 **/
s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
{
        s32 ret_val = E1000_SUCCESS;
        u16 phy_reg, data;
        u32 mac_reg;
        u16 i;

        DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");

        if (hw->mac.type < e1000_pch2lan)
                return E1000_SUCCESS;

        /* disable Rx path while enabling/disabling workaround */
        hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
        ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
                                        phy_reg | (1 << 14));
        if (ret_val)
                return ret_val;

        if (enable) {
                /* Write Rx addresses (rar_entry_count for RAL/H, and
                 * SHRAL/H) and initial CRC values to the MAC
                 */
                for (i = 0; i < hw->mac.rar_entry_count; i++) {
                        u8 mac_addr[ETH_ADDR_LEN] = {0};
                        u32 addr_high, addr_low;

                        addr_high = E1000_READ_REG(hw, E1000_RAH(i));
                        if (!(addr_high & E1000_RAH_AV))
                                continue;
                        addr_low = E1000_READ_REG(hw, E1000_RAL(i));
                        mac_addr[0] = (addr_low & 0xFF);
                        mac_addr[1] = ((addr_low >> 8) & 0xFF);
                        mac_addr[2] = ((addr_low >> 16) & 0xFF);
                        mac_addr[3] = ((addr_low >> 24) & 0xFF);
                        mac_addr[4] = (addr_high & 0xFF);
                        mac_addr[5] = ((addr_high >> 8) & 0xFF);

                        E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
                                        e1000_calc_rx_da_crc(mac_addr));
                }

                /* Write Rx addresses to the PHY */
                e1000_copy_rx_addrs_to_phy_ich8lan(hw);

                /* Enable jumbo frame workaround in the MAC */
                mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
                mac_reg &= ~(1 << 14);
                mac_reg |= (7 << 15);
                E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);

                mac_reg = E1000_READ_REG(hw, E1000_RCTL);
                mac_reg |= E1000_RCTL_SECRC;
                E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);

                ret_val = e1000_read_kmrn_reg_generic(hw,
                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
                                                &data);
                if (ret_val)
                        return ret_val;
                ret_val = e1000_write_kmrn_reg_generic(hw,
                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
                                                data | (1 << 0));
                if (ret_val)
                        return ret_val;
                ret_val = e1000_read_kmrn_reg_generic(hw,
                                                E1000_KMRNCTRLSTA_HD_CTRL,
                                                &data);
                if (ret_val)
                        return ret_val;
                data &= ~(0xF << 8);
                data |= (0xB << 8);
                ret_val = e1000_write_kmrn_reg_generic(hw,
                                                E1000_KMRNCTRLSTA_HD_CTRL,
                                                data);
                if (ret_val)
                        return ret_val;

                /* Enable jumbo frame workaround in the PHY */
                hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
                data &= ~(0x7F << 5);
                data |= (0x37 << 5);
                ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
                if (ret_val)
                        return ret_val;
                hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
                data &= ~(1 << 13);
                ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
                if (ret_val)
                        return ret_val;
                hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
                data &= ~(0x3FF << 2);
                data |= (E1000_TX_PTR_GAP << 2);
                ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
                if (ret_val)
                        return ret_val;
                ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
                if (ret_val)
                        return ret_val;
                hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
                ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
                                                (1 << 10));
                if (ret_val)
                        return ret_val;
        } else {
                /* Write MAC register values back to h/w defaults */
                mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
                mac_reg &= ~(0xF << 14);
                E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);

                mac_reg = E1000_READ_REG(hw, E1000_RCTL);
                mac_reg &= ~E1000_RCTL_SECRC;
                E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);

                ret_val = e1000_read_kmrn_reg_generic(hw,
                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
                                                &data);
                if (ret_val)
                        return ret_val;
                ret_val = e1000_write_kmrn_reg_generic(hw,
                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
                                                data & ~(1 << 0));
                if (ret_val)
                        return ret_val;
                ret_val = e1000_read_kmrn_reg_generic(hw,
                                                E1000_KMRNCTRLSTA_HD_CTRL,
                                                &data);
                if (ret_val)
                        return ret_val;
                data &= ~(0xF << 8);
                data |= (0xB << 8);
                ret_val = e1000_write_kmrn_reg_generic(hw,
                                                E1000_KMRNCTRLSTA_HD_CTRL,
                                                data);
                if (ret_val)
                        return ret_val;

                /* Write PHY register values back to h/w defaults */
                hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
                data &= ~(0x7F << 5);
                ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
                if (ret_val)
                        return ret_val;
                hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
                data |= (1 << 13);
                ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
                if (ret_val)
                        return ret_val;
                hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
                data &= ~(0x3FF << 2);
                data |= (0x8 << 2);
                ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
                if (ret_val)
                        return ret_val;
                ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
                if (ret_val)
                        return ret_val;
                hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
                ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
                                                ~(1 << 10));
                if (ret_val)
                        return ret_val;
        }

        /* re-enable Rx path after enabling/disabling workaround */
        return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
                                     ~(1 << 14));
}

/**
 *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
 *  done after every PHY reset.
 *  @hw: pointer to the HW structure
 **/
STATIC s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
{
        s32 ret_val = E1000_SUCCESS;

        DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");

        if (hw->mac.type != e1000_pch2lan)
                return E1000_SUCCESS;

        /* Set MDIO slow mode before any other MDIO access */
        ret_val = e1000_set_mdio_slow_mode_hv(hw);
        if (ret_val)
                return ret_val;

        ret_val = hw->phy.ops.acquire(hw);
        if (ret_val)
                return ret_val;
        /* set MSE higher to enable link to stay up when noise is high */
        ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
        if (ret_val)
                goto release;
        /* drop link after 5 times MSE threshold was reached */
        ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
release:
        hw->phy.ops.release(hw);

        return ret_val;
}

/**
 *  e1000_k1_gig_workaround_lv - K1 Si workaround
 *  @hw:   pointer to the HW structure
 *
 *  Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
 *  Disable K1 for 1000 and 100 speeds
 **/
STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
{
        s32 ret_val = E1000_SUCCESS;
        u16 status_reg = 0;

        DEBUGFUNC("e1000_k1_workaround_lv");

        if (hw->mac.type != e1000_pch2lan)
                return E1000_SUCCESS;

        /* Set K1 beacon duration based on 10Mbs speed */
        ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
        if (ret_val)
                return ret_val;

        if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
            == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
                if (status_reg &
                    (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
                        u16 pm_phy_reg;

                        /* LV 1G/100 Packet drop issue wa  */
                        ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
                                                       &pm_phy_reg);
                        if (ret_val)
                                return ret_val;
                        pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
                        ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
                                                        pm_phy_reg);
                        if (ret_val)
                                return ret_val;
                } else {
                        u32 mac_reg;
                        mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
                        mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
                        mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
                        E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
                }
        }

        return ret_val;
}

/**
 *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
 *  @hw:   pointer to the HW structure
 *  @gate: boolean set to true to gate, false to ungate
 *
 *  Gate/ungate the automatic PHY configuration via hardware; perform
 *  the configuration via software instead.
 **/
STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
{
        u32 extcnf_ctrl;

        DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");

        if (hw->mac.type < e1000_pch2lan)
                return;

        extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);

        if (gate)
                extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
        else
                extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;

        E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
}

/**
 *  e1000_lan_init_done_ich8lan - Check for PHY config completion
 *  @hw: pointer to the HW structure
 *
 *  Check the appropriate indication the MAC has finished configuring the
 *  PHY after a software reset.
 **/
STATIC void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
{
        u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;

        DEBUGFUNC("e1000_lan_init_done_ich8lan");

        /* Wait for basic configuration completes before proceeding */
        do {
                data = E1000_READ_REG(hw, E1000_STATUS);
                data &= E1000_STATUS_LAN_INIT_DONE;
                usec_delay(100);
        } while ((!data) && --loop);

        /* If basic configuration is incomplete before the above loop
         * count reaches 0, loading the configuration from NVM will
         * leave the PHY in a bad state possibly resulting in no link.
         */
        if (loop == 0)
                DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");

        /* Clear the Init Done bit for the next init event */
        data = E1000_READ_REG(hw, E1000_STATUS);