1
2
3
4
5#include <sys/queue.h>
6#include <stdio.h>
7#include <errno.h>
8#include <stdint.h>
9#include <stdarg.h>
10
11#include <rte_string_fns.h>
12#include <rte_common.h>
13#include <rte_interrupts.h>
14#include <rte_byteorder.h>
15#include <rte_log.h>
16#include <rte_debug.h>
17#include <rte_pci.h>
18#include <rte_bus_pci.h>
19#include <rte_ether.h>
20#include <ethdev_driver.h>
21#include <ethdev_pci.h>
22#include <rte_memory.h>
23#include <rte_eal.h>
24#include <rte_malloc.h>
25#include <rte_dev.h>
26
27#include "e1000_logs.h"
28#include "base/e1000_api.h"
29#include "e1000_ethdev.h"
30#include "igb_regs.h"
31
32
33
34
35#define IGB_DEFAULT_RX_FREE_THRESH 32
36
37#define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
38#define IGB_DEFAULT_RX_HTHRESH 8
39#define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
40
41#define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
42#define IGB_DEFAULT_TX_HTHRESH 1
43#define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
44
45
46#define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
47#define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
48#define IGB_8_BIT_WIDTH CHAR_BIT
49#define IGB_8_BIT_MASK UINT8_MAX
50
51
52#define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
53#define E1000_ETQF_FILTER_1588 3
54#define IGB_82576_TSYNC_SHIFT 16
55#define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
56#define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
57#define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
58
59#define E1000_VTIVAR_MISC 0x01740
60#define E1000_VTIVAR_MISC_MASK 0xFF
61#define E1000_VTIVAR_VALID 0x80
62#define E1000_VTIVAR_MISC_MAILBOX 0
63#define E1000_VTIVAR_MISC_INTR_MASK 0x3
64
65
66#define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
67
68
69#define E1000_VET_VET_EXT 0xFFFF0000
70#define E1000_VET_VET_EXT_SHIFT 16
71
72
73#define IGB_MSIX_OTHER_INTR_VEC 0
74
75static int eth_igb_configure(struct rte_eth_dev *dev);
76static int eth_igb_start(struct rte_eth_dev *dev);
77static int eth_igb_stop(struct rte_eth_dev *dev);
78static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
79static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
80static int eth_igb_close(struct rte_eth_dev *dev);
81static int eth_igb_reset(struct rte_eth_dev *dev);
82static int eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
83static int eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
84static int eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
85static int eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
86static int eth_igb_link_update(struct rte_eth_dev *dev,
87 int wait_to_complete);
88static int eth_igb_stats_get(struct rte_eth_dev *dev,
89 struct rte_eth_stats *rte_stats);
90static int eth_igb_xstats_get(struct rte_eth_dev *dev,
91 struct rte_eth_xstat *xstats, unsigned n);
92static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
93 const uint64_t *ids,
94 uint64_t *values, unsigned int n);
95static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
96 struct rte_eth_xstat_name *xstats_names,
97 unsigned int size);
98static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
99 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
100 unsigned int limit);
101static int eth_igb_stats_reset(struct rte_eth_dev *dev);
102static int eth_igb_xstats_reset(struct rte_eth_dev *dev);
103static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
104 char *fw_version, size_t fw_size);
105static int eth_igb_infos_get(struct rte_eth_dev *dev,
106 struct rte_eth_dev_info *dev_info);
107static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
108static int eth_igbvf_infos_get(struct rte_eth_dev *dev,
109 struct rte_eth_dev_info *dev_info);
110static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
111 struct rte_eth_fc_conf *fc_conf);
112static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
113 struct rte_eth_fc_conf *fc_conf);
114static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
115static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
116static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
117static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
118 struct rte_intr_handle *handle);
119static void eth_igb_interrupt_handler(void *param);
120static int igb_hardware_init(struct e1000_hw *hw);
121static void igb_hw_control_acquire(struct e1000_hw *hw);
122static void igb_hw_control_release(struct e1000_hw *hw);
123static void igb_init_manageability(struct e1000_hw *hw);
124static void igb_release_manageability(struct e1000_hw *hw);
125
126static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
127
128static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
129 uint16_t vlan_id, int on);
130static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
131 enum rte_vlan_type vlan_type,
132 uint16_t tpid_id);
133static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
134
135static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
136static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
137static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
138static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
139static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
140static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
141
142static int eth_igb_led_on(struct rte_eth_dev *dev);
143static int eth_igb_led_off(struct rte_eth_dev *dev);
144
145static void igb_intr_disable(struct rte_eth_dev *dev);
146static int igb_get_rx_buffer_size(struct e1000_hw *hw);
147static int eth_igb_rar_set(struct rte_eth_dev *dev,
148 struct rte_ether_addr *mac_addr,
149 uint32_t index, uint32_t pool);
150static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
151static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
152 struct rte_ether_addr *addr);
153
154static void igbvf_intr_disable(struct e1000_hw *hw);
155static int igbvf_dev_configure(struct rte_eth_dev *dev);
156static int igbvf_dev_start(struct rte_eth_dev *dev);
157static int igbvf_dev_stop(struct rte_eth_dev *dev);
158static int igbvf_dev_close(struct rte_eth_dev *dev);
159static int igbvf_promiscuous_enable(struct rte_eth_dev *dev);
160static int igbvf_promiscuous_disable(struct rte_eth_dev *dev);
161static int igbvf_allmulticast_enable(struct rte_eth_dev *dev);
162static int igbvf_allmulticast_disable(struct rte_eth_dev *dev);
163static int eth_igbvf_link_update(struct e1000_hw *hw);
164static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
165 struct rte_eth_stats *rte_stats);
166static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
167 struct rte_eth_xstat *xstats, unsigned n);
168static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
169 struct rte_eth_xstat_name *xstats_names,
170 unsigned limit);
171static int eth_igbvf_stats_reset(struct rte_eth_dev *dev);
172static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
173 uint16_t vlan_id, int on);
174static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
175static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
176static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
177 struct rte_ether_addr *addr);
178static int igbvf_get_reg_length(struct rte_eth_dev *dev);
179static int igbvf_get_regs(struct rte_eth_dev *dev,
180 struct rte_dev_reg_info *regs);
181
182static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
183 struct rte_eth_rss_reta_entry64 *reta_conf,
184 uint16_t reta_size);
185static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
186 struct rte_eth_rss_reta_entry64 *reta_conf,
187 uint16_t reta_size);
188
189static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
190 struct rte_eth_ntuple_filter *ntuple_filter);
191static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
192 struct rte_eth_ntuple_filter *ntuple_filter);
193static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
194 struct rte_eth_ntuple_filter *ntuple_filter);
195static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
196 struct rte_eth_ntuple_filter *ntuple_filter);
197static int eth_igb_flow_ops_get(struct rte_eth_dev *dev,
198 const struct rte_flow_ops **ops);
199static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
200static int eth_igb_get_regs(struct rte_eth_dev *dev,
201 struct rte_dev_reg_info *regs);
202static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
203static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
204 struct rte_dev_eeprom_info *eeprom);
205static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
206 struct rte_dev_eeprom_info *eeprom);
207static int eth_igb_get_module_info(struct rte_eth_dev *dev,
208 struct rte_eth_dev_module_info *modinfo);
209static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
210 struct rte_dev_eeprom_info *info);
211static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
212 struct rte_ether_addr *mc_addr_set,
213 uint32_t nb_mc_addr);
214static int igb_timesync_enable(struct rte_eth_dev *dev);
215static int igb_timesync_disable(struct rte_eth_dev *dev);
216static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
217 struct timespec *timestamp,
218 uint32_t flags);
219static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
220 struct timespec *timestamp);
221static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
222static int igb_timesync_read_time(struct rte_eth_dev *dev,
223 struct timespec *timestamp);
224static int igb_timesync_write_time(struct rte_eth_dev *dev,
225 const struct timespec *timestamp);
226static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
227 uint16_t queue_id);
228static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
229 uint16_t queue_id);
230static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
231 uint8_t queue, uint8_t msix_vector);
232static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
233 uint8_t index, uint8_t offset);
234static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
235static void eth_igbvf_interrupt_handler(void *param);
236static void igbvf_mbx_process(struct rte_eth_dev *dev);
237static int igb_filter_restore(struct rte_eth_dev *dev);
238
239
240
241
242#define UPDATE_VF_STAT(reg, last, cur) \
243{ \
244 u32 latest = E1000_READ_REG(hw, reg); \
245 cur += (latest - last) & UINT_MAX; \
246 last = latest; \
247}
248
249#define IGB_FC_PAUSE_TIME 0x0680
250#define IGB_LINK_UPDATE_CHECK_TIMEOUT 90
251#define IGB_LINK_UPDATE_CHECK_INTERVAL 100
252
253#define IGBVF_PMD_NAME "rte_igbvf_pmd"
254
255static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
256
257
258
259
260static const struct rte_pci_id pci_id_igb_map[] = {
261 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
262 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
263 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
264 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
265 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
266 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
267 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
268 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
269
270 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
271 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
272 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
273
274 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
275 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
276 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
277 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
278 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
279 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
280
281 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
282 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
283 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
284 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
285 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
286 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
287 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
288 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
289 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
290 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
291 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
292 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
293 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
294 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
295 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
296 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
297 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
298 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
299 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
300 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
301 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
302 { .vendor_id = 0, },
303};
304
305
306
307
308static const struct rte_pci_id pci_id_igbvf_map[] = {
309 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
310 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
311 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
312 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
313 { .vendor_id = 0, },
314};
315
316static const struct rte_eth_desc_lim rx_desc_lim = {
317 .nb_max = E1000_MAX_RING_DESC,
318 .nb_min = E1000_MIN_RING_DESC,
319 .nb_align = IGB_RXD_ALIGN,
320};
321
322static const struct rte_eth_desc_lim tx_desc_lim = {
323 .nb_max = E1000_MAX_RING_DESC,
324 .nb_min = E1000_MIN_RING_DESC,
325 .nb_align = IGB_RXD_ALIGN,
326 .nb_seg_max = IGB_TX_MAX_SEG,
327 .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
328};
329
330static const struct eth_dev_ops eth_igb_ops = {
331 .dev_configure = eth_igb_configure,
332 .dev_start = eth_igb_start,
333 .dev_stop = eth_igb_stop,
334 .dev_set_link_up = eth_igb_dev_set_link_up,
335 .dev_set_link_down = eth_igb_dev_set_link_down,
336 .dev_close = eth_igb_close,
337 .dev_reset = eth_igb_reset,
338 .promiscuous_enable = eth_igb_promiscuous_enable,
339 .promiscuous_disable = eth_igb_promiscuous_disable,
340 .allmulticast_enable = eth_igb_allmulticast_enable,
341 .allmulticast_disable = eth_igb_allmulticast_disable,
342 .link_update = eth_igb_link_update,
343 .stats_get = eth_igb_stats_get,
344 .xstats_get = eth_igb_xstats_get,
345 .xstats_get_by_id = eth_igb_xstats_get_by_id,
346 .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
347 .xstats_get_names = eth_igb_xstats_get_names,
348 .stats_reset = eth_igb_stats_reset,
349 .xstats_reset = eth_igb_xstats_reset,
350 .fw_version_get = eth_igb_fw_version_get,
351 .dev_infos_get = eth_igb_infos_get,
352 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
353 .mtu_set = eth_igb_mtu_set,
354 .vlan_filter_set = eth_igb_vlan_filter_set,
355 .vlan_tpid_set = eth_igb_vlan_tpid_set,
356 .vlan_offload_set = eth_igb_vlan_offload_set,
357 .rx_queue_setup = eth_igb_rx_queue_setup,
358 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
359 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
360 .rx_queue_release = eth_igb_rx_queue_release,
361 .tx_queue_setup = eth_igb_tx_queue_setup,
362 .tx_queue_release = eth_igb_tx_queue_release,
363 .tx_done_cleanup = eth_igb_tx_done_cleanup,
364 .dev_led_on = eth_igb_led_on,
365 .dev_led_off = eth_igb_led_off,
366 .flow_ctrl_get = eth_igb_flow_ctrl_get,
367 .flow_ctrl_set = eth_igb_flow_ctrl_set,
368 .mac_addr_add = eth_igb_rar_set,
369 .mac_addr_remove = eth_igb_rar_clear,
370 .mac_addr_set = eth_igb_default_mac_addr_set,
371 .reta_update = eth_igb_rss_reta_update,
372 .reta_query = eth_igb_rss_reta_query,
373 .rss_hash_update = eth_igb_rss_hash_update,
374 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
375 .flow_ops_get = eth_igb_flow_ops_get,
376 .set_mc_addr_list = eth_igb_set_mc_addr_list,
377 .rxq_info_get = igb_rxq_info_get,
378 .txq_info_get = igb_txq_info_get,
379 .timesync_enable = igb_timesync_enable,
380 .timesync_disable = igb_timesync_disable,
381 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
382 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
383 .get_reg = eth_igb_get_regs,
384 .get_eeprom_length = eth_igb_get_eeprom_length,
385 .get_eeprom = eth_igb_get_eeprom,
386 .set_eeprom = eth_igb_set_eeprom,
387 .get_module_info = eth_igb_get_module_info,
388 .get_module_eeprom = eth_igb_get_module_eeprom,
389 .timesync_adjust_time = igb_timesync_adjust_time,
390 .timesync_read_time = igb_timesync_read_time,
391 .timesync_write_time = igb_timesync_write_time,
392};
393
394
395
396
397
398static const struct eth_dev_ops igbvf_eth_dev_ops = {
399 .dev_configure = igbvf_dev_configure,
400 .dev_start = igbvf_dev_start,
401 .dev_stop = igbvf_dev_stop,
402 .dev_close = igbvf_dev_close,
403 .promiscuous_enable = igbvf_promiscuous_enable,
404 .promiscuous_disable = igbvf_promiscuous_disable,
405 .allmulticast_enable = igbvf_allmulticast_enable,
406 .allmulticast_disable = igbvf_allmulticast_disable,
407 .link_update = eth_igb_link_update,
408 .stats_get = eth_igbvf_stats_get,
409 .xstats_get = eth_igbvf_xstats_get,
410 .xstats_get_names = eth_igbvf_xstats_get_names,
411 .stats_reset = eth_igbvf_stats_reset,
412 .xstats_reset = eth_igbvf_stats_reset,
413 .vlan_filter_set = igbvf_vlan_filter_set,
414 .dev_infos_get = eth_igbvf_infos_get,
415 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
416 .rx_queue_setup = eth_igb_rx_queue_setup,
417 .rx_queue_release = eth_igb_rx_queue_release,
418 .tx_queue_setup = eth_igb_tx_queue_setup,
419 .tx_queue_release = eth_igb_tx_queue_release,
420 .tx_done_cleanup = eth_igb_tx_done_cleanup,
421 .set_mc_addr_list = eth_igb_set_mc_addr_list,
422 .rxq_info_get = igb_rxq_info_get,
423 .txq_info_get = igb_txq_info_get,
424 .mac_addr_set = igbvf_default_mac_addr_set,
425 .get_reg = igbvf_get_regs,
426};
427
428
429struct rte_igb_xstats_name_off {
430 char name[RTE_ETH_XSTATS_NAME_SIZE];
431 unsigned offset;
432};
433
434static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
435 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
436 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
437 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
438 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
439 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
440 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
441 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
442 ecol)},
443 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
444 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
445 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
446 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
447 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
448 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
449 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
450 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
451 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
452 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
453 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
454 fcruc)},
455 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
456 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
457 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
458 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
459 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
460 prc1023)},
461 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
462 prc1522)},
463 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
464 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
465 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
466 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
467 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
468 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
469 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
470 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
471 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
472 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
473 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
474 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
475 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
476 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
477 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
478 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
479 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
480 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
481 ptc1023)},
482 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
483 ptc1522)},
484 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
485 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
486 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
487 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
488 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
489 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
490 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
491
492 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
493};
494
495#define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
496 sizeof(rte_igb_stats_strings[0]))
497
498static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
499 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
500 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
501 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
502 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
503 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
504};
505
506#define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
507 sizeof(rte_igbvf_stats_strings[0]))
508
509
510static inline void
511igb_intr_enable(struct rte_eth_dev *dev)
512{
513 struct e1000_interrupt *intr =
514 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
515 struct e1000_hw *hw =
516 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
517 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
518 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
519
520 if (rte_intr_allow_others(intr_handle) &&
521 dev->data->dev_conf.intr_conf.lsc != 0) {
522 E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC);
523 }
524
525 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
526 E1000_WRITE_FLUSH(hw);
527}
528
529static void
530igb_intr_disable(struct rte_eth_dev *dev)
531{
532 struct e1000_hw *hw =
533 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
534 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
535 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
536
537 if (rte_intr_allow_others(intr_handle) &&
538 dev->data->dev_conf.intr_conf.lsc != 0) {
539 E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC);
540 }
541
542 E1000_WRITE_REG(hw, E1000_IMC, ~0);
543 E1000_WRITE_FLUSH(hw);
544}
545
546static inline void
547igbvf_intr_enable(struct rte_eth_dev *dev)
548{
549 struct e1000_hw *hw =
550 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
551
552
553 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
554 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
555 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
556 E1000_WRITE_FLUSH(hw);
557}
558
559
560static void
561igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
562{
563 uint32_t tmp = 0;
564
565
566 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
567 tmp |= E1000_VTIVAR_VALID;
568 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
569}
570
571static void
572eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
573{
574 struct e1000_hw *hw =
575 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
576
577
578 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
579}
580
581static inline int32_t
582igb_pf_reset_hw(struct e1000_hw *hw)
583{
584 uint32_t ctrl_ext;
585 int32_t status;
586
587 status = e1000_reset_hw(hw);
588
589 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
590
591 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
592 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
593 E1000_WRITE_FLUSH(hw);
594
595 return status;
596}
597
598static void
599igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
600{
601 struct e1000_hw *hw =
602 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
603
604
605 hw->vendor_id = pci_dev->id.vendor_id;
606 hw->device_id = pci_dev->id.device_id;
607 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
608 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
609
610 e1000_set_mac_type(hw);
611
612
613}
614
615static int
616igb_reset_swfw_lock(struct e1000_hw *hw)
617{
618 int ret_val;
619
620
621
622
623
624 ret_val = e1000_init_mac_params(hw);
625 if (ret_val)
626 return ret_val;
627
628
629
630
631
632
633 if (e1000_get_hw_semaphore_generic(hw) < 0) {
634 PMD_DRV_LOG(DEBUG, "SMBI lock released");
635 }
636 e1000_put_hw_semaphore_generic(hw);
637
638 if (hw->mac.ops.acquire_swfw_sync != NULL) {
639 uint16_t mask;
640
641
642
643
644
645
646 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
647 if (hw->bus.func > E1000_FUNC_1)
648 mask <<= 2;
649 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
650 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
651 hw->bus.func);
652 }
653 hw->mac.ops.release_swfw_sync(hw, mask);
654
655
656
657
658
659
660
661 mask = E1000_SWFW_EEP_SM;
662 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
663 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
664 }
665 hw->mac.ops.release_swfw_sync(hw, mask);
666 }
667
668 return E1000_SUCCESS;
669}
670
671
672static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
673{
674 struct e1000_filter_info *filter_info =
675 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
676 struct e1000_5tuple_filter *p_5tuple;
677 struct e1000_2tuple_filter *p_2tuple;
678
679 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
680 TAILQ_REMOVE(&filter_info->fivetuple_list,
681 p_5tuple, entries);
682 rte_free(p_5tuple);
683 }
684 filter_info->fivetuple_mask = 0;
685 while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
686 TAILQ_REMOVE(&filter_info->twotuple_list,
687 p_2tuple, entries);
688 rte_free(p_2tuple);
689 }
690 filter_info->twotuple_mask = 0;
691
692 return 0;
693}
694
695
696static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
697{
698 struct e1000_filter_info *filter_info =
699 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
700 struct e1000_flex_filter *p_flex;
701
702 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
703 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
704 rte_free(p_flex);
705 }
706 filter_info->flex_mask = 0;
707
708 return 0;
709}
710
711static int
712eth_igb_dev_init(struct rte_eth_dev *eth_dev)
713{
714 int error = 0;
715 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
716 struct e1000_hw *hw =
717 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
718 struct e1000_vfta * shadow_vfta =
719 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
720 struct e1000_filter_info *filter_info =
721 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
722 struct e1000_adapter *adapter =
723 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
724
725 uint32_t ctrl_ext;
726
727 eth_dev->dev_ops = ð_igb_ops;
728 eth_dev->rx_queue_count = eth_igb_rx_queue_count;
729 eth_dev->rx_descriptor_done = eth_igb_rx_descriptor_done;
730 eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
731 eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
732 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
733 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
734 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
735
736
737
738
739 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
740 if (eth_dev->data->scattered_rx)
741 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
742 return 0;
743 }
744
745 rte_eth_copy_pci_info(eth_dev, pci_dev);
746 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
747
748 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
749
750 igb_identify_hardware(eth_dev, pci_dev);
751 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
752 error = -EIO;
753 goto err_late;
754 }
755
756 e1000_get_bus_info(hw);
757
758
759 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
760 error = -EIO;
761 goto err_late;
762 }
763
764
765 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
766 error = -EIO;
767 goto err_late;
768 }
769
770 hw->mac.autoneg = 1;
771 hw->phy.autoneg_wait_to_complete = 0;
772 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
773
774
775 if (hw->phy.media_type == e1000_media_type_copper) {
776 hw->phy.mdix = 0;
777 hw->phy.disable_polarity_correction = 0;
778 hw->phy.ms_type = e1000_ms_hw_default;
779 }
780
781
782
783
784
785 igb_pf_reset_hw(hw);
786
787
788 if (e1000_validate_nvm_checksum(hw) < 0) {
789
790
791
792
793
794 if (e1000_validate_nvm_checksum(hw) < 0) {
795 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
796 error = -EIO;
797 goto err_late;
798 }
799 }
800
801
802 if (e1000_read_mac_addr(hw) != 0) {
803 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
804 error = -EIO;
805 goto err_late;
806 }
807
808
809 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
810 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
811 if (eth_dev->data->mac_addrs == NULL) {
812 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
813 "store MAC addresses",
814 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
815 error = -ENOMEM;
816 goto err_late;
817 }
818
819
820 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
821 ð_dev->data->mac_addrs[0]);
822
823
824 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
825
826
827 if (igb_hardware_init(hw) != 0) {
828 PMD_INIT_LOG(ERR, "Hardware initialization failed");
829 rte_free(eth_dev->data->mac_addrs);
830 eth_dev->data->mac_addrs = NULL;
831 error = -ENODEV;
832 goto err_late;
833 }
834 hw->mac.get_link_status = 1;
835 adapter->stopped = 0;
836
837
838 if (e1000_check_reset_block(hw) < 0) {
839 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
840 "SOL/IDER session");
841 }
842
843
844 igb_pf_host_init(eth_dev);
845
846 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
847
848 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
849 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
850 E1000_WRITE_FLUSH(hw);
851
852 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
853 eth_dev->data->port_id, pci_dev->id.vendor_id,
854 pci_dev->id.device_id);
855
856 rte_intr_callback_register(&pci_dev->intr_handle,
857 eth_igb_interrupt_handler,
858 (void *)eth_dev);
859
860
861 rte_intr_enable(&pci_dev->intr_handle);
862
863
864 igb_intr_enable(eth_dev);
865
866 eth_igb_dev_set_link_down(eth_dev);
867
868
869 memset(filter_info, 0,
870 sizeof(struct e1000_filter_info));
871
872 TAILQ_INIT(&filter_info->flex_list);
873 TAILQ_INIT(&filter_info->twotuple_list);
874 TAILQ_INIT(&filter_info->fivetuple_list);
875
876 TAILQ_INIT(&igb_filter_ntuple_list);
877 TAILQ_INIT(&igb_filter_ethertype_list);
878 TAILQ_INIT(&igb_filter_syn_list);
879 TAILQ_INIT(&igb_filter_flex_list);
880 TAILQ_INIT(&igb_filter_rss_list);
881 TAILQ_INIT(&igb_flow_list);
882
883 return 0;
884
885err_late:
886 igb_hw_control_release(hw);
887
888 return error;
889}
890
891static int
892eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
893{
894 PMD_INIT_FUNC_TRACE();
895
896 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
897 return 0;
898
899 eth_igb_close(eth_dev);
900
901 return 0;
902}
903
904
905
906
907static int
908eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
909{
910 struct rte_pci_device *pci_dev;
911 struct rte_intr_handle *intr_handle;
912 struct e1000_adapter *adapter =
913 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
914 struct e1000_hw *hw =
915 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
916 int diag;
917 struct rte_ether_addr *perm_addr =
918 (struct rte_ether_addr *)hw->mac.perm_addr;
919
920 PMD_INIT_FUNC_TRACE();
921
922 eth_dev->dev_ops = &igbvf_eth_dev_ops;
923 eth_dev->rx_descriptor_done = eth_igb_rx_descriptor_done;
924 eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
925 eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
926 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
927 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
928 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
929
930
931
932
933 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
934 if (eth_dev->data->scattered_rx)
935 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
936 return 0;
937 }
938
939 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
940 rte_eth_copy_pci_info(eth_dev, pci_dev);
941 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
942
943 hw->device_id = pci_dev->id.device_id;
944 hw->vendor_id = pci_dev->id.vendor_id;
945 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
946 adapter->stopped = 0;
947
948
949 diag = e1000_setup_init_funcs(hw, TRUE);
950 if (diag != 0) {
951 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
952 diag);
953 return -EIO;
954 }
955
956
957 hw->mbx.ops.init_params(hw);
958
959
960 igbvf_intr_disable(hw);
961
962 diag = hw->mac.ops.reset_hw(hw);
963
964
965 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", RTE_ETHER_ADDR_LEN *
966 hw->mac.rar_entry_count, 0);
967 if (eth_dev->data->mac_addrs == NULL) {
968 PMD_INIT_LOG(ERR,
969 "Failed to allocate %d bytes needed to store MAC "
970 "addresses",
971 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
972 return -ENOMEM;
973 }
974
975
976 if (rte_is_zero_ether_addr(perm_addr)) {
977 rte_eth_random_addr(perm_addr->addr_bytes);
978 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
979 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
980 "%02x:%02x:%02x:%02x:%02x:%02x",
981 perm_addr->addr_bytes[0],
982 perm_addr->addr_bytes[1],
983 perm_addr->addr_bytes[2],
984 perm_addr->addr_bytes[3],
985 perm_addr->addr_bytes[4],
986 perm_addr->addr_bytes[5]);
987 }
988
989 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
990 if (diag) {
991 rte_free(eth_dev->data->mac_addrs);
992 eth_dev->data->mac_addrs = NULL;
993 return diag;
994 }
995
996 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
997 ð_dev->data->mac_addrs[0]);
998
999 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1000 "mac.type=%s",
1001 eth_dev->data->port_id, pci_dev->id.vendor_id,
1002 pci_dev->id.device_id, "igb_mac_82576_vf");
1003
1004 intr_handle = &pci_dev->intr_handle;
1005 rte_intr_callback_register(intr_handle,
1006 eth_igbvf_interrupt_handler, eth_dev);
1007
1008 return 0;
1009}
1010
1011static int
1012eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1013{
1014 PMD_INIT_FUNC_TRACE();
1015
1016 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1017 return 0;
1018
1019 igbvf_dev_close(eth_dev);
1020
1021 return 0;
1022}
1023
1024static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1025 struct rte_pci_device *pci_dev)
1026{
1027 return rte_eth_dev_pci_generic_probe(pci_dev,
1028 sizeof(struct e1000_adapter), eth_igb_dev_init);
1029}
1030
1031static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1032{
1033 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1034}
1035
1036static struct rte_pci_driver rte_igb_pmd = {
1037 .id_table = pci_id_igb_map,
1038 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1039 .probe = eth_igb_pci_probe,
1040 .remove = eth_igb_pci_remove,
1041};
1042
1043
1044static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1045 struct rte_pci_device *pci_dev)
1046{
1047 return rte_eth_dev_pci_generic_probe(pci_dev,
1048 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1049}
1050
1051static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1052{
1053 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1054}
1055
1056
1057
1058
1059static struct rte_pci_driver rte_igbvf_pmd = {
1060 .id_table = pci_id_igbvf_map,
1061 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1062 .probe = eth_igbvf_pci_probe,
1063 .remove = eth_igbvf_pci_remove,
1064};
1065
1066static void
1067igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1068{
1069 struct e1000_hw *hw =
1070 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1071
1072 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1073 rctl |= E1000_RCTL_VFE;
1074 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1075}
1076
1077static int
1078igb_check_mq_mode(struct rte_eth_dev *dev)
1079{
1080 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1081 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1082 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1083 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1084
1085 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1086 tx_mq_mode == ETH_MQ_TX_DCB ||
1087 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1088 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1089 return -EINVAL;
1090 }
1091 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1092
1093
1094
1095
1096
1097 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1098 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1099 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1100 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1101 } else {
1102
1103
1104
1105 PMD_INIT_LOG(ERR, "SRIOV is active,"
1106 " wrong mq_mode rx %d.",
1107 rx_mq_mode);
1108 return -EINVAL;
1109 }
1110
1111 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1112
1113 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1114 " TX mode %d is not supported. "
1115 " Driver will behave as %d mode.",
1116 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1117 }
1118
1119
1120 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1121 PMD_INIT_LOG(ERR, "SRIOV is active,"
1122 " only support one queue on VFs.");
1123 return -EINVAL;
1124 }
1125 } else {
1126
1127
1128
1129 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1130 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1131 rx_mq_mode != ETH_MQ_RX_RSS) {
1132
1133 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1134 rx_mq_mode);
1135 return -EINVAL;
1136 }
1137
1138 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1139 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1140 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1141 " Due to txmode is meaningless in this"
1142 " driver, just ignore.",
1143 tx_mq_mode);
1144 }
1145 }
1146 return 0;
1147}
1148
1149static int
1150eth_igb_configure(struct rte_eth_dev *dev)
1151{
1152 struct e1000_interrupt *intr =
1153 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1154 int ret;
1155
1156 PMD_INIT_FUNC_TRACE();
1157
1158 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1159 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1160
1161
1162 ret = igb_check_mq_mode(dev);
1163 if (ret != 0) {
1164 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1165 ret);
1166 return ret;
1167 }
1168
1169 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1170 PMD_INIT_FUNC_TRACE();
1171
1172 return 0;
1173}
1174
1175static void
1176eth_igb_rxtx_control(struct rte_eth_dev *dev,
1177 bool enable)
1178{
1179 struct e1000_hw *hw =
1180 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1181 uint32_t tctl, rctl;
1182
1183 tctl = E1000_READ_REG(hw, E1000_TCTL);
1184 rctl = E1000_READ_REG(hw, E1000_RCTL);
1185
1186 if (enable) {
1187
1188 tctl |= E1000_TCTL_EN;
1189 rctl |= E1000_RCTL_EN;
1190 } else {
1191
1192 tctl &= ~E1000_TCTL_EN;
1193 rctl &= ~E1000_RCTL_EN;
1194 }
1195 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1196 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1197 E1000_WRITE_FLUSH(hw);
1198}
1199
1200static int
1201eth_igb_start(struct rte_eth_dev *dev)
1202{
1203 struct e1000_hw *hw =
1204 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1205 struct e1000_adapter *adapter =
1206 E1000_DEV_PRIVATE(dev->data->dev_private);
1207 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1208 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1209 int ret, mask;
1210 uint32_t intr_vector = 0;
1211 uint32_t ctrl_ext;
1212 uint32_t *speeds;
1213 int num_speeds;
1214 bool autoneg;
1215
1216 PMD_INIT_FUNC_TRACE();
1217
1218
1219 rte_intr_disable(intr_handle);
1220
1221
1222 eth_igb_dev_set_link_up(dev);
1223
1224
1225
1226
1227
1228
1229 if (hw->mac.type == e1000_82575) {
1230 uint32_t pba;
1231
1232 pba = E1000_PBA_32K;
1233 E1000_WRITE_REG(hw, E1000_PBA, pba);
1234 }
1235
1236
1237 e1000_rar_set(hw, hw->mac.addr, 0);
1238
1239
1240 if (igb_hardware_init(hw)) {
1241 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1242 return -EIO;
1243 }
1244 adapter->stopped = 0;
1245
1246 E1000_WRITE_REG(hw, E1000_VET,
1247 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1248
1249 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1250
1251 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1252 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1253 E1000_WRITE_FLUSH(hw);
1254
1255
1256 igb_pf_host_configure(dev);
1257
1258
1259 if ((rte_intr_cap_multiple(intr_handle) ||
1260 !RTE_ETH_DEV_SRIOV(dev).active) &&
1261 dev->data->dev_conf.intr_conf.rxq != 0) {
1262 intr_vector = dev->data->nb_rx_queues;
1263 if (rte_intr_efd_enable(intr_handle, intr_vector))
1264 return -1;
1265 }
1266
1267 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1268 intr_handle->intr_vec =
1269 rte_zmalloc("intr_vec",
1270 dev->data->nb_rx_queues * sizeof(int), 0);
1271 if (intr_handle->intr_vec == NULL) {
1272 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1273 " intr_vec", dev->data->nb_rx_queues);
1274 return -ENOMEM;
1275 }
1276 }
1277
1278
1279 eth_igb_configure_msix_intr(dev);
1280
1281
1282 igb_init_manageability(hw);
1283
1284 eth_igb_tx_init(dev);
1285
1286
1287 ret = eth_igb_rx_init(dev);
1288 if (ret) {
1289 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1290 igb_dev_clear_queues(dev);
1291 return ret;
1292 }
1293
1294 e1000_clear_hw_cntrs_base_generic(hw);
1295
1296
1297
1298
1299 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1300 ETH_VLAN_EXTEND_MASK;
1301 ret = eth_igb_vlan_offload_set(dev, mask);
1302 if (ret) {
1303 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1304 igb_dev_clear_queues(dev);
1305 return ret;
1306 }
1307
1308 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1309
1310 igb_vmdq_vlan_hw_filter_enable(dev);
1311 }
1312
1313 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1314 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1315 (hw->mac.type == e1000_i211)) {
1316
1317 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1318 }
1319
1320
1321 speeds = &dev->data->dev_conf.link_speeds;
1322 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1323 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1324 hw->mac.autoneg = 1;
1325 } else {
1326 num_speeds = 0;
1327 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1328
1329
1330 hw->phy.autoneg_advertised = 0;
1331
1332 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1333 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1334 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1335 num_speeds = -1;
1336 goto error_invalid_config;
1337 }
1338 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1339 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1340 num_speeds++;
1341 }
1342 if (*speeds & ETH_LINK_SPEED_10M) {
1343 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1344 num_speeds++;
1345 }
1346 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1347 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1348 num_speeds++;
1349 }
1350 if (*speeds & ETH_LINK_SPEED_100M) {
1351 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1352 num_speeds++;
1353 }
1354 if (*speeds & ETH_LINK_SPEED_1G) {
1355 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1356 num_speeds++;
1357 }
1358 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1359 goto error_invalid_config;
1360
1361
1362
1363
1364 if (!autoneg) {
1365 hw->mac.autoneg = 0;
1366 hw->mac.forced_speed_duplex =
1367 hw->phy.autoneg_advertised;
1368 } else {
1369 hw->mac.autoneg = 1;
1370 }
1371 }
1372
1373 e1000_setup_link(hw);
1374
1375 if (rte_intr_allow_others(intr_handle)) {
1376
1377 if (dev->data->dev_conf.intr_conf.lsc != 0)
1378 eth_igb_lsc_interrupt_setup(dev, TRUE);
1379 else
1380 eth_igb_lsc_interrupt_setup(dev, FALSE);
1381 } else {
1382 rte_intr_callback_unregister(intr_handle,
1383 eth_igb_interrupt_handler,
1384 (void *)dev);
1385 if (dev->data->dev_conf.intr_conf.lsc != 0)
1386 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1387 " no intr multiplex");
1388 }
1389
1390
1391 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1392 rte_intr_dp_is_en(intr_handle))
1393 eth_igb_rxq_interrupt_setup(dev);
1394
1395
1396 rte_intr_enable(intr_handle);
1397
1398
1399 igb_intr_enable(dev);
1400
1401
1402 igb_filter_restore(dev);
1403
1404 eth_igb_rxtx_control(dev, true);
1405 eth_igb_link_update(dev, 0);
1406
1407 PMD_INIT_LOG(DEBUG, "<<");
1408
1409 return 0;
1410
1411error_invalid_config:
1412 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1413 dev->data->dev_conf.link_speeds, dev->data->port_id);
1414 igb_dev_clear_queues(dev);
1415 return -EINVAL;
1416}
1417
1418
1419
1420
1421
1422
1423
1424static int
1425eth_igb_stop(struct rte_eth_dev *dev)
1426{
1427 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1428 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1429 struct rte_eth_link link;
1430 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1431 struct e1000_adapter *adapter =
1432 E1000_DEV_PRIVATE(dev->data->dev_private);
1433
1434 if (adapter->stopped)
1435 return 0;
1436
1437 eth_igb_rxtx_control(dev, false);
1438
1439 igb_intr_disable(dev);
1440
1441
1442 rte_intr_disable(intr_handle);
1443
1444 igb_pf_reset_hw(hw);
1445 E1000_WRITE_REG(hw, E1000_WUC, 0);
1446
1447
1448 if (hw->mac.type >= e1000_82580 &&
1449 (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1450 uint32_t phpm_reg;
1451
1452 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1453 phpm_reg |= E1000_82580_PM_GO_LINKD;
1454 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1455 }
1456
1457
1458 eth_igb_dev_set_link_down(dev);
1459
1460 igb_dev_clear_queues(dev);
1461
1462
1463 memset(&link, 0, sizeof(link));
1464 rte_eth_linkstatus_set(dev, &link);
1465
1466 if (!rte_intr_allow_others(intr_handle))
1467
1468 rte_intr_callback_register(intr_handle,
1469 eth_igb_interrupt_handler,
1470 (void *)dev);
1471
1472
1473 rte_intr_efd_disable(intr_handle);
1474 if (intr_handle->intr_vec != NULL) {
1475 rte_free(intr_handle->intr_vec);
1476 intr_handle->intr_vec = NULL;
1477 }
1478
1479 adapter->stopped = true;
1480 dev->data->dev_started = 0;
1481
1482 return 0;
1483}
1484
1485static int
1486eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1487{
1488 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1489
1490 if (hw->phy.media_type == e1000_media_type_copper)
1491 e1000_power_up_phy(hw);
1492 else
1493 e1000_power_up_fiber_serdes_link(hw);
1494
1495 return 0;
1496}
1497
1498static int
1499eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1500{
1501 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1502
1503 if (hw->phy.media_type == e1000_media_type_copper)
1504 e1000_power_down_phy(hw);
1505 else
1506 e1000_shutdown_fiber_serdes_link(hw);
1507
1508 return 0;
1509}
1510
1511static int
1512eth_igb_close(struct rte_eth_dev *dev)
1513{
1514 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1515 struct rte_eth_link link;
1516 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1517 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1518 struct e1000_filter_info *filter_info =
1519 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1520 int ret;
1521
1522 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1523 return 0;
1524
1525 ret = eth_igb_stop(dev);
1526
1527 e1000_phy_hw_reset(hw);
1528 igb_release_manageability(hw);
1529 igb_hw_control_release(hw);
1530
1531
1532 if (hw->mac.type >= e1000_82580 &&
1533 (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1534 uint32_t phpm_reg;
1535
1536 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1537 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1538 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1539 }
1540
1541 igb_dev_free_queues(dev);
1542
1543 if (intr_handle->intr_vec) {
1544 rte_free(intr_handle->intr_vec);
1545 intr_handle->intr_vec = NULL;
1546 }
1547
1548 memset(&link, 0, sizeof(link));
1549 rte_eth_linkstatus_set(dev, &link);
1550
1551
1552 igb_reset_swfw_lock(hw);
1553
1554
1555 igb_pf_host_uninit(dev);
1556
1557 rte_intr_callback_unregister(intr_handle,
1558 eth_igb_interrupt_handler, dev);
1559
1560
1561 filter_info->syn_info = 0;
1562
1563
1564 filter_info->ethertype_mask = 0;
1565 memset(filter_info->ethertype_filters, 0,
1566 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1567
1568
1569 memset(&filter_info->rss_info, 0,
1570 sizeof(struct igb_rte_flow_rss_conf));
1571
1572
1573 igb_ntuple_filter_uninit(dev);
1574
1575
1576 igb_flex_filter_uninit(dev);
1577
1578
1579 igb_filterlist_flush(dev);
1580
1581 return ret;
1582}
1583
1584
1585
1586
1587static int
1588eth_igb_reset(struct rte_eth_dev *dev)
1589{
1590 int ret;
1591
1592
1593
1594
1595
1596
1597
1598 if (dev->data->sriov.active)
1599 return -ENOTSUP;
1600
1601 ret = eth_igb_dev_uninit(dev);
1602 if (ret)
1603 return ret;
1604
1605 ret = eth_igb_dev_init(dev);
1606
1607 return ret;
1608}
1609
1610
1611static int
1612igb_get_rx_buffer_size(struct e1000_hw *hw)
1613{
1614 uint32_t rx_buf_size;
1615 if (hw->mac.type == e1000_82576) {
1616 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1617 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1618
1619 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1620 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1621 rx_buf_size = (rx_buf_size << 10);
1622 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1623 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1624 } else {
1625 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1626 }
1627
1628 return rx_buf_size;
1629}
1630
1631
1632
1633
1634
1635
1636static int
1637igb_hardware_init(struct e1000_hw *hw)
1638{
1639 uint32_t rx_buf_size;
1640 int diag;
1641
1642
1643 igb_hw_control_acquire(hw);
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659 rx_buf_size = igb_get_rx_buffer_size(hw);
1660
1661 hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);
1662 hw->fc.low_water = hw->fc.high_water - 1500;
1663 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1664 hw->fc.send_xon = 1;
1665
1666
1667 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1668 hw->fc.requested_mode = igb_fc_setting;
1669 else
1670 hw->fc.requested_mode = e1000_fc_none;
1671
1672
1673 igb_pf_reset_hw(hw);
1674 E1000_WRITE_REG(hw, E1000_WUC, 0);
1675
1676 diag = e1000_init_hw(hw);
1677 if (diag < 0)
1678 return diag;
1679
1680 E1000_WRITE_REG(hw, E1000_VET,
1681 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1682 e1000_get_phy_info(hw);
1683 e1000_check_for_link(hw);
1684
1685 return 0;
1686}
1687
1688
1689static void
1690igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1691{
1692 int pause_frames;
1693
1694 uint64_t old_gprc = stats->gprc;
1695 uint64_t old_gptc = stats->gptc;
1696 uint64_t old_tpr = stats->tpr;
1697 uint64_t old_tpt = stats->tpt;
1698 uint64_t old_rpthc = stats->rpthc;
1699 uint64_t old_hgptc = stats->hgptc;
1700
1701 if(hw->phy.media_type == e1000_media_type_copper ||
1702 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1703 stats->symerrs +=
1704 E1000_READ_REG(hw,E1000_SYMERRS);
1705 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1706 }
1707
1708 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1709 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1710 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1711 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1712
1713 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1714 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1715 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1716 stats->dc += E1000_READ_REG(hw, E1000_DC);
1717 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1718 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1719 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1720
1721
1722
1723
1724 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1725 stats->xoffrxc += pause_frames;
1726 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1727 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1728 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1729 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1730 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1731 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1732 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1733 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1734 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1735 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1736 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1737 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1738
1739
1740
1741
1742
1743 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1744 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1745 stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN;
1746 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1747 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1748 stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN;
1749
1750 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1751 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1752 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1753 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1754 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1755
1756 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1757 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1758
1759 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1760 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1761 stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
1762 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1763 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1764 stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN;
1765
1766 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1767 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1768 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1769 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1770 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1771 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1772 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1773 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1774
1775
1776
1777 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1778 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1779 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1780 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1781 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1782 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1783 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1784 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1785 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1786
1787
1788
1789 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1790 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1791 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1792 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1793 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1794 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1795 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1796 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1797 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1798 stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN;
1799 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1800 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1801 stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN;
1802 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1803 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1804 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1805
1806 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1807 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1808 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1809 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1810 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1811 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1812}
1813
1814static int
1815eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1816{
1817 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1818 struct e1000_hw_stats *stats =
1819 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1820
1821 igb_read_stats_registers(hw, stats);
1822
1823 if (rte_stats == NULL)
1824 return -EINVAL;
1825
1826
1827 rte_stats->imissed = stats->mpc;
1828 rte_stats->ierrors = stats->crcerrs + stats->rlec +
1829 stats->rxerrc + stats->algnerrc + stats->cexterr;
1830
1831
1832 rte_stats->oerrors = stats->ecol + stats->latecol;
1833
1834 rte_stats->ipackets = stats->gprc;
1835 rte_stats->opackets = stats->gptc;
1836 rte_stats->ibytes = stats->gorc;
1837 rte_stats->obytes = stats->gotc;
1838 return 0;
1839}
1840
1841static int
1842eth_igb_stats_reset(struct rte_eth_dev *dev)
1843{
1844 struct e1000_hw_stats *hw_stats =
1845 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1846
1847
1848 eth_igb_stats_get(dev, NULL);
1849
1850
1851 memset(hw_stats, 0, sizeof(*hw_stats));
1852
1853 return 0;
1854}
1855
1856static int
1857eth_igb_xstats_reset(struct rte_eth_dev *dev)
1858{
1859 struct e1000_hw_stats *stats =
1860 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1861
1862
1863 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1864
1865
1866 memset(stats, 0, sizeof(*stats));
1867
1868 return 0;
1869}
1870
1871static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1872 struct rte_eth_xstat_name *xstats_names,
1873 __rte_unused unsigned int size)
1874{
1875 unsigned i;
1876
1877 if (xstats_names == NULL)
1878 return IGB_NB_XSTATS;
1879
1880
1881
1882 for (i = 0; i < IGB_NB_XSTATS; i++) {
1883 strlcpy(xstats_names[i].name, rte_igb_stats_strings[i].name,
1884 sizeof(xstats_names[i].name));
1885 }
1886
1887 return IGB_NB_XSTATS;
1888}
1889
1890static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1891 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1892 unsigned int limit)
1893{
1894 unsigned int i;
1895
1896 if (!ids) {
1897 if (xstats_names == NULL)
1898 return IGB_NB_XSTATS;
1899
1900 for (i = 0; i < IGB_NB_XSTATS; i++)
1901 strlcpy(xstats_names[i].name,
1902 rte_igb_stats_strings[i].name,
1903 sizeof(xstats_names[i].name));
1904
1905 return IGB_NB_XSTATS;
1906
1907 } else {
1908 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1909
1910 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1911 IGB_NB_XSTATS);
1912
1913 for (i = 0; i < limit; i++) {
1914 if (ids[i] >= IGB_NB_XSTATS) {
1915 PMD_INIT_LOG(ERR, "id value isn't valid");
1916 return -1;
1917 }
1918 strcpy(xstats_names[i].name,
1919 xstats_names_copy[ids[i]].name);
1920 }
1921 return limit;
1922 }
1923}
1924
1925static int
1926eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1927 unsigned n)
1928{
1929 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1930 struct e1000_hw_stats *hw_stats =
1931 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1932 unsigned i;
1933
1934 if (n < IGB_NB_XSTATS)
1935 return IGB_NB_XSTATS;
1936
1937 igb_read_stats_registers(hw, hw_stats);
1938
1939
1940
1941
1942 if (!xstats)
1943 return 0;
1944
1945
1946 for (i = 0; i < IGB_NB_XSTATS; i++) {
1947 xstats[i].id = i;
1948 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1949 rte_igb_stats_strings[i].offset);
1950 }
1951
1952 return IGB_NB_XSTATS;
1953}
1954
1955static int
1956eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1957 uint64_t *values, unsigned int n)
1958{
1959 unsigned int i;
1960
1961 if (!ids) {
1962 struct e1000_hw *hw =
1963 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1964 struct e1000_hw_stats *hw_stats =
1965 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1966
1967 if (n < IGB_NB_XSTATS)
1968 return IGB_NB_XSTATS;
1969
1970 igb_read_stats_registers(hw, hw_stats);
1971
1972
1973
1974
1975 if (!values)
1976 return 0;
1977
1978
1979 for (i = 0; i < IGB_NB_XSTATS; i++)
1980 values[i] = *(uint64_t *)(((char *)hw_stats) +
1981 rte_igb_stats_strings[i].offset);
1982
1983 return IGB_NB_XSTATS;
1984
1985 } else {
1986 uint64_t values_copy[IGB_NB_XSTATS];
1987
1988 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
1989 IGB_NB_XSTATS);
1990
1991 for (i = 0; i < n; i++) {
1992 if (ids[i] >= IGB_NB_XSTATS) {
1993 PMD_INIT_LOG(ERR, "id value isn't valid");
1994 return -1;
1995 }
1996 values[i] = values_copy[ids[i]];
1997 }
1998 return n;
1999 }
2000}
2001
2002static void
2003igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2004{
2005
2006 UPDATE_VF_STAT(E1000_VFGPRC,
2007 hw_stats->last_gprc, hw_stats->gprc);
2008
2009
2010 UPDATE_VF_STAT(E1000_VFGORC,
2011 hw_stats->last_gorc, hw_stats->gorc);
2012
2013
2014 UPDATE_VF_STAT(E1000_VFGPTC,
2015 hw_stats->last_gptc, hw_stats->gptc);
2016
2017
2018 UPDATE_VF_STAT(E1000_VFGOTC,
2019 hw_stats->last_gotc, hw_stats->gotc);
2020
2021
2022 UPDATE_VF_STAT(E1000_VFMPRC,
2023 hw_stats->last_mprc, hw_stats->mprc);
2024
2025
2026 UPDATE_VF_STAT(E1000_VFGPRLBC,
2027 hw_stats->last_gprlbc, hw_stats->gprlbc);
2028
2029
2030 UPDATE_VF_STAT(E1000_VFGORLBC,
2031 hw_stats->last_gorlbc, hw_stats->gorlbc);
2032
2033
2034 UPDATE_VF_STAT(E1000_VFGPTLBC,
2035 hw_stats->last_gptlbc, hw_stats->gptlbc);
2036
2037
2038 UPDATE_VF_STAT(E1000_VFGOTLBC,
2039 hw_stats->last_gotlbc, hw_stats->gotlbc);
2040}
2041
2042static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2043 struct rte_eth_xstat_name *xstats_names,
2044 __rte_unused unsigned limit)
2045{
2046 unsigned i;
2047
2048 if (xstats_names != NULL)
2049 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2050 strlcpy(xstats_names[i].name,
2051 rte_igbvf_stats_strings[i].name,
2052 sizeof(xstats_names[i].name));
2053 }
2054 return IGBVF_NB_XSTATS;
2055}
2056
2057static int
2058eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2059 unsigned n)
2060{
2061 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2062 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2063 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2064 unsigned i;
2065
2066 if (n < IGBVF_NB_XSTATS)
2067 return IGBVF_NB_XSTATS;
2068
2069 igbvf_read_stats_registers(hw, hw_stats);
2070
2071 if (!xstats)
2072 return 0;
2073
2074 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2075 xstats[i].id = i;
2076 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2077 rte_igbvf_stats_strings[i].offset);
2078 }
2079
2080 return IGBVF_NB_XSTATS;
2081}
2082
2083static int
2084eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2085{
2086 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2087 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2088 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2089
2090 igbvf_read_stats_registers(hw, hw_stats);
2091
2092 if (rte_stats == NULL)
2093 return -EINVAL;
2094
2095 rte_stats->ipackets = hw_stats->gprc;
2096 rte_stats->ibytes = hw_stats->gorc;
2097 rte_stats->opackets = hw_stats->gptc;
2098 rte_stats->obytes = hw_stats->gotc;
2099 return 0;
2100}
2101
2102static int
2103eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2104{
2105 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2106 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2107
2108
2109 eth_igbvf_stats_get(dev, NULL);
2110
2111
2112 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2113 offsetof(struct e1000_vf_stats, gprc));
2114
2115 return 0;
2116}
2117
2118static int
2119eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2120 size_t fw_size)
2121{
2122 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2123 struct e1000_fw_version fw;
2124 int ret;
2125
2126 e1000_get_fw_version(hw, &fw);
2127
2128 switch (hw->mac.type) {
2129 case e1000_i210:
2130 case e1000_i211:
2131 if (!(e1000_get_flash_presence_i210(hw))) {
2132 ret = snprintf(fw_version, fw_size,
2133 "%2d.%2d-%d",
2134 fw.invm_major, fw.invm_minor,
2135 fw.invm_img_type);
2136 break;
2137 }
2138
2139 default:
2140
2141 if (fw.or_valid) {
2142 ret = snprintf(fw_version, fw_size,
2143 "%d.%d, 0x%08x, %d.%d.%d",
2144 fw.eep_major, fw.eep_minor, fw.etrack_id,
2145 fw.or_major, fw.or_build, fw.or_patch);
2146
2147 } else {
2148 if (fw.etrack_id != 0X0000) {
2149 ret = snprintf(fw_version, fw_size,
2150 "%d.%d, 0x%08x",
2151 fw.eep_major, fw.eep_minor,
2152 fw.etrack_id);
2153 } else {
2154 ret = snprintf(fw_version, fw_size,
2155 "%d.%d.%d",
2156 fw.eep_major, fw.eep_minor,
2157 fw.eep_build);
2158 }
2159 }
2160 break;
2161 }
2162 if (ret < 0)
2163 return -EINVAL;
2164
2165 ret += 1;
2166 if (fw_size < (size_t)ret)
2167 return ret;
2168 else
2169 return 0;
2170}
2171
2172static int
2173eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2174{
2175 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2176
2177 dev_info->min_rx_bufsize = 256;
2178 dev_info->max_rx_pktlen = 0x3FFF;
2179 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2180 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2181 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2182 dev_info->rx_queue_offload_capa;
2183 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2184 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2185 dev_info->tx_queue_offload_capa;
2186
2187 switch (hw->mac.type) {
2188 case e1000_82575:
2189 dev_info->max_rx_queues = 4;
2190 dev_info->max_tx_queues = 4;
2191 dev_info->max_vmdq_pools = 0;
2192 break;
2193
2194 case e1000_82576:
2195 dev_info->max_rx_queues = 16;
2196 dev_info->max_tx_queues = 16;
2197 dev_info->max_vmdq_pools = ETH_8_POOLS;
2198 dev_info->vmdq_queue_num = 16;
2199 break;
2200
2201 case e1000_82580:
2202 dev_info->max_rx_queues = 8;
2203 dev_info->max_tx_queues = 8;
2204 dev_info->max_vmdq_pools = ETH_8_POOLS;
2205 dev_info->vmdq_queue_num = 8;
2206 break;
2207
2208 case e1000_i350:
2209 dev_info->max_rx_queues = 8;
2210 dev_info->max_tx_queues = 8;
2211 dev_info->max_vmdq_pools = ETH_8_POOLS;
2212 dev_info->vmdq_queue_num = 8;
2213 break;
2214
2215 case e1000_i354:
2216 dev_info->max_rx_queues = 8;
2217 dev_info->max_tx_queues = 8;
2218 break;
2219
2220 case e1000_i210:
2221 dev_info->max_rx_queues = 4;
2222 dev_info->max_tx_queues = 4;
2223 dev_info->max_vmdq_pools = 0;
2224 break;
2225
2226 case e1000_i211:
2227 dev_info->max_rx_queues = 2;
2228 dev_info->max_tx_queues = 2;
2229 dev_info->max_vmdq_pools = 0;
2230 break;
2231
2232 default:
2233
2234 return -EINVAL;
2235 }
2236 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2237 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2238 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2239
2240 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2241 .rx_thresh = {
2242 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2243 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2244 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2245 },
2246 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2247 .rx_drop_en = 0,
2248 .offloads = 0,
2249 };
2250
2251 dev_info->default_txconf = (struct rte_eth_txconf) {
2252 .tx_thresh = {
2253 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2254 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2255 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2256 },
2257 .offloads = 0,
2258 };
2259
2260 dev_info->rx_desc_lim = rx_desc_lim;
2261 dev_info->tx_desc_lim = tx_desc_lim;
2262
2263 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2264 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2265 ETH_LINK_SPEED_1G;
2266
2267 dev_info->max_mtu = dev_info->max_rx_pktlen - E1000_ETH_OVERHEAD;
2268 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2269
2270 return 0;
2271}
2272
2273static const uint32_t *
2274eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2275{
2276 static const uint32_t ptypes[] = {
2277
2278 RTE_PTYPE_L2_ETHER,
2279 RTE_PTYPE_L3_IPV4,
2280 RTE_PTYPE_L3_IPV4_EXT,
2281 RTE_PTYPE_L3_IPV6,
2282 RTE_PTYPE_L3_IPV6_EXT,
2283 RTE_PTYPE_L4_TCP,
2284 RTE_PTYPE_L4_UDP,
2285 RTE_PTYPE_L4_SCTP,
2286 RTE_PTYPE_TUNNEL_IP,
2287 RTE_PTYPE_INNER_L3_IPV6,
2288 RTE_PTYPE_INNER_L3_IPV6_EXT,
2289 RTE_PTYPE_INNER_L4_TCP,
2290 RTE_PTYPE_INNER_L4_UDP,
2291 RTE_PTYPE_UNKNOWN
2292 };
2293
2294 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2295 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2296 return ptypes;
2297 return NULL;
2298}
2299
2300static int
2301eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2302{
2303 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2304
2305 dev_info->min_rx_bufsize = 256;
2306 dev_info->max_rx_pktlen = 0x3FFF;
2307 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2308 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2309 DEV_TX_OFFLOAD_IPV4_CKSUM |
2310 DEV_TX_OFFLOAD_UDP_CKSUM |
2311 DEV_TX_OFFLOAD_TCP_CKSUM |
2312 DEV_TX_OFFLOAD_SCTP_CKSUM |
2313 DEV_TX_OFFLOAD_TCP_TSO;
2314 switch (hw->mac.type) {
2315 case e1000_vfadapt:
2316 dev_info->max_rx_queues = 2;
2317 dev_info->max_tx_queues = 2;
2318 break;
2319 case e1000_vfadapt_i350:
2320 dev_info->max_rx_queues = 1;
2321 dev_info->max_tx_queues = 1;
2322 break;
2323 default:
2324
2325 return -EINVAL;
2326 }
2327
2328 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2329 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2330 dev_info->rx_queue_offload_capa;
2331 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2332 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2333 dev_info->tx_queue_offload_capa;
2334
2335 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2336 .rx_thresh = {
2337 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2338 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2339 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2340 },
2341 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2342 .rx_drop_en = 0,
2343 .offloads = 0,
2344 };
2345
2346 dev_info->default_txconf = (struct rte_eth_txconf) {
2347 .tx_thresh = {
2348 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2349 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2350 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2351 },
2352 .offloads = 0,
2353 };
2354
2355 dev_info->rx_desc_lim = rx_desc_lim;
2356 dev_info->tx_desc_lim = tx_desc_lim;
2357
2358 return 0;
2359}
2360
2361
2362static int
2363eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2364{
2365 struct e1000_hw *hw =
2366 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2367 struct rte_eth_link link;
2368 int link_check, count;
2369
2370 link_check = 0;
2371 hw->mac.get_link_status = 1;
2372
2373
2374 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2375
2376 switch (hw->phy.media_type) {
2377 case e1000_media_type_copper:
2378
2379 e1000_check_for_link(hw);
2380 link_check = !hw->mac.get_link_status;
2381 break;
2382
2383 case e1000_media_type_fiber:
2384 e1000_check_for_link(hw);
2385 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2386 E1000_STATUS_LU);
2387 break;
2388
2389 case e1000_media_type_internal_serdes:
2390 e1000_check_for_link(hw);
2391 link_check = hw->mac.serdes_has_link;
2392 break;
2393
2394
2395 case e1000_media_type_unknown:
2396 eth_igbvf_link_update(hw);
2397 link_check = !hw->mac.get_link_status;
2398 break;
2399
2400 default:
2401 break;
2402 }
2403 if (link_check || wait_to_complete == 0)
2404 break;
2405 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2406 }
2407 memset(&link, 0, sizeof(link));
2408
2409
2410 if (link_check) {
2411 uint16_t duplex, speed;
2412 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2413 link.link_duplex = (duplex == FULL_DUPLEX) ?
2414 ETH_LINK_FULL_DUPLEX :
2415 ETH_LINK_HALF_DUPLEX;
2416 link.link_speed = speed;
2417 link.link_status = ETH_LINK_UP;
2418 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2419 ETH_LINK_SPEED_FIXED);
2420 } else if (!link_check) {
2421 link.link_speed = 0;
2422 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2423 link.link_status = ETH_LINK_DOWN;
2424 link.link_autoneg = ETH_LINK_FIXED;
2425 }
2426
2427 return rte_eth_linkstatus_set(dev, &link);
2428}
2429
2430
2431
2432
2433
2434
2435static void
2436igb_hw_control_acquire(struct e1000_hw *hw)
2437{
2438 uint32_t ctrl_ext;
2439
2440
2441 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2442 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2443}
2444
2445
2446
2447
2448
2449
2450static void
2451igb_hw_control_release(struct e1000_hw *hw)
2452{
2453 uint32_t ctrl_ext;
2454
2455
2456 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2457 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2458 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2459}
2460
2461
2462
2463
2464
2465
2466static void
2467igb_init_manageability(struct e1000_hw *hw)
2468{
2469 if (e1000_enable_mng_pass_thru(hw)) {
2470 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2471 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2472
2473
2474 manc &= ~(E1000_MANC_ARP_EN);
2475
2476
2477 manc |= E1000_MANC_EN_MNG2HOST;
2478 manc2h |= 1 << 5;
2479 manc2h |= 1 << 6;
2480 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2481 E1000_WRITE_REG(hw, E1000_MANC, manc);
2482 }
2483}
2484
2485static void
2486igb_release_manageability(struct e1000_hw *hw)
2487{
2488 if (e1000_enable_mng_pass_thru(hw)) {
2489 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2490
2491 manc |= E1000_MANC_ARP_EN;
2492 manc &= ~E1000_MANC_EN_MNG2HOST;
2493
2494 E1000_WRITE_REG(hw, E1000_MANC, manc);
2495 }
2496}
2497
2498static int
2499eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2500{
2501 struct e1000_hw *hw =
2502 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2503 uint32_t rctl;
2504
2505 rctl = E1000_READ_REG(hw, E1000_RCTL);
2506 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2507 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2508
2509 return 0;
2510}
2511
2512static int
2513eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2514{
2515 struct e1000_hw *hw =
2516 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2517 uint32_t rctl;
2518
2519 rctl = E1000_READ_REG(hw, E1000_RCTL);
2520 rctl &= (~E1000_RCTL_UPE);
2521 if (dev->data->all_multicast == 1)
2522 rctl |= E1000_RCTL_MPE;
2523 else
2524 rctl &= (~E1000_RCTL_MPE);
2525 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2526
2527 return 0;
2528}
2529
2530static int
2531eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2532{
2533 struct e1000_hw *hw =
2534 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2535 uint32_t rctl;
2536
2537 rctl = E1000_READ_REG(hw, E1000_RCTL);
2538 rctl |= E1000_RCTL_MPE;
2539 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2540
2541 return 0;
2542}
2543
2544static int
2545eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2546{
2547 struct e1000_hw *hw =
2548 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2549 uint32_t rctl;
2550
2551 if (dev->data->promiscuous == 1)
2552 return 0;
2553 rctl = E1000_READ_REG(hw, E1000_RCTL);
2554 rctl &= (~E1000_RCTL_MPE);
2555 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2556
2557 return 0;
2558}
2559
2560static int
2561eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2562{
2563 struct e1000_hw *hw =
2564 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2565 struct e1000_vfta * shadow_vfta =
2566 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2567 uint32_t vfta;
2568 uint32_t vid_idx;
2569 uint32_t vid_bit;
2570
2571 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2572 E1000_VFTA_ENTRY_MASK);
2573 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2574 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2575 if (on)
2576 vfta |= vid_bit;
2577 else
2578 vfta &= ~vid_bit;
2579 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2580
2581
2582 shadow_vfta->vfta[vid_idx] = vfta;
2583
2584 return 0;
2585}
2586
2587static int
2588eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2589 enum rte_vlan_type vlan_type,
2590 uint16_t tpid)
2591{
2592 struct e1000_hw *hw =
2593 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2594 uint32_t reg, qinq;
2595
2596 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2597 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2598
2599
2600 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2601 reg = E1000_READ_REG(hw, E1000_VET);
2602 reg = (reg & (~E1000_VET_VET_EXT)) |
2603 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2604 E1000_WRITE_REG(hw, E1000_VET, reg);
2605
2606 return 0;
2607 }
2608
2609
2610 PMD_DRV_LOG(ERR, "Not supported");
2611
2612 return -ENOTSUP;
2613}
2614
2615static void
2616igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2617{
2618 struct e1000_hw *hw =
2619 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2620 uint32_t reg;
2621
2622
2623 reg = E1000_READ_REG(hw, E1000_RCTL);
2624 reg &= ~E1000_RCTL_CFIEN;
2625 reg &= ~E1000_RCTL_VFE;
2626 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2627}
2628
2629static void
2630igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2631{
2632 struct e1000_hw *hw =
2633 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2634 struct e1000_vfta * shadow_vfta =
2635 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2636 uint32_t reg;
2637 int i;
2638
2639
2640 reg = E1000_READ_REG(hw, E1000_RCTL);
2641 reg &= ~E1000_RCTL_CFIEN;
2642 reg |= E1000_RCTL_VFE;
2643 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2644
2645
2646 for (i = 0; i < IGB_VFTA_SIZE; i++)
2647 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2648}
2649
2650static void
2651igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2652{
2653 struct e1000_hw *hw =
2654 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2655 uint32_t reg;
2656
2657
2658 reg = E1000_READ_REG(hw, E1000_CTRL);
2659 reg &= ~E1000_CTRL_VME;
2660 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2661}
2662
2663static void
2664igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2665{
2666 struct e1000_hw *hw =
2667 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2668 uint32_t reg;
2669
2670
2671 reg = E1000_READ_REG(hw, E1000_CTRL);
2672 reg |= E1000_CTRL_VME;
2673 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2674}
2675
2676static void
2677igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2678{
2679 struct e1000_hw *hw =
2680 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2681 uint32_t reg;
2682
2683
2684 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2685 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2686 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2687
2688
2689 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2690 E1000_WRITE_REG(hw, E1000_RLPML,
2691 dev->data->dev_conf.rxmode.max_rx_pkt_len);
2692}
2693
2694static void
2695igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2696{
2697 struct e1000_hw *hw =
2698 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2699 uint32_t reg;
2700
2701
2702 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2703 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2704 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2705
2706
2707 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2708 E1000_WRITE_REG(hw, E1000_RLPML,
2709 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2710 VLAN_TAG_SIZE);
2711}
2712
2713static int
2714eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2715{
2716 struct rte_eth_rxmode *rxmode;
2717
2718 rxmode = &dev->data->dev_conf.rxmode;
2719 if(mask & ETH_VLAN_STRIP_MASK){
2720 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2721 igb_vlan_hw_strip_enable(dev);
2722 else
2723 igb_vlan_hw_strip_disable(dev);
2724 }
2725
2726 if(mask & ETH_VLAN_FILTER_MASK){
2727 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2728 igb_vlan_hw_filter_enable(dev);
2729 else
2730 igb_vlan_hw_filter_disable(dev);
2731 }
2732
2733 if(mask & ETH_VLAN_EXTEND_MASK){
2734 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2735 igb_vlan_hw_extend_enable(dev);
2736 else
2737 igb_vlan_hw_extend_disable(dev);
2738 }
2739
2740 return 0;
2741}
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756static int
2757eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2758{
2759 struct e1000_interrupt *intr =
2760 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2761
2762 if (on)
2763 intr->mask |= E1000_ICR_LSC;
2764 else
2765 intr->mask &= ~E1000_ICR_LSC;
2766
2767 return 0;
2768}
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2781{
2782 uint32_t mask, regval;
2783 int ret;
2784 struct e1000_hw *hw =
2785 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2786 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2787 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2788 int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
2789 struct rte_eth_dev_info dev_info;
2790
2791 memset(&dev_info, 0, sizeof(dev_info));
2792 ret = eth_igb_infos_get(dev, &dev_info);
2793 if (ret != 0)
2794 return ret;
2795
2796 mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift;
2797 regval = E1000_READ_REG(hw, E1000_EIMS);
2798 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2799
2800 return 0;
2801}
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814static int
2815eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2816{
2817 uint32_t icr;
2818 struct e1000_hw *hw =
2819 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2820 struct e1000_interrupt *intr =
2821 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2822
2823 igb_intr_disable(dev);
2824
2825
2826 icr = E1000_READ_REG(hw, E1000_ICR);
2827
2828 intr->flags = 0;
2829 if (icr & E1000_ICR_LSC) {
2830 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2831 }
2832
2833 if (icr & E1000_ICR_VMMB)
2834 intr->flags |= E1000_FLAG_MAILBOX;
2835
2836 return 0;
2837}
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849static int
2850eth_igb_interrupt_action(struct rte_eth_dev *dev,
2851 struct rte_intr_handle *intr_handle)
2852{
2853 struct e1000_hw *hw =
2854 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2855 struct e1000_interrupt *intr =
2856 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2857 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2858 struct rte_eth_link link;
2859 int ret;
2860
2861 if (intr->flags & E1000_FLAG_MAILBOX) {
2862 igb_pf_mbx_process(dev);
2863 intr->flags &= ~E1000_FLAG_MAILBOX;
2864 }
2865
2866 igb_intr_enable(dev);
2867 rte_intr_ack(intr_handle);
2868
2869 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2870 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2871
2872
2873 hw->mac.get_link_status = 1;
2874 ret = eth_igb_link_update(dev, 0);
2875
2876
2877 if (ret < 0)
2878 return 0;
2879
2880 rte_eth_linkstatus_get(dev, &link);
2881 if (link.link_status) {
2882 PMD_INIT_LOG(INFO,
2883 " Port %d: Link Up - speed %u Mbps - %s",
2884 dev->data->port_id,
2885 (unsigned)link.link_speed,
2886 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2887 "full-duplex" : "half-duplex");
2888 } else {
2889 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2890 dev->data->port_id);
2891 }
2892
2893 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
2894 pci_dev->addr.domain,
2895 pci_dev->addr.bus,
2896 pci_dev->addr.devid,
2897 pci_dev->addr.function);
2898 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2899 }
2900
2901 return 0;
2902}
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915static void
2916eth_igb_interrupt_handler(void *param)
2917{
2918 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2919
2920 eth_igb_interrupt_get_status(dev);
2921 eth_igb_interrupt_action(dev, dev->intr_handle);
2922}
2923
2924static int
2925eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2926{
2927 uint32_t eicr;
2928 struct e1000_hw *hw =
2929 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2930 struct e1000_interrupt *intr =
2931 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2932
2933 igbvf_intr_disable(hw);
2934
2935
2936 eicr = E1000_READ_REG(hw, E1000_EICR);
2937 intr->flags = 0;
2938
2939 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2940 intr->flags |= E1000_FLAG_MAILBOX;
2941
2942 return 0;
2943}
2944
2945void igbvf_mbx_process(struct rte_eth_dev *dev)
2946{
2947 struct e1000_hw *hw =
2948 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2949 struct e1000_mbx_info *mbx = &hw->mbx;
2950 u32 in_msg = 0;
2951
2952
2953 in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2954
2955
2956 if (in_msg == E1000_PF_CONTROL_MSG) {
2957
2958 if (mbx->ops.read(hw, &in_msg, 1, 0))
2959 return;
2960 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2961 NULL);
2962 }
2963}
2964
2965static int
2966eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2967{
2968 struct e1000_interrupt *intr =
2969 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2970
2971 if (intr->flags & E1000_FLAG_MAILBOX) {
2972 igbvf_mbx_process(dev);
2973 intr->flags &= ~E1000_FLAG_MAILBOX;
2974 }
2975
2976 igbvf_intr_enable(dev);
2977 rte_intr_ack(intr_handle);
2978
2979 return 0;
2980}
2981
2982static void
2983eth_igbvf_interrupt_handler(void *param)
2984{
2985 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2986
2987 eth_igbvf_interrupt_get_status(dev);
2988 eth_igbvf_interrupt_action(dev, dev->intr_handle);
2989}
2990
2991static int
2992eth_igb_led_on(struct rte_eth_dev *dev)
2993{
2994 struct e1000_hw *hw;
2995
2996 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2997 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2998}
2999
3000static int
3001eth_igb_led_off(struct rte_eth_dev *dev)
3002{
3003 struct e1000_hw *hw;
3004
3005 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3006 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3007}
3008
3009static int
3010eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3011{
3012 struct e1000_hw *hw;
3013 uint32_t ctrl;
3014 int tx_pause;
3015 int rx_pause;
3016
3017 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3018 fc_conf->pause_time = hw->fc.pause_time;
3019 fc_conf->high_water = hw->fc.high_water;
3020 fc_conf->low_water = hw->fc.low_water;
3021 fc_conf->send_xon = hw->fc.send_xon;
3022 fc_conf->autoneg = hw->mac.autoneg;
3023
3024
3025
3026
3027
3028 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3029 if (ctrl & E1000_CTRL_TFCE)
3030 tx_pause = 1;
3031 else
3032 tx_pause = 0;
3033
3034 if (ctrl & E1000_CTRL_RFCE)
3035 rx_pause = 1;
3036 else
3037 rx_pause = 0;
3038
3039 if (rx_pause && tx_pause)
3040 fc_conf->mode = RTE_FC_FULL;
3041 else if (rx_pause)
3042 fc_conf->mode = RTE_FC_RX_PAUSE;
3043 else if (tx_pause)
3044 fc_conf->mode = RTE_FC_TX_PAUSE;
3045 else
3046 fc_conf->mode = RTE_FC_NONE;
3047
3048 return 0;
3049}
3050
3051static int
3052eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3053{
3054 struct e1000_hw *hw;
3055 int err;
3056 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3057 e1000_fc_none,
3058 e1000_fc_rx_pause,
3059 e1000_fc_tx_pause,
3060 e1000_fc_full
3061 };
3062 uint32_t rx_buf_size;
3063 uint32_t max_high_water;
3064 uint32_t rctl;
3065 uint32_t ctrl;
3066
3067 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3068 if (fc_conf->autoneg != hw->mac.autoneg)
3069 return -ENOTSUP;
3070 rx_buf_size = igb_get_rx_buffer_size(hw);
3071 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3072
3073
3074 max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
3075 if ((fc_conf->high_water > max_high_water) ||
3076 (fc_conf->high_water < fc_conf->low_water)) {
3077 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3078 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
3079 return -EINVAL;
3080 }
3081
3082 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3083 hw->fc.pause_time = fc_conf->pause_time;
3084 hw->fc.high_water = fc_conf->high_water;
3085 hw->fc.low_water = fc_conf->low_water;
3086 hw->fc.send_xon = fc_conf->send_xon;
3087
3088 err = e1000_setup_link_generic(hw);
3089 if (err == E1000_SUCCESS) {
3090
3091
3092
3093
3094 rctl = E1000_READ_REG(hw, E1000_RCTL);
3095
3096
3097 if (fc_conf->mac_ctrl_frame_fwd != 0)
3098 rctl |= E1000_RCTL_PMCF;
3099 else
3100 rctl &= ~E1000_RCTL_PMCF;
3101
3102 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3103
3104
3105
3106
3107
3108 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3109
3110
3111
3112
3113
3114 switch (fc_conf->mode) {
3115 case RTE_FC_NONE:
3116 ctrl &= ~E1000_CTRL_RFCE & ~E1000_CTRL_TFCE;
3117 break;
3118 case RTE_FC_RX_PAUSE:
3119 ctrl |= E1000_CTRL_RFCE;
3120 ctrl &= ~E1000_CTRL_TFCE;
3121 break;
3122 case RTE_FC_TX_PAUSE:
3123 ctrl |= E1000_CTRL_TFCE;
3124 ctrl &= ~E1000_CTRL_RFCE;
3125 break;
3126 case RTE_FC_FULL:
3127 ctrl |= E1000_CTRL_RFCE | E1000_CTRL_TFCE;
3128 break;
3129 default:
3130 PMD_INIT_LOG(ERR, "invalid flow control mode");
3131 return -EINVAL;
3132 }
3133
3134 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
3135
3136 E1000_WRITE_FLUSH(hw);
3137
3138 return 0;
3139 }
3140
3141 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3142 return -EIO;
3143}
3144
3145#define E1000_RAH_POOLSEL_SHIFT (18)
3146static int
3147eth_igb_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3148 uint32_t index, uint32_t pool)
3149{
3150 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3151 uint32_t rah;
3152
3153 e1000_rar_set(hw, mac_addr->addr_bytes, index);
3154 rah = E1000_READ_REG(hw, E1000_RAH(index));
3155 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3156 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3157 return 0;
3158}
3159
3160static void
3161eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3162{
3163 uint8_t addr[RTE_ETHER_ADDR_LEN];
3164 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3165
3166 memset(addr, 0, sizeof(addr));
3167
3168 e1000_rar_set(hw, addr, index);
3169}
3170
3171static int
3172eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3173 struct rte_ether_addr *addr)
3174{
3175 eth_igb_rar_clear(dev, 0);
3176 eth_igb_rar_set(dev, (void *)addr, 0, 0);
3177
3178 return 0;
3179}
3180
3181
3182
3183static void
3184igbvf_intr_disable(struct e1000_hw *hw)
3185{
3186 PMD_INIT_FUNC_TRACE();
3187
3188
3189 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3190
3191 E1000_WRITE_FLUSH(hw);
3192}
3193
3194static void
3195igbvf_stop_adapter(struct rte_eth_dev *dev)
3196{
3197 u32 reg_val;
3198 u16 i;
3199 struct rte_eth_dev_info dev_info;
3200 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3201 int ret;
3202
3203 memset(&dev_info, 0, sizeof(dev_info));
3204 ret = eth_igbvf_infos_get(dev, &dev_info);
3205 if (ret != 0)
3206 return;
3207
3208
3209 igbvf_intr_disable(hw);
3210
3211
3212 E1000_READ_REG(hw, E1000_EICR);
3213
3214
3215 for (i = 0; i < dev_info.max_tx_queues; i++)
3216 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3217
3218
3219 for (i = 0; i < dev_info.max_rx_queues; i++) {
3220 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3221 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3222 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3223 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3224 ;
3225 }
3226
3227
3228 E1000_WRITE_FLUSH(hw);
3229 msec_delay(2);
3230}
3231
3232static int eth_igbvf_link_update(struct e1000_hw *hw)
3233{
3234 struct e1000_mbx_info *mbx = &hw->mbx;
3235 struct e1000_mac_info *mac = &hw->mac;
3236 int ret_val = E1000_SUCCESS;
3237
3238 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3239
3240
3241
3242
3243
3244
3245
3246
3247 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3248 mac->get_link_status = TRUE;
3249
3250 if (!mac->get_link_status)
3251 goto out;
3252
3253
3254 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3255 goto out;
3256
3257
3258
3259 mac->get_link_status = FALSE;
3260
3261out:
3262 return ret_val;
3263}
3264
3265
3266static int
3267igbvf_dev_configure(struct rte_eth_dev *dev)
3268{
3269 struct rte_eth_conf* conf = &dev->data->dev_conf;
3270
3271 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3272 dev->data->port_id);
3273
3274 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3275 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3276
3277
3278
3279
3280
3281#ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3282 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
3283 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3284 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
3285 }
3286#else
3287 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
3288 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3289 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
3290 }
3291#endif
3292
3293 return 0;
3294}
3295
3296static int
3297igbvf_dev_start(struct rte_eth_dev *dev)
3298{
3299 struct e1000_hw *hw =
3300 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3301 struct e1000_adapter *adapter =
3302 E1000_DEV_PRIVATE(dev->data->dev_private);
3303 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3304 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3305 int ret;
3306 uint32_t intr_vector = 0;
3307
3308 PMD_INIT_FUNC_TRACE();
3309
3310 hw->mac.ops.reset_hw(hw);
3311 adapter->stopped = 0;
3312
3313
3314 igbvf_set_vfta_all(dev,1);
3315
3316 eth_igbvf_tx_init(dev);
3317
3318
3319 ret = eth_igbvf_rx_init(dev);
3320 if (ret) {
3321 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3322 igb_dev_clear_queues(dev);
3323 return ret;
3324 }
3325
3326
3327 if (rte_intr_cap_multiple(intr_handle) &&
3328 dev->data->dev_conf.intr_conf.rxq) {
3329 intr_vector = dev->data->nb_rx_queues;
3330 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3331 if (ret)
3332 return ret;
3333 }
3334
3335 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3336 intr_handle->intr_vec =
3337 rte_zmalloc("intr_vec",
3338 dev->data->nb_rx_queues * sizeof(int), 0);
3339 if (!intr_handle->intr_vec) {
3340 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3341 " intr_vec", dev->data->nb_rx_queues);
3342 return -ENOMEM;
3343 }
3344 }
3345
3346 eth_igbvf_configure_msix_intr(dev);
3347
3348
3349 rte_intr_enable(intr_handle);
3350
3351
3352 igbvf_intr_enable(dev);
3353
3354 return 0;
3355}
3356
3357static int
3358igbvf_dev_stop(struct rte_eth_dev *dev)
3359{
3360 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3361 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3362 struct e1000_adapter *adapter =
3363 E1000_DEV_PRIVATE(dev->data->dev_private);
3364
3365 if (adapter->stopped)
3366 return 0;
3367
3368 PMD_INIT_FUNC_TRACE();
3369
3370 igbvf_stop_adapter(dev);
3371
3372
3373
3374
3375
3376 igbvf_set_vfta_all(dev,0);
3377
3378 igb_dev_clear_queues(dev);
3379
3380
3381 rte_intr_disable(intr_handle);
3382
3383
3384 rte_intr_efd_disable(intr_handle);
3385 if (intr_handle->intr_vec) {
3386 rte_free(intr_handle->intr_vec);
3387 intr_handle->intr_vec = NULL;
3388 }
3389
3390 adapter->stopped = true;
3391 dev->data->dev_started = 0;
3392
3393 return 0;
3394}
3395
3396static int
3397igbvf_dev_close(struct rte_eth_dev *dev)
3398{
3399 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3400 struct rte_ether_addr addr;
3401 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3402 int ret;
3403
3404 PMD_INIT_FUNC_TRACE();
3405
3406 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3407 return 0;
3408
3409 e1000_reset_hw(hw);
3410
3411 ret = igbvf_dev_stop(dev);
3412 if (ret != 0)
3413 return ret;
3414
3415 igb_dev_free_queues(dev);
3416
3417
3418
3419
3420
3421
3422
3423 memset(&addr, 0, sizeof(addr));
3424 igbvf_default_mac_addr_set(dev, &addr);
3425
3426 rte_intr_callback_unregister(&pci_dev->intr_handle,
3427 eth_igbvf_interrupt_handler,
3428 (void *)dev);
3429
3430 return 0;
3431}
3432
3433static int
3434igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3435{
3436 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3437
3438
3439 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3440
3441 return 0;
3442}
3443
3444static int
3445igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3446{
3447 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3448
3449
3450 if (dev->data->all_multicast == 1)
3451 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3452 else
3453 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3454
3455 return 0;
3456}
3457
3458static int
3459igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3460{
3461 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3462
3463
3464 if (dev->data->promiscuous == 0)
3465 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3466
3467 return 0;
3468}
3469
3470static int
3471igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3472{
3473 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3474
3475
3476 if (dev->data->promiscuous == 0)
3477 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3478
3479 return 0;
3480}
3481
3482static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3483{
3484 struct e1000_mbx_info *mbx = &hw->mbx;
3485 uint32_t msgbuf[2];
3486 s32 err;
3487
3488
3489 msgbuf[0] = E1000_VF_SET_VLAN;
3490 msgbuf[1] = vid;
3491
3492 if (on)
3493 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3494
3495 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3496 if (err)
3497 goto mbx_err;
3498
3499 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3500 if (err)
3501 goto mbx_err;
3502
3503 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3504 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3505 err = -EINVAL;
3506
3507mbx_err:
3508 return err;
3509}
3510
3511static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3512{
3513 struct e1000_hw *hw =
3514 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3515 struct e1000_vfta * shadow_vfta =
3516 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3517 int i = 0, j = 0, vfta = 0, mask = 1;
3518
3519 for (i = 0; i < IGB_VFTA_SIZE; i++){
3520 vfta = shadow_vfta->vfta[i];
3521 if(vfta){
3522 mask = 1;
3523 for (j = 0; j < 32; j++){
3524 if(vfta & mask)
3525 igbvf_set_vfta(hw,
3526 (uint16_t)((i<<5)+j), on);
3527 mask<<=1;
3528 }
3529 }
3530 }
3531
3532}
3533
3534static int
3535igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3536{
3537 struct e1000_hw *hw =
3538 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3539 struct e1000_vfta * shadow_vfta =
3540 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3541 uint32_t vid_idx = 0;
3542 uint32_t vid_bit = 0;
3543 int ret = 0;
3544
3545 PMD_INIT_FUNC_TRACE();
3546
3547
3548 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3549 if(ret){
3550 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3551 return ret;
3552 }
3553 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3554 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3555
3556
3557 if (on)
3558 shadow_vfta->vfta[vid_idx] |= vid_bit;
3559 else
3560 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3561
3562 return 0;
3563}
3564
3565static int
3566igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3567{
3568 struct e1000_hw *hw =
3569 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3570
3571
3572 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3573 return 0;
3574}
3575
3576
3577static int
3578eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3579 struct rte_eth_rss_reta_entry64 *reta_conf,
3580 uint16_t reta_size)
3581{
3582 uint8_t i, j, mask;
3583 uint32_t reta, r;
3584 uint16_t idx, shift;
3585 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3586
3587 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3588 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3589 "(%d) doesn't match the number hardware can supported "
3590 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3591 return -EINVAL;
3592 }
3593
3594 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3595 idx = i / RTE_RETA_GROUP_SIZE;
3596 shift = i % RTE_RETA_GROUP_SIZE;
3597 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3598 IGB_4_BIT_MASK);
3599 if (!mask)
3600 continue;
3601 if (mask == IGB_4_BIT_MASK)
3602 r = 0;
3603 else
3604 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3605 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3606 if (mask & (0x1 << j))
3607 reta |= reta_conf[idx].reta[shift + j] <<
3608 (CHAR_BIT * j);
3609 else
3610 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3611 }
3612 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3613 }
3614
3615 return 0;
3616}
3617
3618static int
3619eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3620 struct rte_eth_rss_reta_entry64 *reta_conf,
3621 uint16_t reta_size)
3622{
3623 uint8_t i, j, mask;
3624 uint32_t reta;
3625 uint16_t idx, shift;
3626 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3627
3628 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3629 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3630 "(%d) doesn't match the number hardware can supported "
3631 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3632 return -EINVAL;
3633 }
3634
3635 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3636 idx = i / RTE_RETA_GROUP_SIZE;
3637 shift = i % RTE_RETA_GROUP_SIZE;
3638 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3639 IGB_4_BIT_MASK);
3640 if (!mask)
3641 continue;
3642 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3643 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3644 if (mask & (0x1 << j))
3645 reta_conf[idx].reta[shift + j] =
3646 ((reta >> (CHAR_BIT * j)) &
3647 IGB_8_BIT_MASK);
3648 }
3649 }
3650
3651 return 0;
3652}
3653
3654int
3655eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3656 struct rte_eth_syn_filter *filter,
3657 bool add)
3658{
3659 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3660 struct e1000_filter_info *filter_info =
3661 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3662 uint32_t synqf, rfctl;
3663
3664 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3665 return -EINVAL;
3666
3667 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3668
3669 if (add) {
3670 if (synqf & E1000_SYN_FILTER_ENABLE)
3671 return -EINVAL;
3672
3673 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3674 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3675
3676 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3677 if (filter->hig_pri)
3678 rfctl |= E1000_RFCTL_SYNQFP;
3679 else
3680 rfctl &= ~E1000_RFCTL_SYNQFP;
3681
3682 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3683 } else {
3684 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3685 return -ENOENT;
3686 synqf = 0;
3687 }
3688
3689 filter_info->syn_info = synqf;
3690 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3691 E1000_WRITE_FLUSH(hw);
3692 return 0;
3693}
3694
3695
3696static inline int
3697ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3698 struct e1000_2tuple_filter_info *filter_info)
3699{
3700 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3701 return -EINVAL;
3702 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3703 return -EINVAL;
3704 if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
3705 return -EINVAL;
3706
3707 switch (filter->dst_port_mask) {
3708 case UINT16_MAX:
3709 filter_info->dst_port_mask = 0;
3710 filter_info->dst_port = filter->dst_port;
3711 break;
3712 case 0:
3713 filter_info->dst_port_mask = 1;
3714 break;
3715 default:
3716 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3717 return -EINVAL;
3718 }
3719
3720 switch (filter->proto_mask) {
3721 case UINT8_MAX:
3722 filter_info->proto_mask = 0;
3723 filter_info->proto = filter->proto;
3724 break;
3725 case 0:
3726 filter_info->proto_mask = 1;
3727 break;
3728 default:
3729 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3730 return -EINVAL;
3731 }
3732
3733 filter_info->priority = (uint8_t)filter->priority;
3734 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3735 filter_info->tcp_flags = filter->tcp_flags;
3736 else
3737 filter_info->tcp_flags = 0;
3738
3739 return 0;
3740}
3741
3742static inline struct e1000_2tuple_filter *
3743igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3744 struct e1000_2tuple_filter_info *key)
3745{
3746 struct e1000_2tuple_filter *it;
3747
3748 TAILQ_FOREACH(it, filter_list, entries) {
3749 if (memcmp(key, &it->filter_info,
3750 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3751 return it;
3752 }
3753 }
3754 return NULL;
3755}
3756
3757
3758static inline void
3759igb_inject_2uple_filter(struct rte_eth_dev *dev,
3760 struct e1000_2tuple_filter *filter)
3761{
3762 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3763 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3764 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3765 int i;
3766
3767 i = filter->index;
3768 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3769 if (filter->filter_info.dst_port_mask == 1)
3770 imir |= E1000_IMIR_PORT_BP;
3771 else
3772 imir &= ~E1000_IMIR_PORT_BP;
3773
3774 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3775
3776 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3777 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3778 ttqf |= (uint32_t)(filter->filter_info.proto &
3779 E1000_TTQF_PROTOCOL_MASK);
3780 if (filter->filter_info.proto_mask == 0)
3781 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3782
3783
3784 if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
3785 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
3786 imir_ext |= E1000_IMIREXT_CTRL_URG;
3787 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
3788 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3789 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
3790 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3791 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
3792 imir_ext |= E1000_IMIREXT_CTRL_RST;
3793 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
3794 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3795 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
3796 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3797 } else {
3798 imir_ext |= E1000_IMIREXT_CTRL_BP;
3799 }
3800 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3801 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3802 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3803}
3804
3805
3806
3807
3808
3809
3810
3811
3812
3813
3814
3815
3816static int
3817igb_add_2tuple_filter(struct rte_eth_dev *dev,
3818 struct rte_eth_ntuple_filter *ntuple_filter)
3819{
3820 struct e1000_filter_info *filter_info =
3821 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3822 struct e1000_2tuple_filter *filter;
3823 int i, ret;
3824
3825 filter = rte_zmalloc("e1000_2tuple_filter",
3826 sizeof(struct e1000_2tuple_filter), 0);
3827 if (filter == NULL)
3828 return -ENOMEM;
3829
3830 ret = ntuple_filter_to_2tuple(ntuple_filter,
3831 &filter->filter_info);
3832 if (ret < 0) {
3833 rte_free(filter);
3834 return ret;
3835 }
3836 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3837 &filter->filter_info) != NULL) {
3838 PMD_DRV_LOG(ERR, "filter exists.");
3839 rte_free(filter);
3840 return -EEXIST;
3841 }
3842 filter->queue = ntuple_filter->queue;
3843
3844
3845
3846
3847
3848 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3849 if (!(filter_info->twotuple_mask & (1 << i))) {
3850 filter_info->twotuple_mask |= 1 << i;
3851 filter->index = i;
3852 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3853 filter,
3854 entries);
3855 break;
3856 }
3857 }
3858 if (i >= E1000_MAX_TTQF_FILTERS) {
3859 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3860 rte_free(filter);
3861 return -ENOSYS;
3862 }
3863
3864 igb_inject_2uple_filter(dev, filter);
3865 return 0;
3866}
3867
3868int
3869igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3870 struct e1000_2tuple_filter *filter)
3871{
3872 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3873 struct e1000_filter_info *filter_info =
3874 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3875
3876 filter_info->twotuple_mask &= ~(1 << filter->index);
3877 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3878 rte_free(filter);
3879
3880 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3881 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3882 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3883 return 0;
3884}
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896
3897static int
3898igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3899 struct rte_eth_ntuple_filter *ntuple_filter)
3900{
3901 struct e1000_filter_info *filter_info =
3902 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3903 struct e1000_2tuple_filter_info filter_2tuple;
3904 struct e1000_2tuple_filter *filter;
3905 int ret;
3906
3907 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3908 ret = ntuple_filter_to_2tuple(ntuple_filter,
3909 &filter_2tuple);
3910 if (ret < 0)
3911 return ret;
3912
3913 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3914 &filter_2tuple);
3915 if (filter == NULL) {
3916 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3917 return -ENOENT;
3918 }
3919
3920 igb_delete_2tuple_filter(dev, filter);
3921
3922 return 0;
3923}
3924
3925
3926static inline void
3927igb_inject_flex_filter(struct rte_eth_dev *dev,
3928 struct e1000_flex_filter *filter)
3929{
3930 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3931 uint32_t wufc, queueing;
3932 uint32_t reg_off;
3933 uint8_t i, j = 0;
3934
3935 wufc = E1000_READ_REG(hw, E1000_WUFC);
3936 if (filter->index < E1000_MAX_FHFT)
3937 reg_off = E1000_FHFT(filter->index);
3938 else
3939 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3940
3941 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3942 (E1000_WUFC_FLX0 << filter->index));
3943 queueing = filter->filter_info.len |
3944 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3945 (filter->filter_info.priority <<
3946 E1000_FHFT_QUEUEING_PRIO_SHIFT);
3947 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3948 queueing);
3949
3950 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3951 E1000_WRITE_REG(hw, reg_off,
3952 filter->filter_info.dwords[j]);
3953 reg_off += sizeof(uint32_t);
3954 E1000_WRITE_REG(hw, reg_off,
3955 filter->filter_info.dwords[++j]);
3956 reg_off += sizeof(uint32_t);
3957 E1000_WRITE_REG(hw, reg_off,
3958 (uint32_t)filter->filter_info.mask[i]);
3959 reg_off += sizeof(uint32_t) * 2;
3960 ++j;
3961 }
3962}
3963
3964static inline struct e1000_flex_filter *
3965eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3966 struct e1000_flex_filter_info *key)
3967{
3968 struct e1000_flex_filter *it;
3969
3970 TAILQ_FOREACH(it, filter_list, entries) {
3971 if (memcmp(key, &it->filter_info,
3972 sizeof(struct e1000_flex_filter_info)) == 0)
3973 return it;
3974 }
3975
3976 return NULL;
3977}
3978
3979
3980
3981
3982
3983
3984void
3985igb_remove_flex_filter(struct rte_eth_dev *dev,
3986 struct e1000_flex_filter *filter)
3987{
3988 struct e1000_filter_info *filter_info =
3989 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3990 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3991 uint32_t wufc, i;
3992 uint32_t reg_off;
3993
3994 wufc = E1000_READ_REG(hw, E1000_WUFC);
3995 if (filter->index < E1000_MAX_FHFT)
3996 reg_off = E1000_FHFT(filter->index);
3997 else
3998 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3999
4000 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4001 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4002
4003 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4004 (~(E1000_WUFC_FLX0 << filter->index)));
4005
4006 filter_info->flex_mask &= ~(1 << filter->index);
4007 TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4008 rte_free(filter);
4009}
4010
4011int
4012eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4013 struct igb_flex_filter *filter,
4014 bool add)
4015{
4016 struct e1000_filter_info *filter_info =
4017 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4018 struct e1000_flex_filter *flex_filter, *it;
4019 uint32_t mask;
4020 uint8_t shift, i;
4021
4022 flex_filter = rte_zmalloc("e1000_flex_filter",
4023 sizeof(struct e1000_flex_filter), 0);
4024 if (flex_filter == NULL)
4025 return -ENOMEM;
4026
4027 flex_filter->filter_info.len = filter->len;
4028 flex_filter->filter_info.priority = filter->priority;
4029 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4030 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4031 mask = 0;
4032
4033 for (shift = 0; shift < CHAR_BIT; shift++) {
4034 if (filter->mask[i] & (0x01 << shift))
4035 mask |= (0x80 >> shift);
4036 }
4037 flex_filter->filter_info.mask[i] = mask;
4038 }
4039
4040 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4041 &flex_filter->filter_info);
4042 if (it == NULL && !add) {
4043 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4044 rte_free(flex_filter);
4045 return -ENOENT;
4046 }
4047 if (it != NULL && add) {
4048 PMD_DRV_LOG(ERR, "filter exists.");
4049 rte_free(flex_filter);
4050 return -EEXIST;
4051 }
4052
4053 if (add) {
4054 flex_filter->queue = filter->queue;
4055
4056
4057
4058
4059 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4060 if (!(filter_info->flex_mask & (1 << i))) {
4061 filter_info->flex_mask |= 1 << i;
4062 flex_filter->index = i;
4063 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4064 flex_filter,
4065 entries);
4066 break;
4067 }
4068 }
4069 if (i >= E1000_MAX_FLEX_FILTERS) {
4070 PMD_DRV_LOG(ERR, "flex filters are full.");
4071 rte_free(flex_filter);
4072 return -ENOSYS;
4073 }
4074
4075 igb_inject_flex_filter(dev, flex_filter);
4076
4077 } else {
4078 igb_remove_flex_filter(dev, it);
4079 rte_free(flex_filter);
4080 }
4081
4082 return 0;
4083}
4084
4085
4086static inline int
4087ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4088 struct e1000_5tuple_filter_info *filter_info)
4089{
4090 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4091 return -EINVAL;
4092 if (filter->priority > E1000_2TUPLE_MAX_PRI)
4093 return -EINVAL;
4094 if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
4095 return -EINVAL;
4096
4097 switch (filter->dst_ip_mask) {
4098 case UINT32_MAX:
4099 filter_info->dst_ip_mask = 0;
4100 filter_info->dst_ip = filter->dst_ip;
4101 break;
4102 case 0:
4103 filter_info->dst_ip_mask = 1;
4104 break;
4105 default:
4106 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4107 return -EINVAL;
4108 }
4109
4110 switch (filter->src_ip_mask) {
4111 case UINT32_MAX:
4112 filter_info->src_ip_mask = 0;
4113 filter_info->src_ip = filter->src_ip;
4114 break;
4115 case 0:
4116 filter_info->src_ip_mask = 1;
4117 break;
4118 default:
4119 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4120 return -EINVAL;
4121 }
4122
4123 switch (filter->dst_port_mask) {
4124 case UINT16_MAX:
4125 filter_info->dst_port_mask = 0;
4126 filter_info->dst_port = filter->dst_port;
4127 break;
4128 case 0:
4129 filter_info->dst_port_mask = 1;
4130 break;
4131 default:
4132 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4133 return -EINVAL;
4134 }
4135
4136 switch (filter->src_port_mask) {
4137 case UINT16_MAX:
4138 filter_info->src_port_mask = 0;
4139 filter_info->src_port = filter->src_port;
4140 break;
4141 case 0:
4142 filter_info->src_port_mask = 1;
4143 break;
4144 default:
4145 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4146 return -EINVAL;
4147 }
4148
4149 switch (filter->proto_mask) {
4150 case UINT8_MAX:
4151 filter_info->proto_mask = 0;
4152 filter_info->proto = filter->proto;
4153 break;
4154 case 0:
4155 filter_info->proto_mask = 1;
4156 break;
4157 default:
4158 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4159 return -EINVAL;
4160 }
4161
4162 filter_info->priority = (uint8_t)filter->priority;
4163 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4164 filter_info->tcp_flags = filter->tcp_flags;
4165 else
4166 filter_info->tcp_flags = 0;
4167
4168 return 0;
4169}
4170
4171static inline struct e1000_5tuple_filter *
4172igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4173 struct e1000_5tuple_filter_info *key)
4174{
4175 struct e1000_5tuple_filter *it;
4176
4177 TAILQ_FOREACH(it, filter_list, entries) {
4178 if (memcmp(key, &it->filter_info,
4179 sizeof(struct e1000_5tuple_filter_info)) == 0) {
4180 return it;
4181 }
4182 }
4183 return NULL;
4184}
4185
4186
4187static inline void
4188igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4189 struct e1000_5tuple_filter *filter)
4190{
4191 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4192 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4193 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4194 uint8_t i;
4195
4196 i = filter->index;
4197 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4198 if (filter->filter_info.src_ip_mask == 0)
4199 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4200 if (filter->filter_info.dst_ip_mask == 0)
4201 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4202 if (filter->filter_info.src_port_mask == 0)
4203 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4204 if (filter->filter_info.proto_mask == 0)
4205 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4206 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4207 E1000_FTQF_QUEUE_MASK;
4208 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4209 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4210 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4211 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4212
4213 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4214 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4215
4216 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4217 if (filter->filter_info.dst_port_mask == 1)
4218 imir |= E1000_IMIR_PORT_BP;
4219 else
4220 imir &= ~E1000_IMIR_PORT_BP;
4221 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4222
4223
4224 if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
4225 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
4226 imir_ext |= E1000_IMIREXT_CTRL_URG;
4227 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
4228 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4229 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
4230 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4231 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
4232 imir_ext |= E1000_IMIREXT_CTRL_RST;
4233 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
4234 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4235 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
4236 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4237 } else {
4238 imir_ext |= E1000_IMIREXT_CTRL_BP;
4239 }
4240 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4241 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4242}
4243
4244
4245
4246
4247
4248
4249
4250
4251
4252
4253
4254
4255static int
4256igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4257 struct rte_eth_ntuple_filter *ntuple_filter)
4258{
4259 struct e1000_filter_info *filter_info =
4260 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4261 struct e1000_5tuple_filter *filter;
4262 uint8_t i;
4263 int ret;
4264
4265 filter = rte_zmalloc("e1000_5tuple_filter",
4266 sizeof(struct e1000_5tuple_filter), 0);
4267 if (filter == NULL)
4268 return -ENOMEM;
4269
4270 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4271 &filter->filter_info);
4272 if (ret < 0) {
4273 rte_free(filter);
4274 return ret;
4275 }
4276
4277 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4278 &filter->filter_info) != NULL) {
4279 PMD_DRV_LOG(ERR, "filter exists.");
4280 rte_free(filter);
4281 return -EEXIST;
4282 }
4283 filter->queue = ntuple_filter->queue;
4284
4285
4286
4287
4288
4289 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4290 if (!(filter_info->fivetuple_mask & (1 << i))) {
4291 filter_info->fivetuple_mask |= 1 << i;
4292 filter->index = i;
4293 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4294 filter,
4295 entries);
4296 break;
4297 }
4298 }
4299 if (i >= E1000_MAX_FTQF_FILTERS) {
4300 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4301 rte_free(filter);
4302 return -ENOSYS;
4303 }
4304
4305 igb_inject_5tuple_filter_82576(dev, filter);
4306 return 0;
4307}
4308
4309int
4310igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4311 struct e1000_5tuple_filter *filter)
4312{
4313 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4314 struct e1000_filter_info *filter_info =
4315 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4316
4317 filter_info->fivetuple_mask &= ~(1 << filter->index);
4318 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4319 rte_free(filter);
4320
4321 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4322 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4323 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4324 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4325 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4326 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4327 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4328 return 0;
4329}
4330
4331
4332
4333
4334
4335
4336
4337
4338
4339
4340
4341
4342static int
4343igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4344 struct rte_eth_ntuple_filter *ntuple_filter)
4345{
4346 struct e1000_filter_info *filter_info =
4347 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4348 struct e1000_5tuple_filter_info filter_5tuple;
4349 struct e1000_5tuple_filter *filter;
4350 int ret;
4351
4352 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4353 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4354 &filter_5tuple);
4355 if (ret < 0)
4356 return ret;
4357
4358 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4359 &filter_5tuple);
4360 if (filter == NULL) {
4361 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4362 return -ENOENT;
4363 }
4364
4365 igb_delete_5tuple_filter_82576(dev, filter);
4366
4367 return 0;
4368}
4369
4370static int
4371eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4372{
4373 uint32_t rctl;
4374 struct e1000_hw *hw;
4375 struct rte_eth_dev_info dev_info;
4376 uint32_t frame_size = mtu + E1000_ETH_OVERHEAD;
4377 int ret;
4378
4379 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4380
4381#ifdef RTE_LIBRTE_82571_SUPPORT
4382
4383 if (hw->mac.type == e1000_82571)
4384 return -ENOTSUP;
4385#endif
4386 ret = eth_igb_infos_get(dev, &dev_info);
4387 if (ret != 0)
4388 return ret;
4389
4390
4391 if (mtu < RTE_ETHER_MIN_MTU ||
4392 frame_size > dev_info.max_rx_pktlen)
4393 return -EINVAL;
4394
4395
4396
4397
4398
4399 if (dev->data->dev_started && !dev->data->scattered_rx &&
4400 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
4401 PMD_INIT_LOG(ERR, "Stop port first.");
4402 return -EINVAL;
4403 }
4404
4405 rctl = E1000_READ_REG(hw, E1000_RCTL);
4406
4407
4408 if (frame_size > E1000_ETH_MAX_LEN) {
4409 dev->data->dev_conf.rxmode.offloads |=
4410 DEV_RX_OFFLOAD_JUMBO_FRAME;
4411 rctl |= E1000_RCTL_LPE;
4412 } else {
4413 dev->data->dev_conf.rxmode.offloads &=
4414 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4415 rctl &= ~E1000_RCTL_LPE;
4416 }
4417 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4418
4419
4420 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4421
4422 E1000_WRITE_REG(hw, E1000_RLPML,
4423 dev->data->dev_conf.rxmode.max_rx_pkt_len);
4424
4425 return 0;
4426}
4427
4428
4429
4430
4431
4432
4433
4434
4435
4436
4437
4438
4439
4440int
4441igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4442 struct rte_eth_ntuple_filter *ntuple_filter,
4443 bool add)
4444{
4445 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4446 int ret;
4447
4448 switch (ntuple_filter->flags) {
4449 case RTE_5TUPLE_FLAGS:
4450 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4451 if (hw->mac.type != e1000_82576)
4452 return -ENOTSUP;
4453 if (add)
4454 ret = igb_add_5tuple_filter_82576(dev,
4455 ntuple_filter);
4456 else
4457 ret = igb_remove_5tuple_filter_82576(dev,
4458 ntuple_filter);
4459 break;
4460 case RTE_2TUPLE_FLAGS:
4461 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4462 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4463 hw->mac.type != e1000_i210 &&
4464 hw->mac.type != e1000_i211)
4465 return -ENOTSUP;
4466 if (add)
4467 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4468 else
4469 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4470 break;
4471 default:
4472 ret = -EINVAL;
4473 break;
4474 }
4475
4476 return ret;
4477}
4478
4479static inline int
4480igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4481 uint16_t ethertype)
4482{
4483 int i;
4484
4485 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4486 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4487 (filter_info->ethertype_mask & (1 << i)))
4488 return i;
4489 }
4490 return -1;
4491}
4492
4493static inline int
4494igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4495 uint16_t ethertype, uint32_t etqf)
4496{
4497 int i;
4498
4499 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4500 if (!(filter_info->ethertype_mask & (1 << i))) {
4501 filter_info->ethertype_mask |= 1 << i;
4502 filter_info->ethertype_filters[i].ethertype = ethertype;
4503 filter_info->ethertype_filters[i].etqf = etqf;
4504 return i;
4505 }
4506 }
4507 return -1;
4508}
4509
4510int
4511igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4512 uint8_t idx)
4513{
4514 if (idx >= E1000_MAX_ETQF_FILTERS)
4515 return -1;
4516 filter_info->ethertype_mask &= ~(1 << idx);
4517 filter_info->ethertype_filters[idx].ethertype = 0;
4518 filter_info->ethertype_filters[idx].etqf = 0;
4519 return idx;
4520}
4521
4522
4523int
4524igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4525 struct rte_eth_ethertype_filter *filter,
4526 bool add)
4527{
4528 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4529 struct e1000_filter_info *filter_info =
4530 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4531 uint32_t etqf = 0;
4532 int ret;
4533
4534 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4535 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4536 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4537 " ethertype filter.", filter->ether_type);
4538 return -EINVAL;
4539 }
4540
4541 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4542 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4543 return -EINVAL;
4544 }
4545 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4546 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4547 return -EINVAL;
4548 }
4549
4550 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4551 if (ret >= 0 && add) {
4552 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4553 filter->ether_type);
4554 return -EEXIST;
4555 }
4556 if (ret < 0 && !add) {
4557 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4558 filter->ether_type);
4559 return -ENOENT;
4560 }
4561
4562 if (add) {
4563 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4564 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4565 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4566 ret = igb_ethertype_filter_insert(filter_info,
4567 filter->ether_type, etqf);
4568 if (ret < 0) {
4569 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4570 return -ENOSYS;
4571 }
4572 } else {
4573 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4574 if (ret < 0)
4575 return -ENOSYS;
4576 }
4577 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4578 E1000_WRITE_FLUSH(hw);
4579
4580 return 0;
4581}
4582
4583static int
4584eth_igb_flow_ops_get(struct rte_eth_dev *dev __rte_unused,
4585 const struct rte_flow_ops **ops)
4586{
4587 *ops = &igb_flow_ops;
4588 return 0;
4589}
4590
4591static int
4592eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4593 struct rte_ether_addr *mc_addr_set,
4594 uint32_t nb_mc_addr)
4595{
4596 struct e1000_hw *hw;
4597
4598 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4599 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4600 return 0;
4601}
4602
4603static uint64_t
4604igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4605{
4606 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4607 uint64_t systime_cycles;
4608
4609 switch (hw->mac.type) {
4610 case e1000_i210:
4611 case e1000_i211:
4612
4613
4614
4615
4616 E1000_READ_REG(hw, E1000_SYSTIMR);
4617
4618 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4619 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4620 * NSEC_PER_SEC;
4621 break;
4622 case e1000_82580:
4623 case e1000_i350:
4624 case e1000_i354:
4625
4626
4627
4628
4629 E1000_READ_REG(hw, E1000_SYSTIMR);
4630 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4631
4632 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4633 & 0xff) << 32;
4634 break;
4635 default:
4636 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4637 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4638 << 32;
4639 break;
4640 }
4641
4642 return systime_cycles;
4643}
4644
4645static uint64_t
4646igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4647{
4648 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4649 uint64_t rx_tstamp_cycles;
4650
4651 switch (hw->mac.type) {
4652 case e1000_i210:
4653 case e1000_i211:
4654
4655 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4656 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4657 * NSEC_PER_SEC;
4658 break;
4659 case e1000_82580:
4660 case e1000_i350:
4661 case e1000_i354:
4662 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4663
4664 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4665 & 0xff) << 32;
4666 break;
4667 default:
4668 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4669 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4670 << 32;
4671 break;
4672 }
4673
4674 return rx_tstamp_cycles;
4675}
4676
4677static uint64_t
4678igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4679{
4680 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4681 uint64_t tx_tstamp_cycles;
4682
4683 switch (hw->mac.type) {
4684 case e1000_i210:
4685 case e1000_i211:
4686
4687 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4688 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4689 * NSEC_PER_SEC;
4690 break;
4691 case e1000_82580:
4692 case e1000_i350:
4693 case e1000_i354:
4694 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4695
4696 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4697 & 0xff) << 32;
4698 break;
4699 default:
4700 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4701 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4702 << 32;
4703 break;
4704 }
4705
4706 return tx_tstamp_cycles;
4707}
4708
4709static void
4710igb_start_timecounters(struct rte_eth_dev *dev)
4711{
4712 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4713 struct e1000_adapter *adapter = dev->data->dev_private;
4714 uint32_t incval = 1;
4715 uint32_t shift = 0;
4716 uint64_t mask = E1000_CYCLECOUNTER_MASK;
4717
4718 switch (hw->mac.type) {
4719 case e1000_82580:
4720 case e1000_i350:
4721 case e1000_i354:
4722
4723 mask = (1ULL << 40) - 1;
4724
4725 case e1000_i210:
4726 case e1000_i211:
4727
4728
4729
4730
4731 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4732 break;
4733 case e1000_82576:
4734 incval = E1000_INCVALUE_82576;
4735 shift = IGB_82576_TSYNC_SHIFT;
4736 E1000_WRITE_REG(hw, E1000_TIMINCA,
4737 E1000_INCPERIOD_82576 | incval);
4738 break;
4739 default:
4740
4741 return;
4742 }
4743
4744 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4745 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4746 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4747
4748 adapter->systime_tc.cc_mask = mask;
4749 adapter->systime_tc.cc_shift = shift;
4750 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4751
4752 adapter->rx_tstamp_tc.cc_mask = mask;
4753 adapter->rx_tstamp_tc.cc_shift = shift;
4754 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4755
4756 adapter->tx_tstamp_tc.cc_mask = mask;
4757 adapter->tx_tstamp_tc.cc_shift = shift;
4758 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4759}
4760
4761static int
4762igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4763{
4764 struct e1000_adapter *adapter = dev->data->dev_private;
4765
4766 adapter->systime_tc.nsec += delta;
4767 adapter->rx_tstamp_tc.nsec += delta;
4768 adapter->tx_tstamp_tc.nsec += delta;
4769
4770 return 0;
4771}
4772
4773static int
4774igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4775{
4776 uint64_t ns;
4777 struct e1000_adapter *adapter = dev->data->dev_private;
4778
4779 ns = rte_timespec_to_ns(ts);
4780
4781
4782 adapter->systime_tc.nsec = ns;
4783 adapter->rx_tstamp_tc.nsec = ns;
4784 adapter->tx_tstamp_tc.nsec = ns;
4785
4786 return 0;
4787}
4788
4789static int
4790igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4791{
4792 uint64_t ns, systime_cycles;
4793 struct e1000_adapter *adapter = dev->data->dev_private;
4794
4795 systime_cycles = igb_read_systime_cyclecounter(dev);
4796 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4797 *ts = rte_ns_to_timespec(ns);
4798
4799 return 0;
4800}
4801
4802static int
4803igb_timesync_enable(struct rte_eth_dev *dev)
4804{
4805 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4806 uint32_t tsync_ctl;
4807 uint32_t tsauxc;
4808
4809
4810 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4811
4812 switch (hw->mac.type) {
4813 case e1000_82580:
4814 case e1000_i350:
4815 case e1000_i354:
4816 case e1000_i210:
4817 case e1000_i211:
4818 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4819
4820 case e1000_82576:
4821 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4822 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4823 break;
4824 default:
4825
4826 return -ENOTSUP;
4827 }
4828
4829
4830 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4831 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4832 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4833
4834 igb_start_timecounters(dev);
4835
4836
4837 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4838 (RTE_ETHER_TYPE_1588 |
4839 E1000_ETQF_FILTER_ENABLE |
4840 E1000_ETQF_1588));
4841
4842
4843 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4844 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4845 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4846
4847
4848 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4849 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4850 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4851
4852 return 0;
4853}
4854
4855static int
4856igb_timesync_disable(struct rte_eth_dev *dev)
4857{
4858 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4859 uint32_t tsync_ctl;
4860
4861
4862 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4863 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4864 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4865
4866
4867 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4868 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4869 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4870
4871
4872 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4873
4874
4875 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4876
4877 return 0;
4878}
4879
4880static int
4881igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4882 struct timespec *timestamp,
4883 uint32_t flags __rte_unused)
4884{
4885 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4886 struct e1000_adapter *adapter = dev->data->dev_private;
4887 uint32_t tsync_rxctl;
4888 uint64_t rx_tstamp_cycles;
4889 uint64_t ns;
4890
4891 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4892 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4893 return -EINVAL;
4894
4895 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4896 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4897 *timestamp = rte_ns_to_timespec(ns);
4898
4899 return 0;
4900}
4901
4902static int
4903igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4904 struct timespec *timestamp)
4905{
4906 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4907 struct e1000_adapter *adapter = dev->data->dev_private;
4908 uint32_t tsync_txctl;
4909 uint64_t tx_tstamp_cycles;
4910 uint64_t ns;
4911
4912 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4913 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4914 return -EINVAL;
4915
4916 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4917 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4918 *timestamp = rte_ns_to_timespec(ns);
4919
4920 return 0;
4921}
4922
4923static int
4924eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4925{
4926 int count = 0;
4927 int g_ind = 0;
4928 const struct reg_info *reg_group;
4929
4930 while ((reg_group = igb_regs[g_ind++]))
4931 count += igb_reg_group_count(reg_group);
4932
4933 return count;
4934}
4935
4936static int
4937igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4938{
4939 int count = 0;
4940 int g_ind = 0;
4941 const struct reg_info *reg_group;
4942
4943 while ((reg_group = igbvf_regs[g_ind++]))
4944 count += igb_reg_group_count(reg_group);
4945
4946 return count;
4947}
4948
4949static int
4950eth_igb_get_regs(struct rte_eth_dev *dev,
4951 struct rte_dev_reg_info *regs)
4952{
4953 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4954 uint32_t *data = regs->data;
4955 int g_ind = 0;
4956 int count = 0;
4957 const struct reg_info *reg_group;
4958
4959 if (data == NULL) {
4960 regs->length = eth_igb_get_reg_length(dev);
4961 regs->width = sizeof(uint32_t);
4962 return 0;
4963 }
4964
4965
4966 if ((regs->length == 0) ||
4967 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4968 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4969 hw->device_id;
4970 while ((reg_group = igb_regs[g_ind++]))
4971 count += igb_read_regs_group(dev, &data[count],
4972 reg_group);
4973 return 0;
4974 }
4975
4976 return -ENOTSUP;
4977}
4978
4979static int
4980igbvf_get_regs(struct rte_eth_dev *dev,
4981 struct rte_dev_reg_info *regs)
4982{
4983 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4984 uint32_t *data = regs->data;
4985 int g_ind = 0;
4986 int count = 0;
4987 const struct reg_info *reg_group;
4988
4989 if (data == NULL) {
4990 regs->length = igbvf_get_reg_length(dev);
4991 regs->width = sizeof(uint32_t);
4992 return 0;
4993 }
4994
4995
4996 if ((regs->length == 0) ||
4997 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
4998 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4999 hw->device_id;
5000 while ((reg_group = igbvf_regs[g_ind++]))
5001 count += igb_read_regs_group(dev, &data[count],
5002 reg_group);
5003 return 0;
5004 }
5005
5006 return -ENOTSUP;
5007}
5008
5009static int
5010eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5011{
5012 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5013
5014
5015 return hw->nvm.word_size * 2;
5016}
5017
5018static int
5019eth_igb_get_eeprom(struct rte_eth_dev *dev,
5020 struct rte_dev_eeprom_info *in_eeprom)
5021{
5022 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5023 struct e1000_nvm_info *nvm = &hw->nvm;
5024 uint16_t *data = in_eeprom->data;
5025 int first, length;
5026
5027 first = in_eeprom->offset >> 1;
5028 length = in_eeprom->length >> 1;
5029 if ((first >= hw->nvm.word_size) ||
5030 ((first + length) >= hw->nvm.word_size))
5031 return -EINVAL;
5032
5033 in_eeprom->magic = hw->vendor_id |
5034 ((uint32_t)hw->device_id << 16);
5035
5036 if ((nvm->ops.read) == NULL)
5037 return -ENOTSUP;
5038
5039 return nvm->ops.read(hw, first, length, data);
5040}
5041
5042static int
5043eth_igb_set_eeprom(struct rte_eth_dev *dev,
5044 struct rte_dev_eeprom_info *in_eeprom)
5045{
5046 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5047 struct e1000_nvm_info *nvm = &hw->nvm;
5048 uint16_t *data = in_eeprom->data;
5049 int first, length;
5050
5051 first = in_eeprom->offset >> 1;
5052 length = in_eeprom->length >> 1;
5053 if ((first >= hw->nvm.word_size) ||
5054 ((first + length) >= hw->nvm.word_size))
5055 return -EINVAL;
5056
5057 in_eeprom->magic = (uint32_t)hw->vendor_id |
5058 ((uint32_t)hw->device_id << 16);
5059
5060 if ((nvm->ops.write) == NULL)
5061 return -ENOTSUP;
5062 return nvm->ops.write(hw, first, length, data);
5063}
5064
5065static int
5066eth_igb_get_module_info(struct rte_eth_dev *dev,
5067 struct rte_eth_dev_module_info *modinfo)
5068{
5069 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5070
5071 uint32_t status = 0;
5072 uint16_t sff8472_rev, addr_mode;
5073 bool page_swap = false;
5074
5075 if (hw->phy.media_type == e1000_media_type_copper ||
5076 hw->phy.media_type == e1000_media_type_unknown)
5077 return -EOPNOTSUPP;
5078
5079
5080 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5081 if (status)
5082 return -EIO;
5083
5084
5085 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5086 if (status)
5087 return -EIO;
5088
5089
5090 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5091 PMD_DRV_LOG(ERR,
5092 "Address change required to access page 0xA2, "
5093 "but not supported. Please report the module "
5094 "type to the driver maintainers.\n");
5095 page_swap = true;
5096 }
5097
5098 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5099
5100 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5101 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5102 } else {
5103
5104 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5105 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5106 }
5107
5108 return 0;
5109}
5110
5111static int
5112eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5113 struct rte_dev_eeprom_info *info)
5114{
5115 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5116
5117 uint32_t status = 0;
5118 uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5119 u16 first_word, last_word;
5120 int i = 0;
5121
5122 first_word = info->offset >> 1;
5123 last_word = (info->offset + info->length - 1) >> 1;
5124
5125
5126 for (i = 0; i < last_word - first_word + 1; i++) {
5127 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5128 &dataword[i]);
5129 if (status) {
5130
5131 return -EIO;
5132 }
5133
5134 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5135 }
5136
5137 memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5138
5139 return 0;
5140}
5141
5142static int
5143eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5144{
5145 struct e1000_hw *hw =
5146 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5147 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5148 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5149 uint32_t vec = E1000_MISC_VEC_ID;
5150
5151 if (rte_intr_allow_others(intr_handle))
5152 vec = E1000_RX_VEC_START;
5153
5154 uint32_t mask = 1 << (queue_id + vec);
5155
5156 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5157 E1000_WRITE_FLUSH(hw);
5158
5159 return 0;
5160}
5161
5162static int
5163eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5164{
5165 struct e1000_hw *hw =
5166 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5167 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5168 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5169 uint32_t vec = E1000_MISC_VEC_ID;
5170
5171 if (rte_intr_allow_others(intr_handle))
5172 vec = E1000_RX_VEC_START;
5173
5174 uint32_t mask = 1 << (queue_id + vec);
5175 uint32_t regval;
5176
5177 regval = E1000_READ_REG(hw, E1000_EIMS);
5178 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5179 E1000_WRITE_FLUSH(hw);
5180
5181 rte_intr_ack(intr_handle);
5182
5183 return 0;
5184}
5185
5186static void
5187eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5188 uint8_t index, uint8_t offset)
5189{
5190 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5191
5192
5193 val &= ~((uint32_t)0xFF << offset);
5194
5195
5196 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5197
5198 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5199}
5200
5201static void
5202eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5203 uint8_t queue, uint8_t msix_vector)
5204{
5205 uint32_t tmp = 0;
5206
5207 if (hw->mac.type == e1000_82575) {
5208 if (direction == 0)
5209 tmp = E1000_EICR_RX_QUEUE0 << queue;
5210 else if (direction == 1)
5211 tmp = E1000_EICR_TX_QUEUE0 << queue;
5212 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5213 } else if (hw->mac.type == e1000_82576) {
5214 if ((direction == 0) || (direction == 1))
5215 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5216 ((queue & 0x8) << 1) +
5217 8 * direction);
5218 } else if ((hw->mac.type == e1000_82580) ||
5219 (hw->mac.type == e1000_i350) ||
5220 (hw->mac.type == e1000_i354) ||
5221 (hw->mac.type == e1000_i210) ||
5222 (hw->mac.type == e1000_i211)) {
5223 if ((direction == 0) || (direction == 1))
5224 eth_igb_write_ivar(hw, msix_vector,
5225 queue >> 1,
5226 ((queue & 0x1) << 4) +
5227 8 * direction);
5228 }
5229}
5230
5231
5232
5233
5234
5235static void
5236eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5237{
5238 int queue_id;
5239 uint32_t tmpval, regval, intr_mask;
5240 struct e1000_hw *hw =
5241 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5242 uint32_t vec = E1000_MISC_VEC_ID;
5243 uint32_t base = E1000_MISC_VEC_ID;
5244 uint32_t misc_shift = 0;
5245 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5246 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5247
5248
5249
5250
5251 if (!rte_intr_dp_is_en(intr_handle))
5252 return;
5253
5254 if (rte_intr_allow_others(intr_handle)) {
5255 vec = base = E1000_RX_VEC_START;
5256 misc_shift = 1;
5257 }
5258
5259
5260 if (hw->mac.type == e1000_82575) {
5261 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5262
5263 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5264
5265
5266 tmpval |= E1000_CTRL_EXT_EIAME;
5267 tmpval |= E1000_CTRL_EXT_IRCA;
5268
5269 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5270
5271
5272 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5273 regval = E1000_READ_REG(hw, E1000_EIAC);
5274 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5275 regval = E1000_READ_REG(hw, E1000_EIAM);
5276 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5277 } else if ((hw->mac.type == e1000_82576) ||
5278 (hw->mac.type == e1000_82580) ||
5279 (hw->mac.type == e1000_i350) ||
5280 (hw->mac.type == e1000_i354) ||
5281 (hw->mac.type == e1000_i210) ||
5282 (hw->mac.type == e1000_i211)) {
5283
5284 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5285 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5286 E1000_GPIE_NSICR);
5287 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5288 misc_shift;
5289
5290 if (dev->data->dev_conf.intr_conf.lsc != 0)
5291 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5292
5293 regval = E1000_READ_REG(hw, E1000_EIAC);
5294 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5295
5296
5297 regval = E1000_READ_REG(hw, E1000_EIMS);
5298 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5299 tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8;
5300 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5301 }
5302
5303
5304
5305
5306 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5307 misc_shift;
5308
5309 if (dev->data->dev_conf.intr_conf.lsc != 0)
5310 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5311
5312 regval = E1000_READ_REG(hw, E1000_EIAM);
5313 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5314
5315 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5316 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5317 intr_handle->intr_vec[queue_id] = vec;
5318 if (vec < base + intr_handle->nb_efd - 1)
5319 vec++;
5320 }
5321
5322 E1000_WRITE_FLUSH(hw);
5323}
5324
5325
5326static inline void
5327igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5328{
5329 struct e1000_filter_info *filter_info =
5330 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5331 struct e1000_5tuple_filter *p_5tuple;
5332 struct e1000_2tuple_filter *p_2tuple;
5333
5334 TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5335 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5336 }
5337
5338 TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5339 igb_inject_2uple_filter(dev, p_2tuple);
5340 }
5341}
5342
5343
5344static inline void
5345igb_syn_filter_restore(struct rte_eth_dev *dev)
5346{
5347 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5348 struct e1000_filter_info *filter_info =
5349 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5350 uint32_t synqf;
5351
5352 synqf = filter_info->syn_info;
5353
5354 if (synqf & E1000_SYN_FILTER_ENABLE) {
5355 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5356 E1000_WRITE_FLUSH(hw);
5357 }
5358}
5359
5360
5361static inline void
5362igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5363{
5364 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5365 struct e1000_filter_info *filter_info =
5366 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5367 int i;
5368
5369 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5370 if (filter_info->ethertype_mask & (1 << i)) {
5371 E1000_WRITE_REG(hw, E1000_ETQF(i),
5372 filter_info->ethertype_filters[i].etqf);
5373 E1000_WRITE_FLUSH(hw);
5374 }
5375 }
5376}
5377
5378
5379static inline void
5380igb_flex_filter_restore(struct rte_eth_dev *dev)
5381{
5382 struct e1000_filter_info *filter_info =
5383 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5384 struct e1000_flex_filter *flex_filter;
5385
5386 TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5387 igb_inject_flex_filter(dev, flex_filter);
5388 }
5389}
5390
5391
5392static inline void
5393igb_rss_filter_restore(struct rte_eth_dev *dev)
5394{
5395 struct e1000_filter_info *filter_info =
5396 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5397
5398 if (filter_info->rss_info.conf.queue_num)
5399 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5400}
5401
5402
5403static int
5404igb_filter_restore(struct rte_eth_dev *dev)
5405{
5406 igb_ntuple_filter_restore(dev);
5407 igb_ethertype_filter_restore(dev);
5408 igb_syn_filter_restore(dev);
5409 igb_flex_filter_restore(dev);
5410 igb_rss_filter_restore(dev);
5411
5412 return 0;
5413}
5414
5415RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5416RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5417RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5418RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5419RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5420RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");
5421
