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5#ifndef _HINIC_PMD_EQS_H_
6#define _HINIC_PMD_EQS_H_
7
8#define HINIC_EQ_PAGE_SIZE 0x00001000
9
10#define HINIC_AEQN_START 0
11#define HINIC_MAX_AEQS 4
12#define HINIC_MIN_AEQS 2
13#define HINIC_AEQN_0 0
14#define HINIC_AEQN_1 1
15#define HINIC_AEQN_2 2
16
17#define HINIC_EQ_MAX_PAGES 8
18
19#define HINIC_AEQE_SIZE 64
20#define HINIC_CEQE_SIZE 4
21
22#define HINIC_AEQE_DESC_SIZE 4
23#define HINIC_AEQE_DATA_SIZE \
24 (HINIC_AEQE_SIZE - HINIC_AEQE_DESC_SIZE)
25
26#define HINIC_DEFAULT_AEQ_LEN 64
27
28#define GET_EQ_ELEMENT(eq, idx) \
29 (((u8 *)(eq)->virt_addr[(idx) / (eq)->num_elem_in_pg]) + \
30 (((u32)(idx) & ((eq)->num_elem_in_pg - 1)) * (eq)->elem_size))
31
32#define GET_AEQ_ELEM(eq, idx) \
33 ((struct hinic_aeq_elem *)GET_EQ_ELEMENT((eq), (idx)))
34
35#define GET_CEQ_ELEM(eq, idx) ((u32 *)GET_EQ_ELEMENT((eq), (idx)))
36
37enum hinic_eq_intr_mode {
38 HINIC_INTR_MODE_ARMED,
39 HINIC_INTR_MODE_ALWAYS,
40};
41
42enum hinic_eq_ci_arm_state {
43 HINIC_EQ_NOT_ARMED,
44 HINIC_EQ_ARMED,
45};
46
47enum hinic_aeq_type {
48 HINIC_HW_INTER_INT = 0,
49 HINIC_MBX_FROM_FUNC = 1,
50 HINIC_MSG_FROM_MGMT_CPU = 2,
51 HINIC_API_RSP = 3,
52 HINIC_API_CHAIN_STS = 4,
53 HINIC_MBX_SEND_RSLT = 5,
54 HINIC_MAX_AEQ_EVENTS
55};
56
57#define HINIC_RETRY_NUM (10)
58
59struct hinic_eq {
60 struct hinic_hwdev *hwdev;
61 u16 q_id;
62 u16 type;
63 u32 page_size;
64 u16 eq_len;
65
66 u16 cons_idx;
67 u16 wrapped;
68
69 u16 elem_size;
70 u16 num_pages;
71 u32 num_elem_in_pg;
72
73 struct irq_info eq_irq;
74
75 dma_addr_t *dma_addr;
76 u8 **virt_addr;
77
78 u16 poll_retry_nr;
79};
80
81struct hinic_aeq_elem {
82 u8 aeqe_data[HINIC_AEQE_DATA_SIZE];
83 u32 desc;
84};
85
86struct hinic_aeqs {
87 struct hinic_hwdev *hwdev;
88 u16 poll_retry_nr;
89
90 struct hinic_eq aeq[HINIC_MAX_AEQS];
91 u16 num_aeqs;
92};
93
94void eq_update_ci(struct hinic_eq *eq);
95
96void hinic_dump_aeq_info(struct hinic_hwdev *hwdev);
97
98int hinic_comm_aeqs_init(struct hinic_hwdev *hwdev);
99
100void hinic_comm_aeqs_free(struct hinic_hwdev *hwdev);
101
102#endif
103
