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4
5#ifndef _HNS3_CMD_H_
6#define _HNS3_CMD_H_
7
8#include <stdint.h>
9
10#define HNS3_CMDQ_TX_TIMEOUT 30000
11#define HNS3_CMDQ_CLEAR_WAIT_TIME 200
12#define HNS3_CMDQ_RX_INVLD_B 0
13#define HNS3_CMDQ_RX_OUTVLD_B 1
14#define HNS3_CMD_DESC_ALIGNMENT 4096
15#define HNS3_CMD_FLAG_NEXT BIT(2)
16
17struct hns3_hw;
18
19#define HNS3_CMD_DESC_DATA_NUM 6
20struct hns3_cmd_desc {
21 uint16_t opcode;
22 uint16_t flag;
23 uint16_t retval;
24 uint16_t rsv;
25 uint32_t data[HNS3_CMD_DESC_DATA_NUM];
26};
27
28struct hns3_cmq_ring {
29 uint64_t desc_dma_addr;
30 struct hns3_cmd_desc *desc;
31 struct hns3_hw *hw;
32
33 uint16_t buf_size;
34 uint16_t desc_num;
35 uint32_t next_to_use;
36 uint32_t next_to_clean;
37 uint8_t ring_type;
38 rte_spinlock_t lock;
39
40 const void *zone;
41};
42
43enum hns3_cmd_return_status {
44 HNS3_CMD_EXEC_SUCCESS = 0,
45 HNS3_CMD_NO_AUTH = 1,
46 HNS3_CMD_NOT_SUPPORTED = 2,
47 HNS3_CMD_QUEUE_FULL = 3,
48 HNS3_CMD_NEXT_ERR = 4,
49 HNS3_CMD_UNEXE_ERR = 5,
50 HNS3_CMD_PARA_ERR = 6,
51 HNS3_CMD_RESULT_ERR = 7,
52 HNS3_CMD_TIMEOUT = 8,
53 HNS3_CMD_HILINK_ERR = 9,
54 HNS3_CMD_QUEUE_ILLEGAL = 10,
55 HNS3_CMD_INVALID = 11,
56 HNS3_CMD_ROH_CHECK_FAIL = 12
57};
58
59struct hns3_misc_vector {
60 uint8_t *addr;
61 int vector_irq;
62};
63
64struct hns3_cmq {
65 struct hns3_cmq_ring csq;
66 struct hns3_cmq_ring crq;
67 uint16_t tx_timeout;
68 enum hns3_cmd_return_status last_status;
69};
70
71enum hns3_opcode_type {
72
73 HNS3_OPC_QUERY_FW_VER = 0x0001,
74 HNS3_OPC_CFG_RST_TRIGGER = 0x0020,
75 HNS3_OPC_GBL_RST_STATUS = 0x0021,
76 HNS3_OPC_QUERY_FUNC_STATUS = 0x0022,
77 HNS3_OPC_QUERY_PF_RSRC = 0x0023,
78 HNS3_OPC_QUERY_VF_RSRC = 0x0024,
79 HNS3_OPC_GET_CFG_PARAM = 0x0025,
80 HNS3_OPC_PF_RST_DONE = 0x0026,
81
82 HNS3_OPC_STATS_64_BIT = 0x0030,
83 HNS3_OPC_STATS_32_BIT = 0x0031,
84 HNS3_OPC_STATS_MAC = 0x0032,
85 HNS3_OPC_QUERY_MAC_REG_NUM = 0x0033,
86 HNS3_OPC_STATS_MAC_ALL = 0x0034,
87
88 HNS3_OPC_QUERY_REG_NUM = 0x0040,
89 HNS3_OPC_QUERY_32_BIT_REG = 0x0041,
90 HNS3_OPC_QUERY_64_BIT_REG = 0x0042,
91 HNS3_OPC_DFX_BD_NUM = 0x0043,
92 HNS3_OPC_DFX_BIOS_COMMON_REG = 0x0044,
93 HNS3_OPC_DFX_SSU_REG_0 = 0x0045,
94 HNS3_OPC_DFX_SSU_REG_1 = 0x0046,
95 HNS3_OPC_DFX_IGU_EGU_REG = 0x0047,
96 HNS3_OPC_DFX_RPU_REG_0 = 0x0048,
97 HNS3_OPC_DFX_RPU_REG_1 = 0x0049,
98 HNS3_OPC_DFX_NCSI_REG = 0x004A,
99 HNS3_OPC_DFX_RTC_REG = 0x004B,
100 HNS3_OPC_DFX_PPP_REG = 0x004C,
101 HNS3_OPC_DFX_RCB_REG = 0x004D,
102 HNS3_OPC_DFX_TQP_REG = 0x004E,
103 HNS3_OPC_DFX_SSU_REG_2 = 0x004F,
104
105 HNS3_OPC_QUERY_DEV_SPECS = 0x0050,
106
107 HNS3_OPC_SSU_DROP_REG = 0x0065,
108
109
110 HNS3_OPC_CONFIG_MAC_MODE = 0x0301,
111 HNS3_OPC_CONFIG_AN_MODE = 0x0304,
112 HNS3_OPC_QUERY_LINK_STATUS = 0x0307,
113 HNS3_OPC_CONFIG_MAX_FRM_SIZE = 0x0308,
114 HNS3_OPC_CONFIG_SPEED_DUP = 0x0309,
115 HNS3_OPC_QUERY_MAC_TNL_INT = 0x0310,
116 HNS3_OPC_MAC_TNL_INT_EN = 0x0311,
117 HNS3_OPC_CLEAR_MAC_TNL_INT = 0x0312,
118 HNS3_OPC_CONFIG_FEC_MODE = 0x031A,
119
120
121 HNS3_OPC_PTP_INT_EN = 0x0501,
122 HNS3_OPC_CFG_PTP_MODE = 0x0507,
123
124
125 HNS3_OPC_CFG_MAC_PAUSE_EN = 0x0701,
126 HNS3_OPC_CFG_PFC_PAUSE_EN = 0x0702,
127 HNS3_OPC_CFG_MAC_PARA = 0x0703,
128 HNS3_OPC_CFG_PFC_PARA = 0x0704,
129 HNS3_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705,
130 HNS3_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706,
131 HNS3_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707,
132 HNS3_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708,
133 HNS3_OPC_PRI_TO_TC_MAPPING = 0x0709,
134 HNS3_OPC_QOS_MAP = 0x070A,
135
136
137 HNS3_OPC_TM_PG_TO_PRI_LINK = 0x0804,
138 HNS3_OPC_TM_QS_TO_PRI_LINK = 0x0805,
139 HNS3_OPC_TM_NQ_TO_QS_LINK = 0x0806,
140 HNS3_OPC_TM_RQ_TO_QS_LINK = 0x0807,
141 HNS3_OPC_TM_PORT_WEIGHT = 0x0808,
142 HNS3_OPC_TM_PG_WEIGHT = 0x0809,
143 HNS3_OPC_TM_QS_WEIGHT = 0x080A,
144 HNS3_OPC_TM_PRI_WEIGHT = 0x080B,
145 HNS3_OPC_TM_PRI_C_SHAPPING = 0x080C,
146 HNS3_OPC_TM_PRI_P_SHAPPING = 0x080D,
147 HNS3_OPC_TM_PG_C_SHAPPING = 0x080E,
148 HNS3_OPC_TM_PG_P_SHAPPING = 0x080F,
149 HNS3_OPC_TM_PORT_SHAPPING = 0x0810,
150 HNS3_OPC_TM_PG_SCH_MODE_CFG = 0x0812,
151 HNS3_OPC_TM_PRI_SCH_MODE_CFG = 0x0813,
152 HNS3_OPC_TM_QS_SCH_MODE_CFG = 0x0814,
153 HNS3_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
154 HNS3_OPC_ETS_TC_WEIGHT = 0x0843,
155 HNS3_OPC_QSET_DFX_STS = 0x0844,
156 HNS3_OPC_PRI_DFX_STS = 0x0845,
157 HNS3_OPC_PG_DFX_STS = 0x0846,
158 HNS3_OPC_PORT_DFX_STS = 0x0847,
159 HNS3_OPC_SCH_NQ_CNT = 0x0848,
160 HNS3_OPC_SCH_RQ_CNT = 0x0849,
161 HNS3_OPC_TM_INTERNAL_STS = 0x0850,
162 HNS3_OPC_TM_INTERNAL_CNT = 0x0851,
163 HNS3_OPC_TM_INTERNAL_STS_1 = 0x0852,
164
165 HNS3_OPC_TM_PORT_LIMIT_RATE = 0x0870,
166 HNS3_OPC_TM_TC_LIMIT_RATE = 0x0871,
167
168
169 HNS3_OPC_MBX_VF_TO_PF = 0x2001,
170
171
172 HNS3_OPC_TX_BUFF_ALLOC = 0x0901,
173 HNS3_OPC_RX_PRIV_BUFF_ALLOC = 0x0902,
174 HNS3_OPC_RX_PRIV_WL_ALLOC = 0x0903,
175 HNS3_OPC_RX_COM_THRD_ALLOC = 0x0904,
176 HNS3_OPC_RX_COM_WL_ALLOC = 0x0905,
177
178
179 HNS3_OPC_SET_TQP_MAP = 0x0A01,
180
181
182 HNS3_OPC_QUERY_TX_STATUS = 0x0B03,
183 HNS3_OPC_QUERY_RX_STATUS = 0x0B13,
184 HNS3_OPC_CFG_COM_TQP_QUEUE = 0x0B20,
185 HNS3_OPC_RESET_TQP_QUEUE = 0x0B22,
186 HNS3_OPC_RESET_TQP_QUEUE_INDEP = 0x0B23,
187
188
189 HNS3_OPC_TSO_GENERIC_CONFIG = 0x0C01,
190 HNS3_OPC_GRO_GENERIC_CONFIG = 0x0C10,
191
192
193 HNS3_OPC_RSS_GENERIC_CONFIG = 0x0D01,
194 HNS3_OPC_RSS_INPUT_TUPLE = 0x0D02,
195 HNS3_OPC_RSS_INDIR_TABLE = 0x0D07,
196 HNS3_OPC_RSS_TC_MODE = 0x0D08,
197
198
199 HNS3_OPC_CFG_PROMISC_MODE = 0x0E01,
200
201
202 HNS3_OPC_VLAN_PORT_TX_CFG = 0x0F01,
203 HNS3_OPC_VLAN_PORT_RX_CFG = 0x0F02,
204
205
206 HNS3_OPC_MAC_VLAN_ADD = 0x1000,
207 HNS3_OPC_MAC_VLAN_REMOVE = 0x1001,
208 HNS3_OPC_MAC_VLAN_TYPE_ID = 0x1002,
209 HNS3_OPC_MAC_VLAN_INSERT = 0x1003,
210 HNS3_OPC_MAC_VLAN_ALLOCATE = 0x1004,
211 HNS3_OPC_MAC_ETHTYPE_ADD = 0x1010,
212
213
214 HNS3_OPC_VLAN_FILTER_CTRL = 0x1100,
215 HNS3_OPC_VLAN_FILTER_PF_CFG = 0x1101,
216 HNS3_OPC_VLAN_FILTER_VF_CFG = 0x1102,
217
218
219 HNS3_OPC_FD_MODE_CTRL = 0x1200,
220 HNS3_OPC_FD_GET_ALLOCATION = 0x1201,
221 HNS3_OPC_FD_KEY_CONFIG = 0x1202,
222 HNS3_OPC_FD_TCAM_OP = 0x1203,
223 HNS3_OPC_FD_AD_OP = 0x1204,
224 HNS3_OPC_FD_COUNTER_OP = 0x1205,
225
226
227 HNS3_OPC_CLEAR_HW_STATE = 0x700B,
228
229
230 HNS3_OPC_FIRMWARE_COMPAT_CFG = 0x701A,
231
232 HNS3_OPC_PHY_PARAM_CFG = 0x7025,
233
234
235 HNS3_OPC_GET_SFP_EEPROM = 0x7100,
236 HNS3_OPC_GET_SFP_EXIST = 0x7101,
237 HNS3_OPC_GET_SFP_INFO = 0x7104,
238
239
240 HNS3_OPC_ADD_RING_TO_VECTOR = 0x1503,
241 HNS3_OPC_DEL_RING_TO_VECTOR = 0x1504,
242
243
244 HNS3_OPC_MAC_COMMON_INT_EN = 0x030E,
245 HNS3_OPC_TM_SCH_ECC_INT_EN = 0x0829,
246 HNS3_OPC_SSU_ECC_INT_CMD = 0x0989,
247 HNS3_OPC_SSU_COMMON_INT_CMD = 0x098C,
248 HNS3_OPC_PPU_MPF_ECC_INT_CMD = 0x0B40,
249 HNS3_OPC_PPU_MPF_OTHER_INT_CMD = 0x0B41,
250 HNS3_OPC_PPU_PF_OTHER_INT_CMD = 0x0B42,
251 HNS3_OPC_COMMON_ECC_INT_CFG = 0x1505,
252 HNS3_OPC_QUERY_RAS_INT_STS_BD_NUM = 0x1510,
253 HNS3_OPC_QUERY_CLEAR_MPF_RAS_INT = 0x1511,
254 HNS3_OPC_QUERY_CLEAR_PF_RAS_INT = 0x1512,
255 HNS3_OPC_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,
256 HNS3_OPC_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514,
257 HNS3_OPC_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515,
258 HNS3_OPC_QUERY_ALL_ERR_BD_NUM = 0x1516,
259 HNS3_OPC_QUERY_ALL_ERR_INFO = 0x1517,
260 HNS3_OPC_IGU_EGU_TNL_INT_EN = 0x1803,
261 HNS3_OPC_IGU_COMMON_INT_EN = 0x1806,
262 HNS3_OPC_TM_QCN_MEM_INT_CFG = 0x1A14,
263 HNS3_OPC_PPP_CMD0_INT_CMD = 0x2100,
264 HNS3_OPC_PPP_CMD1_INT_CMD = 0x2101,
265 HNS3_OPC_NCSI_INT_EN = 0x2401,
266};
267
268#define HNS3_CMD_FLAG_IN BIT(0)
269#define HNS3_CMD_FLAG_OUT BIT(1)
270#define HNS3_CMD_FLAG_NEXT BIT(2)
271#define HNS3_CMD_FLAG_WR BIT(3)
272#define HNS3_CMD_FLAG_NO_INTR BIT(4)
273#define HNS3_CMD_FLAG_ERR_INTR BIT(5)
274
275#define HNS3_MPF_RAS_INT_MIN_BD_NUM 10
276#define HNS3_PF_RAS_INT_MIN_BD_NUM 4
277#define HNS3_MPF_MSIX_INT_MIN_BD_NUM 10
278#define HNS3_PF_MSIX_INT_MIN_BD_NUM 4
279
280#define HNS3_BUF_SIZE_UNIT 256
281#define HNS3_BUF_MUL_BY 2
282#define HNS3_BUF_DIV_BY 2
283#define NEED_RESERVE_TC_NUM 2
284#define BUF_MAX_PERCENT 100
285#define BUF_RESERVE_PERCENT 90
286
287#define HNS3_MAX_TC_NUM 8
288#define HNS3_TC0_PRI_BUF_EN_B 15
289#define HNS3_BUF_UNIT_S 7
290#define HNS3_TX_BUFF_RSV_NUM 8
291struct hns3_tx_buff_alloc_cmd {
292 uint16_t tx_pkt_buff[HNS3_MAX_TC_NUM];
293 uint8_t tx_buff_rsv[HNS3_TX_BUFF_RSV_NUM];
294};
295
296struct hns3_rx_priv_buff_cmd {
297 uint16_t buf_num[HNS3_MAX_TC_NUM];
298 uint16_t shared_buf;
299 uint8_t rsv[6];
300};
301
302#define HNS3_FW_VERSION_BYTE3_S 24
303#define HNS3_FW_VERSION_BYTE3_M GENMASK(31, 24)
304#define HNS3_FW_VERSION_BYTE2_S 16
305#define HNS3_FW_VERSION_BYTE2_M GENMASK(23, 16)
306#define HNS3_FW_VERSION_BYTE1_S 8
307#define HNS3_FW_VERSION_BYTE1_M GENMASK(15, 8)
308#define HNS3_FW_VERSION_BYTE0_S 0
309#define HNS3_FW_VERSION_BYTE0_M GENMASK(7, 0)
310
311enum HNS3_CAPS_BITS {
312
313
314
315
316 HNS3_CAPS_FD_QUEUE_REGION_B = 2,
317 HNS3_CAPS_PTP_B,
318 HNS3_CAPS_PHY_IMP_B = 7,
319 HNS3_CAPS_TQP_TXRX_INDEP_B,
320 HNS3_CAPS_HW_PAD_B,
321 HNS3_CAPS_STASH_B,
322 HNS3_CAPS_UDP_TUNNEL_CSUM_B,
323 HNS3_CAPS_RAS_IMP_B,
324 HNS3_CAPS_RXD_ADV_LAYOUT_B = 15,
325 HNS3_CAPS_TM_B = 17,
326};
327
328
329enum HNS3VF_CAPS_BITS {
330
331
332
333
334 HNS3VF_CAPS_VLAN_FLT_MOD_B = 0,
335};
336
337enum HNS3_API_CAP_BITS {
338 HNS3_API_CAP_FLEX_RSS_TBL_B,
339};
340
341#define HNS3_QUERY_CAP_LENGTH 3
342struct hns3_query_version_cmd {
343 uint32_t firmware;
344 uint32_t hardware;
345 uint32_t api_caps;
346 uint32_t caps[HNS3_QUERY_CAP_LENGTH];
347};
348
349#define HNS3_RX_PRIV_EN_B 15
350#define HNS3_TC_NUM_ONE_DESC 4
351struct hns3_priv_wl {
352 uint16_t high;
353 uint16_t low;
354};
355
356struct hns3_rx_priv_wl_buf {
357 struct hns3_priv_wl tc_wl[HNS3_TC_NUM_ONE_DESC];
358};
359
360struct hns3_rx_com_thrd {
361 struct hns3_priv_wl com_thrd[HNS3_TC_NUM_ONE_DESC];
362};
363
364struct hns3_rx_com_wl {
365 struct hns3_priv_wl com_wl;
366};
367
368struct hns3_waterline {
369 uint32_t low;
370 uint32_t high;
371};
372
373struct hns3_tc_thrd {
374 uint32_t low;
375 uint32_t high;
376};
377
378struct hns3_priv_buf {
379 struct hns3_waterline wl;
380 uint32_t buf_size;
381 uint32_t tx_buf_size;
382 uint32_t enable;
383};
384
385struct hns3_shared_buf {
386 struct hns3_waterline self;
387 struct hns3_tc_thrd tc_thrd[HNS3_MAX_TC_NUM];
388 uint32_t buf_size;
389};
390
391struct hns3_pkt_buf_alloc {
392 struct hns3_priv_buf priv_buf[HNS3_MAX_TC_NUM];
393 struct hns3_shared_buf s_buf;
394};
395
396#define HNS3_RX_COM_WL_EN_B 15
397struct hns3_rx_com_wl_buf_cmd {
398 uint16_t high_wl;
399 uint16_t low_wl;
400 uint8_t rsv[20];
401};
402
403#define HNS3_RX_PKT_EN_B 15
404struct hns3_rx_pkt_buf_cmd {
405 uint16_t high_pkt;
406 uint16_t low_pkt;
407 uint8_t rsv[20];
408};
409
410#define HNS3_PF_STATE_DONE_B 0
411#define HNS3_PF_STATE_MAIN_B 1
412#define HNS3_PF_STATE_BOND_B 2
413#define HNS3_PF_STATE_MAC_N_B 6
414#define HNS3_PF_MAC_NUM_MASK 0x3
415#define HNS3_PF_STATE_MAIN BIT(HNS3_PF_STATE_MAIN_B)
416#define HNS3_PF_STATE_DONE BIT(HNS3_PF_STATE_DONE_B)
417#define HNS3_VF_RST_STATE_NUM 4
418struct hns3_func_status_cmd {
419 uint32_t vf_rst_state[HNS3_VF_RST_STATE_NUM];
420 uint8_t pf_state;
421 uint8_t mac_id;
422 uint8_t rsv1;
423 uint8_t pf_cnt_in_mac;
424 uint8_t pf_num;
425 uint8_t vf_num;
426 uint8_t rsv[2];
427};
428
429#define HNS3_PF_VEC_NUM_S 0
430#define HNS3_PF_VEC_NUM_M GENMASK(15, 0)
431#define HNS3_MIN_VECTOR_NUM 2
432struct hns3_pf_res_cmd {
433 uint16_t tqp_num;
434 uint16_t buf_size;
435 uint16_t msixcap_localid_ba_nic;
436 uint16_t nic_pf_intr_vector_number;
437 uint16_t roce_pf_intr_vector_number;
438 uint16_t pf_own_fun_number;
439 uint16_t tx_buf_size;
440 uint16_t dv_buf_size;
441
442 uint16_t ext_tqp_num;
443 uint16_t roh_pf_intr_vector_number;
444 uint32_t rsv[1];
445};
446
447#define HNS3_VF_VEC_NUM_S 0
448#define HNS3_VF_VEC_NUM_M GENMASK(7, 0)
449struct hns3_vf_res_cmd {
450 uint16_t tqp_num;
451 uint16_t reserved;
452 uint16_t msixcap_localid_ba_nic;
453 uint16_t msixcap_localid_ba_rocee;
454 uint16_t vf_intr_vector_number;
455 uint16_t rsv[7];
456};
457
458#define HNS3_UMV_SPC_ALC_B 0
459struct hns3_umv_spc_alc_cmd {
460 uint8_t allocate;
461 uint8_t rsv1[3];
462 uint32_t space_size;
463 uint8_t rsv2[16];
464};
465
466#define HNS3_CFG_OFFSET_S 0
467#define HNS3_CFG_OFFSET_M GENMASK(19, 0)
468#define HNS3_CFG_RD_LEN_S 24
469#define HNS3_CFG_RD_LEN_M GENMASK(27, 24)
470#define HNS3_CFG_RD_LEN_BYTES 16
471#define HNS3_CFG_RD_LEN_UNIT 4
472
473#define HNS3_CFG_TC_NUM_S 8
474#define HNS3_CFG_TC_NUM_M GENMASK(15, 8)
475#define HNS3_CFG_TQP_DESC_N_S 16
476#define HNS3_CFG_TQP_DESC_N_M GENMASK(31, 16)
477#define HNS3_CFG_PHY_ADDR_S 0
478#define HNS3_CFG_PHY_ADDR_M GENMASK(7, 0)
479#define HNS3_CFG_MEDIA_TP_S 8
480#define HNS3_CFG_MEDIA_TP_M GENMASK(15, 8)
481#define HNS3_CFG_RX_BUF_LEN_S 16
482#define HNS3_CFG_RX_BUF_LEN_M GENMASK(31, 16)
483#define HNS3_CFG_MAC_ADDR_H_S 0
484#define HNS3_CFG_MAC_ADDR_H_M GENMASK(15, 0)
485#define HNS3_CFG_DEFAULT_SPEED_S 16
486#define HNS3_CFG_DEFAULT_SPEED_M GENMASK(23, 16)
487#define HNS3_CFG_RSS_SIZE_S 24
488#define HNS3_CFG_RSS_SIZE_M GENMASK(31, 24)
489#define HNS3_CFG_SPEED_ABILITY_S 0
490#define HNS3_CFG_SPEED_ABILITY_M GENMASK(7, 0)
491#define HNS3_CFG_UMV_TBL_SPACE_S 16
492#define HNS3_CFG_UMV_TBL_SPACE_M GENMASK(31, 16)
493#define HNS3_CFG_EXT_RSS_SIZE_S 0
494#define HNS3_CFG_EXT_RSS_SIZE_M GENMASK(3, 0)
495
496#define HNS3_ACCEPT_TAG1_B 0
497#define HNS3_ACCEPT_UNTAG1_B 1
498#define HNS3_PORT_INS_TAG1_EN_B 2
499#define HNS3_PORT_INS_TAG2_EN_B 3
500#define HNS3_CFG_NIC_ROCE_SEL_B 4
501#define HNS3_ACCEPT_TAG2_B 5
502#define HNS3_ACCEPT_UNTAG2_B 6
503#define HNS3_TAG_SHIFT_MODE_EN_B 7
504
505#define HNS3_REM_TAG1_EN_B 0
506#define HNS3_REM_TAG2_EN_B 1
507#define HNS3_SHOW_TAG1_EN_B 2
508#define HNS3_SHOW_TAG2_EN_B 3
509#define HNS3_DISCARD_TAG1_EN_B 5
510#define HNS3_DISCARD_TAG2_EN_B 6
511
512
513#define HNS3_VF_NUM_PER_CMD 64
514#define HNS3_VF_NUM_PER_BYTE 8
515
516struct hns3_cfg_param_cmd {
517 uint32_t offset;
518 uint32_t rsv;
519 uint32_t param[4];
520};
521
522#define HNS3_VPORT_VTAG_RX_CFG_CMD_VF_BITMAP_NUM 8
523struct hns3_vport_vtag_rx_cfg_cmd {
524 uint8_t vport_vlan_cfg;
525 uint8_t vf_offset;
526 uint8_t rsv1[6];
527 uint8_t vf_bitmap[HNS3_VPORT_VTAG_RX_CFG_CMD_VF_BITMAP_NUM];
528 uint8_t rsv2[8];
529};
530
531struct hns3_vport_vtag_tx_cfg_cmd {
532 uint8_t vport_vlan_cfg;
533 uint8_t vf_offset;
534 uint8_t rsv1[2];
535 uint16_t def_vlan_tag1;
536 uint16_t def_vlan_tag2;
537 uint8_t vf_bitmap[8];
538 uint8_t rsv2[8];
539};
540
541
542struct hns3_vlan_filter_ctrl_cmd {
543 uint8_t vlan_type;
544 uint8_t vlan_fe;
545 uint8_t rsv1[2];
546 uint8_t vf_id;
547 uint8_t rsv2[19];
548};
549
550#define HNS3_VLAN_OFFSET_BITMAP_NUM 20
551struct hns3_vlan_filter_pf_cfg_cmd {
552 uint8_t vlan_offset;
553 uint8_t vlan_cfg;
554 uint8_t rsv[2];
555 uint8_t vlan_offset_bitmap[HNS3_VLAN_OFFSET_BITMAP_NUM];
556};
557
558#define HNS3_VLAN_FILTER_VF_CFG_CMD_VF_BITMAP_NUM 16
559struct hns3_vlan_filter_vf_cfg_cmd {
560 uint16_t vlan_id;
561 uint8_t resp_code;
562 uint8_t rsv;
563 uint8_t vlan_cfg;
564 uint8_t rsv1[3];
565 uint8_t vf_bitmap[HNS3_VLAN_FILTER_VF_CFG_CMD_VF_BITMAP_NUM];
566};
567
568struct hns3_tx_vlan_type_cfg_cmd {
569 uint16_t ot_vlan_type;
570 uint16_t in_vlan_type;
571 uint8_t rsv[20];
572};
573
574struct hns3_rx_vlan_type_cfg_cmd {
575 uint16_t ot_fst_vlan_type;
576 uint16_t ot_sec_vlan_type;
577 uint16_t in_fst_vlan_type;
578 uint16_t in_sec_vlan_type;
579 uint8_t rsv[16];
580};
581
582#define HNS3_TSO_MSS_MIN_S 0
583#define HNS3_TSO_MSS_MIN_M GENMASK(13, 0)
584
585#define HNS3_TSO_MSS_MAX_S 16
586#define HNS3_TSO_MSS_MAX_M GENMASK(29, 16)
587
588struct hns3_cfg_tso_status_cmd {
589 rte_le16_t tso_mss_min;
590 rte_le16_t tso_mss_max;
591 uint8_t rsv[20];
592};
593
594#define HNS3_GRO_EN_B 0
595struct hns3_cfg_gro_status_cmd {
596 rte_le16_t gro_en;
597 uint8_t rsv[22];
598};
599
600#define HNS3_TSO_MSS_MIN 256
601#define HNS3_TSO_MSS_MAX 9668
602
603#define HNS3_RSS_HASH_KEY_OFFSET_B 4
604
605#define HNS3_RSS_CFG_TBL_SIZE 16
606#define HNS3_RSS_HASH_KEY_NUM 16
607
608struct hns3_rss_generic_config_cmd {
609
610 uint8_t hash_config;
611 uint8_t rsv[7];
612 uint8_t hash_key[HNS3_RSS_HASH_KEY_NUM];
613};
614
615
616struct hns3_rss_input_tuple_cmd {
617 uint64_t tuple_field;
618 uint8_t rsv[16];
619};
620
621#define HNS3_RSS_CFG_TBL_SIZE 16
622#define HNS3_RSS_CFG_TBL_SIZE_H 4
623#define HNS3_RSS_CFG_TBL_BW_H 2
624#define HNS3_RSS_CFG_TBL_BW_L 8
625
626
627struct hns3_rss_indirection_table_cmd {
628 uint16_t start_table_index;
629 uint16_t rss_set_bitmap;
630 uint8_t rss_result_h[HNS3_RSS_CFG_TBL_SIZE_H];
631 uint8_t rss_result_l[HNS3_RSS_CFG_TBL_SIZE];
632};
633
634#define HNS3_RSS_TC_OFFSET_S 0
635#define HNS3_RSS_TC_OFFSET_M GENMASK(10, 0)
636#define HNS3_RSS_TC_SIZE_MSB_S 11
637#define HNS3_RSS_TC_SIZE_MSB_OFFSET 3
638#define HNS3_RSS_TC_SIZE_S 12
639#define HNS3_RSS_TC_SIZE_M GENMASK(14, 12)
640#define HNS3_RSS_TC_VALID_B 15
641
642
643struct hns3_rss_tc_mode_cmd {
644 uint16_t rss_tc_mode[HNS3_MAX_TC_NUM];
645 uint8_t rsv[8];
646};
647
648#define HNS3_LINK_STATUS_UP_B 0
649#define HNS3_LINK_STATUS_UP_M BIT(HNS3_LINK_STATUS_UP_B)
650struct hns3_link_status_cmd {
651 uint8_t status;
652 uint8_t rsv[23];
653};
654
655struct hns3_promisc_param {
656 uint8_t vf_id;
657 uint8_t enable;
658};
659
660#define HNS3_PROMISC_TX_EN_B BIT(4)
661#define HNS3_PROMISC_RX_EN_B BIT(5)
662#define HNS3_PROMISC_EN_B 1
663#define HNS3_PROMISC_EN_ALL 0x7
664#define HNS3_PROMISC_EN_UC 0x1
665#define HNS3_PROMISC_EN_MC 0x2
666#define HNS3_PROMISC_EN_BC 0x4
667struct hns3_promisc_cfg_cmd {
668 uint8_t flag;
669 uint8_t vf_id;
670 uint16_t rsv0;
671 uint8_t rsv1[20];
672};
673
674enum hns3_promisc_type {
675 HNS3_UNICAST = 1,
676 HNS3_MULTICAST = 2,
677 HNS3_BROADCAST = 3,
678};
679
680#define HNS3_LINK_EVENT_REPORT_EN_B 0
681#define HNS3_NCSI_ERROR_REPORT_EN_B 1
682#define HNS3_FIRMWARE_PHY_DRIVER_EN_B 2
683struct hns3_firmware_compat_cmd {
684 uint32_t compat;
685 uint8_t rsv[20];
686};
687
688
689#define HNS3_PHY_LINK_SPEED_10M_HD_BIT BIT(0)
690#define HNS3_PHY_LINK_SPEED_10M_BIT BIT(1)
691#define HNS3_PHY_LINK_SPEED_100M_HD_BIT BIT(2)
692#define HNS3_PHY_LINK_SPEED_100M_BIT BIT(3)
693#define HNS3_PHY_LINK_SPEED_1000M_BIT BIT(5)
694#define HNS3_PHY_LINK_MODE_AUTONEG_BIT BIT(6)
695#define HNS3_PHY_LINK_MODE_PAUSE_BIT BIT(13)
696#define HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT BIT(14)
697
698#define HNS3_PHY_PARAM_CFG_BD_NUM 2
699struct hns3_phy_params_bd0_cmd {
700 uint32_t speed;
701#define HNS3_PHY_DUPLEX_CFG_B 0
702 uint8_t duplex;
703#define HNS3_PHY_AUTONEG_CFG_B 0
704 uint8_t autoneg;
705 uint8_t eth_tp_mdix;
706 uint8_t eth_tp_mdix_ctrl;
707 uint8_t port;
708 uint8_t transceiver;
709 uint8_t phy_address;
710 uint8_t rsv;
711 uint32_t supported;
712 uint32_t advertising;
713 uint32_t lp_advertising;
714};
715
716struct hns3_phy_params_bd1_cmd {
717 uint8_t master_slave_cfg;
718 uint8_t master_slave_state;
719 uint8_t rsv1[2];
720 uint32_t rsv2[5];
721};
722
723#define HNS3_MAC_TX_EN_B 6
724#define HNS3_MAC_RX_EN_B 7
725#define HNS3_MAC_PAD_TX_B 11
726#define HNS3_MAC_PAD_RX_B 12
727#define HNS3_MAC_1588_TX_B 13
728#define HNS3_MAC_1588_RX_B 14
729#define HNS3_MAC_APP_LP_B 15
730#define HNS3_MAC_LINE_LP_B 16
731#define HNS3_MAC_FCS_TX_B 17
732#define HNS3_MAC_RX_OVERSIZE_TRUNCATE_B 18
733#define HNS3_MAC_RX_FCS_STRIP_B 19
734#define HNS3_MAC_RX_FCS_B 20
735#define HNS3_MAC_TX_UNDER_MIN_ERR_B 21
736#define HNS3_MAC_TX_OVERSIZE_TRUNCATE_B 22
737
738struct hns3_config_mac_mode_cmd {
739 uint32_t txrx_pad_fcs_loop_en;
740 uint8_t rsv[20];
741};
742
743#define HNS3_CFG_SPEED_10M 6
744#define HNS3_CFG_SPEED_100M 7
745#define HNS3_CFG_SPEED_1G 0
746#define HNS3_CFG_SPEED_10G 1
747#define HNS3_CFG_SPEED_25G 2
748#define HNS3_CFG_SPEED_40G 3
749#define HNS3_CFG_SPEED_50G 4
750#define HNS3_CFG_SPEED_100G 5
751#define HNS3_CFG_SPEED_200G 8
752
753#define HNS3_CFG_SPEED_S 0
754#define HNS3_CFG_SPEED_M GENMASK(5, 0)
755#define HNS3_CFG_DUPLEX_B 7
756#define HNS3_CFG_DUPLEX_M BIT(HNS3_CFG_DUPLEX_B)
757
758#define HNS3_CFG_MAC_SPEED_CHANGE_EN_B 0
759
760struct hns3_config_mac_speed_dup_cmd {
761 uint8_t speed_dup;
762 uint8_t mac_change_fec_en;
763 uint8_t rsv[22];
764};
765
766#define HNS3_TQP_ENABLE_B 0
767
768#define HNS3_MAC_CFG_AN_EN_B 0
769#define HNS3_MAC_CFG_AN_INT_EN_B 1
770#define HNS3_MAC_CFG_AN_INT_MSK_B 2
771#define HNS3_MAC_CFG_AN_INT_CLR_B 3
772#define HNS3_MAC_CFG_AN_RST_B 4
773
774#define HNS3_MAC_CFG_AN_EN BIT(HNS3_MAC_CFG_AN_EN_B)
775
776struct hns3_config_auto_neg_cmd {
777 uint32_t cfg_an_cmd_flag;
778 uint8_t rsv[20];
779};
780
781#define HNS3_SFP_INFO_BD0_LEN 20UL
782#define HNS3_SFP_INFO_BDX_LEN 24UL
783
784struct hns3_sfp_info_bd0_cmd {
785 uint16_t offset;
786 uint16_t read_len;
787 uint8_t data[HNS3_SFP_INFO_BD0_LEN];
788};
789
790struct hns3_sfp_type {
791 uint8_t type;
792 uint8_t ext_type;
793};
794
795
796#define HNS3_FIBER_LINK_SPEED_1G_BIT BIT(0)
797#define HNS3_FIBER_LINK_SPEED_10G_BIT BIT(1)
798#define HNS3_FIBER_LINK_SPEED_25G_BIT BIT(2)
799#define HNS3_FIBER_LINK_SPEED_50G_BIT BIT(3)
800#define HNS3_FIBER_LINK_SPEED_100G_BIT BIT(4)
801#define HNS3_FIBER_LINK_SPEED_40G_BIT BIT(5)
802#define HNS3_FIBER_LINK_SPEED_100M_BIT BIT(6)
803#define HNS3_FIBER_LINK_SPEED_10M_BIT BIT(7)
804#define HNS3_FIBER_LINK_SPEED_200G_BIT BIT(8)
805
806struct hns3_sfp_info_cmd {
807 uint32_t sfp_speed;
808 uint8_t query_type;
809 uint8_t active_fec;
810 uint8_t autoneg;
811
812 uint8_t autoneg_ability;
813 uint32_t supported_speed;
814 uint32_t module_type;
815 uint8_t rsv1[8];
816};
817
818#define HNS3_MAC_CFG_FEC_AUTO_EN_B 0
819#define HNS3_MAC_CFG_FEC_MODE_S 1
820#define HNS3_MAC_CFG_FEC_MODE_M GENMASK(3, 1)
821#define HNS3_MAC_FEC_OFF 0
822#define HNS3_MAC_FEC_BASER 1
823#define HNS3_MAC_FEC_RS 2
824
825
826struct hns3_config_fec_cmd {
827 uint8_t fec_mode;
828 uint8_t rsv[23];
829};
830
831#define HNS3_MAC_MGR_MASK_VLAN_B BIT(0)
832#define HNS3_MAC_MGR_MASK_MAC_B BIT(1)
833#define HNS3_MAC_MGR_MASK_ETHERTYPE_B BIT(2)
834#define HNS3_MAC_ETHERTYPE_LLDP 0x88cc
835
836struct hns3_mac_mgr_tbl_entry_cmd {
837 uint8_t flags;
838 uint8_t resp_code;
839 uint16_t vlan_tag;
840 uint32_t mac_addr_hi32;
841 uint16_t mac_addr_lo16;
842 uint16_t rsv1;
843 uint16_t ethter_type;
844 uint16_t egress_port;
845 uint16_t egress_queue;
846 uint8_t sw_port_id_aware;
847 uint8_t rsv2;
848 uint8_t i_port_bitmap;
849 uint8_t i_port_direction;
850 uint8_t rsv3[2];
851};
852
853struct hns3_cfg_com_tqp_queue_cmd {
854 uint16_t tqp_id;
855 uint16_t stream_id;
856 uint8_t enable;
857 uint8_t rsv[19];
858};
859
860#define HNS3_TQP_MAP_TYPE_PF 0
861#define HNS3_TQP_MAP_TYPE_VF 1
862#define HNS3_TQP_MAP_TYPE_B 0
863#define HNS3_TQP_MAP_EN_B 1
864
865struct hns3_tqp_map_cmd {
866 uint16_t tqp_id;
867 uint8_t tqp_vf;
868 uint8_t tqp_flag;
869 uint16_t tqp_vid;
870 uint8_t rsv[18];
871};
872
873enum hns3_ring_type {
874 HNS3_RING_TYPE_TX,
875 HNS3_RING_TYPE_RX
876};
877
878enum hns3_int_gl_idx {
879 HNS3_RING_GL_RX,
880 HNS3_RING_GL_TX,
881 HNS3_RING_GL_IMMEDIATE = 3
882};
883
884#define HNS3_RING_GL_IDX_S 0
885#define HNS3_RING_GL_IDX_M GENMASK(1, 0)
886
887#define HNS3_VECTOR_ELEMENTS_PER_CMD 10
888
889#define HNS3_INT_TYPE_S 0
890#define HNS3_INT_TYPE_M GENMASK(1, 0)
891#define HNS3_TQP_ID_S 2
892#define HNS3_TQP_ID_M GENMASK(12, 2)
893#define HNS3_INT_GL_IDX_S 13
894#define HNS3_INT_GL_IDX_M GENMASK(14, 13)
895#define HNS3_TQP_INT_ID_L_S 0
896#define HNS3_TQP_INT_ID_L_M GENMASK(7, 0)
897#define HNS3_TQP_INT_ID_H_S 8
898#define HNS3_TQP_INT_ID_H_M GENMASK(15, 8)
899struct hns3_ctrl_vector_chain_cmd {
900 uint8_t int_vector_id;
901 uint8_t int_cause_num;
902 uint16_t tqp_type_and_id[HNS3_VECTOR_ELEMENTS_PER_CMD];
903 uint8_t vfid;
904 uint8_t int_vector_id_h;
905};
906
907struct hns3_config_max_frm_size_cmd {
908 uint16_t max_frm_size;
909 uint8_t min_frm_size;
910 uint8_t rsv[21];
911};
912
913enum hns3_mac_vlan_tbl_opcode {
914 HNS3_MAC_VLAN_ADD,
915 HNS3_MAC_VLAN_UPDATE,
916 HNS3_MAC_VLAN_REMOVE,
917 HNS3_MAC_VLAN_LKUP,
918};
919
920enum hns3_mac_vlan_add_resp_code {
921 HNS3_ADD_UC_OVERFLOW = 2,
922 HNS3_ADD_MC_OVERFLOW,
923};
924
925#define HNS3_MC_MAC_VLAN_ADD_DESC_NUM 3
926
927#define HNS3_MAC_VLAN_BIT0_EN_B 0
928#define HNS3_MAC_VLAN_BIT1_EN_B 1
929#define HNS3_MAC_EPORT_SW_EN_B 12
930#define HNS3_MAC_EPORT_TYPE_B 11
931#define HNS3_MAC_EPORT_VFID_S 3
932#define HNS3_MAC_EPORT_VFID_M GENMASK(10, 3)
933#define HNS3_MAC_EPORT_PFID_S 0
934#define HNS3_MAC_EPORT_PFID_M GENMASK(2, 0)
935struct hns3_mac_vlan_tbl_entry_cmd {
936 uint8_t flags;
937 uint8_t resp_code;
938 uint16_t vlan_tag;
939 uint32_t mac_addr_hi32;
940 uint16_t mac_addr_lo16;
941 uint16_t rsv1;
942 uint8_t entry_type;
943 uint8_t mc_mac_en;
944 uint16_t egress_port;
945 uint16_t egress_queue;
946 uint8_t rsv2[6];
947};
948
949#define HNS3_TQP_RESET_B 0
950struct hns3_reset_tqp_queue_cmd {
951 uint16_t tqp_id;
952 uint8_t reset_req;
953 uint8_t ready_to_reset;
954 uint8_t queue_direction;
955 uint8_t rsv[19];
956};
957
958#define HNS3_CFG_RESET_MAC_B 3
959#define HNS3_CFG_RESET_FUNC_B 7
960#define HNS3_CFG_RESET_RCB_B 1
961struct hns3_reset_cmd {
962 uint8_t mac_func_reset;
963 uint8_t fun_reset_vfid;
964 uint8_t fun_reset_rcb;
965 uint8_t rsv1;
966 uint16_t fun_reset_rcb_vqid_start;
967 uint16_t fun_reset_rcb_vqid_num;
968 uint8_t fun_reset_rcb_return_status;
969 uint8_t rsv2[15];
970};
971
972#define HNS3_QUERY_DEV_SPECS_BD_NUM 4
973struct hns3_dev_specs_0_cmd {
974 uint32_t rsv0;
975 uint32_t mac_entry_num;
976 uint32_t mng_entry_num;
977 uint16_t rss_ind_tbl_size;
978 uint16_t rss_key_size;
979 uint16_t intr_ql_max;
980 uint8_t max_non_tso_bd_num;
981 uint8_t rsv1;
982 uint32_t max_tm_rate;
983};
984
985struct hns3_query_rpu_cmd {
986 uint32_t tc_queue_num;
987 uint32_t rsv1[2];
988 uint32_t rpu_rx_pkt_drop_cnt;
989 uint32_t rsv2[2];
990};
991
992#define HNS3_OPC_SSU_DROP_REG_NUM 2
993
994struct hns3_query_ssu_cmd {
995 uint8_t rxtx;
996 uint8_t rsv[3];
997 uint32_t full_drop_cnt;
998 uint32_t part_drop_cnt;
999 uint32_t oq_drop_cnt;
1000 uint32_t rev1[2];
1001};
1002
1003#define HNS3_PTP_ENABLE_B 0
1004#define HNS3_PTP_TX_ENABLE_B 1
1005#define HNS3_PTP_RX_ENABLE_B 2
1006
1007#define HNS3_PTP_TYPE_S 0
1008#define HNS3_PTP_TYPE_M (0x3 << HNS3_PTP_TYPE_S)
1009
1010#define ALL_PTP_V2_TYPE 0xF
1011#define HNS3_PTP_MESSAGE_TYPE_S 0
1012#define HNS3_PTP_MESSAGE_TYPE_M (0xF << HNS3_PTP_MESSAGE_TYPE_S)
1013
1014#define PTP_TYPE_L2_V2_TYPE 0
1015
1016struct hns3_ptp_mode_cfg_cmd {
1017 uint8_t enable;
1018 uint8_t ptp_type;
1019 uint8_t v2_message_type_1;
1020 uint8_t v2_message_type_0;
1021 uint8_t rsv[20];
1022};
1023
1024struct hns3_ptp_int_cmd {
1025 uint8_t int_en;
1026 uint8_t rsvd[23];
1027};
1028
1029#define HNS3_MAX_TQP_NUM_HIP08_PF 64
1030#define HNS3_DEFAULT_TX_BUF 0x4000
1031#define HNS3_TOTAL_PKT_BUF 0x108000
1032#define HNS3_DEFAULT_DV 0xA000
1033#define HNS3_DEFAULT_NON_DCB_DV 0x7800
1034#define HNS3_NON_DCB_ADDITIONAL_BUF 0x1400
1035
1036#define HNS3_TYPE_CRQ 0
1037#define HNS3_TYPE_CSQ 1
1038
1039#define HNS3_NIC_SW_RST_RDY_B 16
1040#define HNS3_NIC_SW_RST_RDY BIT(HNS3_NIC_SW_RST_RDY_B)
1041#define HNS3_NIC_CMQ_DESC_NUM 1024
1042#define HNS3_NIC_CMQ_DESC_NUM_S 3
1043
1044#define HNS3_CMD_SEND_SYNC(flag) \
1045 ((flag) & HNS3_CMD_FLAG_NO_INTR)
1046
1047void hns3_cmd_reuse_desc(struct hns3_cmd_desc *desc, bool is_read);
1048void hns3_cmd_setup_basic_desc(struct hns3_cmd_desc *desc,
1049 enum hns3_opcode_type opcode, bool is_read);
1050int hns3_cmd_send(struct hns3_hw *hw, struct hns3_cmd_desc *desc, int num);
1051int hns3_cmd_init_queue(struct hns3_hw *hw);
1052int hns3_cmd_init(struct hns3_hw *hw);
1053void hns3_cmd_destroy_queue(struct hns3_hw *hw);
1054void hns3_cmd_uninit(struct hns3_hw *hw);
1055
1056#endif
1057
