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4
5#ifndef _HNS3_INTR_H_
6#define _HNS3_INTR_H_
7
8#include <stdint.h>
9
10#include "hns3_ethdev.h"
11
12#define HNS3_PPP_MPF_ECC_ERR_INT0_EN 0xFFFFFFFF
13#define HNS3_PPP_MPF_ECC_ERR_INT0_EN_MASK 0xFFFFFFFF
14#define HNS3_PPP_MPF_ECC_ERR_INT1_EN 0xFFFFFFFF
15#define HNS3_PPP_MPF_ECC_ERR_INT1_EN_MASK 0xFFFFFFFF
16#define HNS3_PPP_PF_ERR_INT_EN 0x0003
17#define HNS3_PPP_PF_ERR_INT_EN_MASK 0x0003
18#define HNS3_PPP_MPF_ECC_ERR_INT2_EN 0x003F
19#define HNS3_PPP_MPF_ECC_ERR_INT2_EN_MASK 0x003F
20#define HNS3_PPP_MPF_ECC_ERR_INT3_EN 0x003F
21#define HNS3_PPP_MPF_ECC_ERR_INT3_EN_MASK 0x003F
22
23#define HNS3_MAC_COMMON_ERR_INT_EN 0x107FF
24#define HNS3_MAC_COMMON_ERR_INT_EN_MASK 0x107FF
25#define HNS3_MAC_TNL_INT_EN GENMASK(9, 0)
26#define HNS3_MAC_TNL_INT_EN_MASK GENMASK(9, 0)
27#define HNS3_MAC_TNL_INT_CLR GENMASK(9, 0)
28
29#define HNS3_IMP_TCM_ECC_ERR_INT_EN 0xFFFF0000
30#define HNS3_IMP_TCM_ECC_ERR_INT_EN_MASK 0xFFFF0000
31#define HNS3_IMP_ITCM4_ECC_ERR_INT_EN 0x300
32#define HNS3_IMP_ITCM4_ECC_ERR_INT_EN_MASK 0x300
33#define HNS3_IMP_RD_POISON_ERR_INT_EN 0x0100
34#define HNS3_IMP_RD_POISON_ERR_INT_EN_MASK 0x0100
35
36#define HNS3_CMDQ_NIC_ECC_ERR_INT_EN 0xFFFF
37#define HNS3_CMDQ_NIC_ECC_ERR_INT_EN_MASK 0xFFFF
38
39#define HNS3_TQP_ECC_ERR_INT_EN 0x0FFF
40#define HNS3_TQP_ECC_ERR_INT_EN_MASK 0x0FFF
41
42#define HNS3_MSIX_SRAM_ECC_ERR_INT_EN 0x0F000000
43#define HNS3_MSIX_SRAM_ECC_ERR_INT_EN_MASK 0x0F000000
44
45#define HNS3_PPU_MPF_ABNORMAL_INT0_EN GENMASK(31, 0)
46#define HNS3_PPU_MPF_ABNORMAL_INT0_EN_MASK GENMASK(31, 0)
47#define HNS3_PPU_MPF_ABNORMAL_INT1_EN GENMASK(31, 0)
48#define HNS3_PPU_MPF_ABNORMAL_INT1_EN_MASK GENMASK(31, 0)
49#define HNS3_PPU_MPF_ABNORMAL_INT2_EN 0x3FFF3FFF
50#define HNS3_PPU_MPF_ABNORMAL_INT2_EN_MASK 0x3FFF3FFF
51#define HNS3_PPU_MPF_ABNORMAL_INT2_EN2 0xB
52#define HNS3_PPU_MPF_ABNORMAL_INT2_EN2_MASK 0xB
53#define HNS3_PPU_MPF_ABNORMAL_INT3_EN GENMASK(7, 0)
54#define HNS3_PPU_MPF_ABNORMAL_INT3_EN_MASK GENMASK(23, 16)
55#define HNS3_PPU_PF_ABNORMAL_INT_EN GENMASK(5, 0)
56#define HNS3_PPU_PF_ABNORMAL_INT_EN_MASK GENMASK(5, 0)
57
58#define HNS3_SSU_1BIT_ECC_ERR_INT_EN GENMASK(31, 0)
59#define HNS3_SSU_1BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)
60#define HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN GENMASK(31, 0)
61#define HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)
62#define HNS3_SSU_BIT32_ECC_ERR_INT_EN 0x0101
63#define HNS3_SSU_BIT32_ECC_ERR_INT_EN_MASK 0x0101
64#define HNS3_SSU_COMMON_INT_EN GENMASK(9, 0)
65#define HNS3_SSU_COMMON_INT_EN_MASK GENMASK(9, 0)
66#define HNS3_SSU_PORT_BASED_ERR_INT_EN 0x0BFF
67#define HNS3_SSU_PORT_BASED_ERR_INT_EN_MASK 0x0BFF0000
68#define HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN GENMASK(23, 0)
69#define HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK GENMASK(23, 0)
70
71#define HNS3_IGU_ERR_INT_ENABLE 0x0000066F
72#define HNS3_IGU_ERR_INT_DISABLE 0x00000660
73#define HNS3_IGU_ERR_INT_EN_MASK 0x000F
74#define HNS3_IGU_TNL_ERR_INT_EN 0x0002AABF
75#define HNS3_IGU_TNL_ERR_INT_EN_MASK 0x003F
76
77#define HNS3_NCSI_ERR_INT_EN 0x3
78
79#define HNS3_TM_SCH_ECC_ERR_INT_EN 0x3
80#define HNS3_TM_QCN_ERR_INT_TYPE 0x29
81#define HNS3_TM_QCN_FIFO_INT_EN 0xFFFF00
82#define HNS3_TM_QCN_MEM_ERR_INT_EN 0xFFFFFF
83
84#define HNS3_RESET_PROCESS_MS 200
85
86#define HNS3_DESC_DATA_MAX 8
87#define HNS3_REG_NUM_MAX 256
88#define HNS3_DESC_NO_DATA_LEN 8
89#define HNS3_DESC_DATA_UNIT_SIZE 4
90
91enum hns3_mod_name_list {
92 MODULE_NONE,
93 MODULE_BIOS_COMMON,
94 MODULE_GE,
95 MODULE_IGU_EGU,
96 MODULE_LGE,
97 MODULE_NCSI,
98 MODULE_PPP,
99 MODULE_QCN,
100 MODULE_RCB_RX,
101 MODULE_RTC,
102 MODULE_SSU,
103 MODULE_TM,
104 MODULE_RCB_TX,
105 MODULE_TXDMA,
106 MODULE_MASTER,
107 MODULE_ROH_MAC,
108};
109
110enum hns3_err_type_list {
111 NONE_ERROR,
112 FIFO_ERROR,
113 MEMORY_ERROR,
114 POISION_ERROR,
115 MSIX_ECC_ERROR,
116 TQP_INT_ECC_ERROR,
117 PF_ABNORMAL_INT_ERROR,
118 MPF_ABNORMAL_INT_ERROR,
119 COMMON_ERROR,
120 PORT_ERROR,
121 ETS_ERROR,
122 NCSI_ERROR,
123 GLB_ERROR,
124};
125
126struct hns3_hw_mod_name {
127 enum hns3_mod_name_list module_name;
128 const char *msg;
129};
130
131struct hns3_hw_err_type {
132 enum hns3_err_type_list error_type;
133 const char *msg;
134};
135
136struct hns3_sum_err_info {
137 uint8_t reset_type;
138 uint8_t mod_num;
139 uint8_t rsv[2];
140};
141
142struct hns3_mod_err_info {
143 uint8_t mod_id;
144 uint8_t err_num;
145 uint8_t rsv[2];
146};
147
148struct hns3_type_reg_err_info {
149 uint8_t type_id;
150 uint8_t reg_num;
151 uint8_t rsv[2];
152 uint32_t reg[HNS3_REG_NUM_MAX];
153};
154
155struct hns3_hw_blk {
156 const char *name;
157 int (*enable_err_intr)(struct hns3_adapter *hns, bool en);
158};
159
160struct hns3_hw_error {
161 uint32_t int_msk;
162 const char *msg;
163 enum hns3_reset_level reset_level;
164};
165
166struct hns3_hw_error_desc {
167 uint8_t desc_offset;
168 uint8_t data_offset;
169 const char *msg;
170 const struct hns3_hw_error *hw_err;
171};
172
173int hns3_enable_hw_error_intr(struct hns3_adapter *hns, bool state);
174void hns3_handle_msix_error(struct hns3_adapter *hns, uint64_t *levels);
175void hns3_handle_ras_error(struct hns3_adapter *hns, uint64_t *levels);
176void hns3_config_mac_tnl_int(struct hns3_hw *hw, bool en);
177void hns3_handle_error(struct hns3_adapter *hns);
178
179void hns3_intr_unregister(const struct rte_intr_handle *hdl,
180 rte_intr_callback_fn cb_fn, void *cb_arg);
181void hns3_notify_reset_ready(struct hns3_hw *hw, bool enable);
182int hns3_reset_init(struct hns3_hw *hw);
183void hns3_wait_callback(void *param);
184void hns3_schedule_reset(struct hns3_adapter *hns);
185void hns3_schedule_delayed_reset(struct hns3_adapter *hns);
186int hns3_reset_req_hw_reset(struct hns3_adapter *hns);
187int hns3_reset_process(struct hns3_adapter *hns,
188 enum hns3_reset_level reset_level);
189void hns3_reset_abort(struct hns3_adapter *hns);
190void hns3_start_report_lse(struct rte_eth_dev *dev);
191void hns3_stop_report_lse(struct rte_eth_dev *dev);
192
193#endif
194
