/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2018-2021 HiSilicon Limited.
 */

#include <rte_bus_pci.h>
#include <rte_common.h>
#include <rte_cycles.h>
#include <rte_geneve.h>
#include <rte_vxlan.h>
#include <ethdev_driver.h>
#include <rte_io.h>
#include <rte_net.h>
#include <rte_malloc.h>
#if defined(RTE_ARCH_ARM64)
#include <rte_cpuflags.h>
#include <rte_vect.h>
#endif

#include "hns3_ethdev.h"
#include "hns3_rxtx.h"
#include "hns3_regs.h"
#include "hns3_logs.h"

#define HNS3_CFG_DESC_NUM(num)  ((num) / 8 - 1)
#define HNS3_RX_RING_PREFETCTH_MASK     3

static void
hns3_rx_queue_release_mbufs(struct hns3_rx_queue *rxq)
{
        uint16_t i;

        /* Note: Fake rx queue will not enter here */
        if (rxq->sw_ring == NULL)
                return;

        if (rxq->rx_rearm_nb == 0) {
                for (i = 0; i < rxq->nb_rx_desc; i++) {
                        if (rxq->sw_ring[i].mbuf != NULL) {
                                rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
                                rxq->sw_ring[i].mbuf = NULL;
                        }
                }
        } else {
                for (i = rxq->next_to_use;
                     i != rxq->rx_rearm_start;
                     i = (i + 1) % rxq->nb_rx_desc) {
                        if (rxq->sw_ring[i].mbuf != NULL) {
                                rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
                                rxq->sw_ring[i].mbuf = NULL;
                        }
                }
        }

        for (i = 0; i < rxq->bulk_mbuf_num; i++)
                rte_pktmbuf_free_seg(rxq->bulk_mbuf[i]);
        rxq->bulk_mbuf_num = 0;

        if (rxq->pkt_first_seg) {
                rte_pktmbuf_free(rxq->pkt_first_seg);
                rxq->pkt_first_seg = NULL;
        }
}

static void
hns3_tx_queue_release_mbufs(struct hns3_tx_queue *txq)
{
        uint16_t i;

        /* Note: Fake tx queue will not enter here */
        if (txq->sw_ring) {
                for (i = 0; i < txq->nb_tx_desc; i++) {
                        if (txq->sw_ring[i].mbuf) {
                                rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
                                txq->sw_ring[i].mbuf = NULL;
                        }
                }
        }
}

static void
hns3_rx_queue_release(void *queue)
{
        struct hns3_rx_queue *rxq = queue;
        if (rxq) {
                hns3_rx_queue_release_mbufs(rxq);
                if (rxq->mz)
                        rte_memzone_free(rxq->mz);
                if (rxq->sw_ring)
                        rte_free(rxq->sw_ring);
                rte_free(rxq);
        }
}

static void
hns3_tx_queue_release(void *queue)
{
        struct hns3_tx_queue *txq = queue;
        if (txq) {
                hns3_tx_queue_release_mbufs(txq);
                if (txq->mz)
                        rte_memzone_free(txq->mz);
                if (txq->sw_ring)
                        rte_free(txq->sw_ring);
                if (txq->free)
                        rte_free(txq->free);
                rte_free(txq);
        }
}

void
hns3_dev_rx_queue_release(void *queue)
{
        struct hns3_rx_queue *rxq = queue;
        struct hns3_adapter *hns;

        if (rxq == NULL)
                return;

        hns = rxq->hns;
        rte_spinlock_lock(&hns->hw.lock);
        hns3_rx_queue_release(queue);
        rte_spinlock_unlock(&hns->hw.lock);
}

void
hns3_dev_tx_queue_release(void *queue)
{
        struct hns3_tx_queue *txq = queue;
        struct hns3_adapter *hns;

        if (txq == NULL)
                return;

        hns = txq->hns;
        rte_spinlock_lock(&hns->hw.lock);
        hns3_tx_queue_release(queue);
        rte_spinlock_unlock(&hns->hw.lock);
}

static void
hns3_fake_rx_queue_release(struct hns3_rx_queue *queue)
{
        struct hns3_rx_queue *rxq = queue;
        struct hns3_adapter *hns;
        struct hns3_hw *hw;
        uint16_t idx;

        if (rxq == NULL)
                return;

        hns = rxq->hns;
        hw = &hns->hw;
        idx = rxq->queue_id;
        if (hw->fkq_data.rx_queues[idx]) {
                hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]);
                hw->fkq_data.rx_queues[idx] = NULL;
        }

        /* free fake rx queue arrays */
        if (idx == (hw->fkq_data.nb_fake_rx_queues - 1)) {
                hw->fkq_data.nb_fake_rx_queues = 0;
                rte_free(hw->fkq_data.rx_queues);
                hw->fkq_data.rx_queues = NULL;
        }
}

static void
hns3_fake_tx_queue_release(struct hns3_tx_queue *queue)
{
        struct hns3_tx_queue *txq = queue;
        struct hns3_adapter *hns;
        struct hns3_hw *hw;
        uint16_t idx;

        if (txq == NULL)
                return;

        hns = txq->hns;
        hw = &hns->hw;
        idx = txq->queue_id;
        if (hw->fkq_data.tx_queues[idx]) {
                hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]);
                hw->fkq_data.tx_queues[idx] = NULL;
        }

        /* free fake tx queue arrays */
        if (idx == (hw->fkq_data.nb_fake_tx_queues - 1)) {
                hw->fkq_data.nb_fake_tx_queues = 0;
                rte_free(hw->fkq_data.tx_queues);
                hw->fkq_data.tx_queues = NULL;
        }
}

static void
hns3_free_rx_queues(struct rte_eth_dev *dev)
{
        struct hns3_adapter *hns = dev->data->dev_private;
        struct hns3_fake_queue_data *fkq_data;
        struct hns3_hw *hw = &hns->hw;
        uint16_t nb_rx_q;
        uint16_t i;

        nb_rx_q = hw->data->nb_rx_queues;
        for (i = 0; i < nb_rx_q; i++) {
                if (dev->data->rx_queues[i]) {
                        hns3_rx_queue_release(dev->data->rx_queues[i]);
                        dev->data->rx_queues[i] = NULL;
                }
        }

        /* Free fake Rx queues */
        fkq_data = &hw->fkq_data;
        for (i = 0; i < fkq_data->nb_fake_rx_queues; i++) {
                if (fkq_data->rx_queues[i])
                        hns3_fake_rx_queue_release(fkq_data->rx_queues[i]);
        }
}

static void
hns3_free_tx_queues(struct rte_eth_dev *dev)
{
        struct hns3_adapter *hns = dev->data->dev_private;
        struct hns3_fake_queue_data *fkq_data;
        struct hns3_hw *hw = &hns->hw;
        uint16_t nb_tx_q;
        uint16_t i;

        nb_tx_q = hw->data->nb_tx_queues;
        for (i = 0; i < nb_tx_q; i++) {
                if (dev->data->tx_queues[i]) {
                        hns3_tx_queue_release(dev->data->tx_queues[i]);
                        dev->data->tx_queues[i] = NULL;
                }
        }

        /* Free fake Tx queues */
        fkq_data = &hw->fkq_data;
        for (i = 0; i < fkq_data->nb_fake_tx_queues; i++) {
                if (fkq_data->tx_queues[i])
                        hns3_fake_tx_queue_release(fkq_data->tx_queues[i]);
        }
}

void
hns3_free_all_queues(struct rte_eth_dev *dev)
{
        hns3_free_rx_queues(dev);
        hns3_free_tx_queues(dev);
}

static int
hns3_alloc_rx_queue_mbufs(struct hns3_hw *hw, struct hns3_rx_queue *rxq)
{
        struct rte_mbuf *mbuf;
        uint64_t dma_addr;
        uint16_t i;

        for (i = 0; i < rxq->nb_rx_desc; i++) {
                mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
                if (unlikely(mbuf == NULL)) {
                        hns3_err(hw, "Failed to allocate RXD[%u] for rx queue!",
                                 i);
                        hns3_rx_queue_release_mbufs(rxq);
                        return -ENOMEM;
                }

                rte_mbuf_refcnt_set(mbuf, 1);
                mbuf->next = NULL;
                mbuf->data_off = RTE_PKTMBUF_HEADROOM;
                mbuf->nb_segs = 1;
                mbuf->port = rxq->port_id;

                rxq->sw_ring[i].mbuf = mbuf;
                dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
                rxq->rx_ring[i].addr = dma_addr;
                rxq->rx_ring[i].rx.bd_base_info = 0;
        }

        return 0;
}

static int
hns3_buf_size2type(uint32_t buf_size)
{
        int bd_size_type;

        switch (buf_size) {
        case 512:
                bd_size_type = HNS3_BD_SIZE_512_TYPE;
                break;
        case 1024:
                bd_size_type = HNS3_BD_SIZE_1024_TYPE;
                break;
        case 4096:
                bd_size_type = HNS3_BD_SIZE_4096_TYPE;
                break;
        default:
                bd_size_type = HNS3_BD_SIZE_2048_TYPE;
        }

        return bd_size_type;
}

static void
hns3_init_rx_queue_hw(struct hns3_rx_queue *rxq)
{
        uint32_t rx_buf_len = rxq->rx_buf_len;
        uint64_t dma_addr = rxq->rx_ring_phys_addr;

        hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_L_REG, (uint32_t)dma_addr);
        hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_H_REG,
                       (uint32_t)((dma_addr >> 31) >> 1));

        hns3_write_dev(rxq, HNS3_RING_RX_BD_LEN_REG,
                       hns3_buf_size2type(rx_buf_len));
        hns3_write_dev(rxq, HNS3_RING_RX_BD_NUM_REG,
                       HNS3_CFG_DESC_NUM(rxq->nb_rx_desc));
}

static void
hns3_init_tx_queue_hw(struct hns3_tx_queue *txq)
{
        uint64_t dma_addr = txq->tx_ring_phys_addr;

        hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_L_REG, (uint32_t)dma_addr);
        hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_H_REG,
                       (uint32_t)((dma_addr >> 31) >> 1));

        hns3_write_dev(txq, HNS3_RING_TX_BD_NUM_REG,
                       HNS3_CFG_DESC_NUM(txq->nb_tx_desc));
}

void
hns3_update_all_queues_pvid_proc_en(struct hns3_hw *hw)
{
        uint16_t nb_rx_q = hw->data->nb_rx_queues;
        uint16_t nb_tx_q = hw->data->nb_tx_queues;
        struct hns3_rx_queue *rxq;
        struct hns3_tx_queue *txq;
        bool pvid_en;
        int i;

        pvid_en = hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE;
        for (i = 0; i < hw->cfg_max_queues; i++) {
                if (i < nb_rx_q) {
                        rxq = hw->data->rx_queues[i];
                        if (rxq != NULL)
                                rxq->pvid_sw_discard_en = pvid_en;
                }
                if (i < nb_tx_q) {
                        txq = hw->data->tx_queues[i];
                        if (txq != NULL)
                                txq->pvid_sw_shift_en = pvid_en;
                }
        }
}

static void
hns3_stop_unused_queue(void *tqp_base, enum hns3_ring_type queue_type)
{
        uint32_t reg_offset;
        uint32_t reg;

        reg_offset = queue_type == HNS3_RING_TYPE_TX ?
                                   HNS3_RING_TX_EN_REG : HNS3_RING_RX_EN_REG;
        reg = hns3_read_reg(tqp_base, reg_offset);
        reg &= ~BIT(HNS3_RING_EN_B);
        hns3_write_reg(tqp_base, reg_offset, reg);
}

void
hns3_enable_all_queues(struct hns3_hw *hw, bool en)
{
        uint16_t nb_rx_q = hw->data->nb_rx_queues;
        uint16_t nb_tx_q = hw->data->nb_tx_queues;
        struct hns3_rx_queue *rxq;
        struct hns3_tx_queue *txq;
        uint32_t rcb_reg;
        void *tqp_base;
        int i;

        for (i = 0; i < hw->cfg_max_queues; i++) {
                if (hns3_dev_indep_txrx_supported(hw)) {
                        rxq = i < nb_rx_q ? hw->data->rx_queues[i] : NULL;
                        txq = i < nb_tx_q ? hw->data->tx_queues[i] : NULL;

                        tqp_base = (void *)((char *)hw->io_base +
                                        hns3_get_tqp_reg_offset(i));
                        /*
                         * If queue struct is not initialized, it means the
                         * related HW ring has not been initialized yet.
                         * So, these queues should be disabled before enable
                         * the tqps to avoid a HW exception since the queues
                         * are enabled by default.
                         */
                        if (rxq == NULL)
                                hns3_stop_unused_queue(tqp_base,
                                                        HNS3_RING_TYPE_RX);
                        if (txq == NULL)
                                hns3_stop_unused_queue(tqp_base,
                                                        HNS3_RING_TYPE_TX);
                } else {
                        rxq = i < nb_rx_q ? hw->data->rx_queues[i] :
                              hw->fkq_data.rx_queues[i - nb_rx_q];

                        tqp_base = rxq->io_base;
                }
                /*
                 * This is the master switch that used to control the enabling
                 * of a pair of Tx and Rx queues. Both the Rx and Tx point to
                 * the same register
                 */
                rcb_reg = hns3_read_reg(tqp_base, HNS3_RING_EN_REG);
                if (en)
                        rcb_reg |= BIT(HNS3_RING_EN_B);
                else
                        rcb_reg &= ~BIT(HNS3_RING_EN_B);
                hns3_write_reg(tqp_base, HNS3_RING_EN_REG, rcb_reg);
        }
}

static void
hns3_enable_txq(struct hns3_tx_queue *txq, bool en)
{
        struct hns3_hw *hw = &txq->hns->hw;
        uint32_t reg;

        if (hns3_dev_indep_txrx_supported(hw)) {
                reg = hns3_read_dev(txq, HNS3_RING_TX_EN_REG);
                if (en)
                        reg |= BIT(HNS3_RING_EN_B);
                else
                        reg &= ~BIT(HNS3_RING_EN_B);
                hns3_write_dev(txq, HNS3_RING_TX_EN_REG, reg);
        }
        txq->enabled = en;
}

static void
hns3_enable_rxq(struct hns3_rx_queue *rxq, bool en)
{
        struct hns3_hw *hw = &rxq->hns->hw;
        uint32_t reg;

        if (hns3_dev_indep_txrx_supported(hw)) {
                reg = hns3_read_dev(rxq, HNS3_RING_RX_EN_REG);
                if (en)
                        reg |= BIT(HNS3_RING_EN_B);
                else
                        reg &= ~BIT(HNS3_RING_EN_B);
                hns3_write_dev(rxq, HNS3_RING_RX_EN_REG, reg);
        }
        rxq->enabled = en;
}

int
hns3_start_all_txqs(struct rte_eth_dev *dev)
{
        struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
        struct hns3_tx_queue *txq;
        uint16_t i, j;

        for (i = 0; i < dev->data->nb_tx_queues; i++) {
                txq = hw->data->tx_queues[i];
                if (!txq) {
                        hns3_err(hw, "Tx queue %u not available or setup.", i);
                        goto start_txqs_fail;
                }
                /*
                 * Tx queue is enabled by default. Therefore, the Tx queues
                 * needs to be disabled when deferred_start is set. There is
                 * another master switch used to control the enabling of a pair
                 * of Tx and Rx queues. And the master switch is disabled by
                 * default.
                 */
                if (txq->tx_deferred_start)
                        hns3_enable_txq(txq, false);
                else
                        hns3_enable_txq(txq, true);
        }
        return 0;

start_txqs_fail:
        for (j = 0; j < i; j++) {
                txq = hw->data->tx_queues[j];
                hns3_enable_txq(txq, false);
        }
        return -EINVAL;
}

int
hns3_start_all_rxqs(struct rte_eth_dev *dev)
{
        struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
        struct hns3_rx_queue *rxq;
        uint16_t i, j;

        for (i = 0; i < dev->data->nb_rx_queues; i++) {
                rxq = hw->data->rx_queues[i];
                if (!rxq) {
                        hns3_err(hw, "Rx queue %u not available or setup.", i);
                        goto start_rxqs_fail;
                }
                /*
                 * Rx queue is enabled by default. Therefore, the Rx queues
                 * needs to be disabled when deferred_start is set. There is
                 * another master switch used to control the enabling of a pair
                 * of Tx and Rx queues. And the master switch is disabled by
                 * default.
                 */
                if (rxq->rx_deferred_start)
                        hns3_enable_rxq(rxq, false);
                else
                        hns3_enable_rxq(rxq, true);
        }
        return 0;

start_rxqs_fail:
        for (j = 0; j < i; j++) {
                rxq = hw->data->rx_queues[j];
                hns3_enable_rxq(rxq, false);
        }
        return -EINVAL;
}

void
hns3_restore_tqp_enable_state(struct hns3_hw *hw)
{
        struct hns3_rx_queue *rxq;
        struct hns3_tx_queue *txq;
        uint16_t i;

        for (i = 0; i < hw->data->nb_rx_queues; i++) {
                rxq = hw->data->rx_queues[i];
                if (rxq != NULL)
                        hns3_enable_rxq(rxq, rxq->enabled);
        }

        for (i = 0; i < hw->data->nb_tx_queues; i++) {
                txq = hw->data->tx_queues[i];
                if (txq != NULL)
                        hns3_enable_txq(txq, txq->enabled);
        }
}

void
hns3_stop_all_txqs(struct rte_eth_dev *dev)
{
        struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
        struct hns3_tx_queue *txq;
        uint16_t i;

        for (i = 0; i < dev->data->nb_tx_queues; i++) {
                txq = hw->data->tx_queues[i];
                if (!txq)
                        continue;
                hns3_enable_txq(txq, false);
        }
}

static int
hns3_tqp_enable(struct hns3_hw *hw, uint16_t queue_id, bool enable)
{
        struct hns3_cfg_com_tqp_queue_cmd *req;
        struct hns3_cmd_desc desc;
        int ret;

        req = (struct hns3_cfg_com_tqp_queue_cmd *)desc.data;

        hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_COM_TQP_QUEUE, false);
        req->tqp_id = rte_cpu_to_le_16(queue_id);
        req->stream_id = 0;
        hns3_set_bit(req->enable, HNS3_TQP_ENABLE_B, enable ? 1 : 0);

        ret = hns3_cmd_send(hw, &desc, 1);
        if (ret)
                hns3_err(hw, "TQP enable fail, ret = %d", ret);

        return ret;
}

static int
hns3_send_reset_tqp_cmd(struct hns3_hw *hw, uint16_t queue_id, bool enable)
{
        struct hns3_reset_tqp_queue_cmd *req;
        struct hns3_cmd_desc desc;
        int ret;

        hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, false);

        req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
        req->tqp_id = rte_cpu_to_le_16(queue_id);
        hns3_set_bit(req->reset_req, HNS3_TQP_RESET_B, enable ? 1 : 0);
        ret = hns3_cmd_send(hw, &desc, 1);
        if (ret)
                hns3_err(hw, "send tqp reset cmd error, queue_id = %u, "
                             "ret = %d", queue_id, ret);

        return ret;
}

static int
hns3_get_tqp_reset_status(struct hns3_hw *hw, uint16_t queue_id,
                          uint8_t *reset_status)
{
        struct hns3_reset_tqp_queue_cmd *req;
        struct hns3_cmd_desc desc;
        int ret;

        hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, true);

        req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
        req->tqp_id = rte_cpu_to_le_16(queue_id);

        ret = hns3_cmd_send(hw, &desc, 1);
        if (ret) {
                hns3_err(hw, "get tqp reset status error, queue_id = %u, "
                             "ret = %d.", queue_id, ret);
                return ret;
        }
        *reset_status = hns3_get_bit(req->ready_to_reset, HNS3_TQP_RESET_B);
        return ret;
}

static int
hns3pf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id)
{
#define HNS3_TQP_RESET_TRY_MS   200
        uint16_t wait_time = 0;
        uint8_t reset_status;
        int ret;

        /*
         * In current version VF is not supported when PF is driven by DPDK
         * driver, all task queue pairs are mapped to PF function, so PF's queue
         * id is equals to the global queue id in PF range.
         */
        ret = hns3_send_reset_tqp_cmd(hw, queue_id, true);
        if (ret) {
                hns3_err(hw, "Send reset tqp cmd fail, ret = %d", ret);
                return ret;
        }

        do {
                /* Wait for tqp hw reset */
                rte_delay_ms(HNS3_POLL_RESPONE_MS);
                wait_time += HNS3_POLL_RESPONE_MS;
                ret = hns3_get_tqp_reset_status(hw, queue_id, &reset_status);
                if (ret)
                        goto tqp_reset_fail;

                if (reset_status)
                        break;
        } while (wait_time < HNS3_TQP_RESET_TRY_MS);

        if (!reset_status) {
                ret = -ETIMEDOUT;
                hns3_err(hw, "reset tqp timeout, queue_id = %u, ret = %d",
                             queue_id, ret);
                goto tqp_reset_fail;
        }

        ret = hns3_send_reset_tqp_cmd(hw, queue_id, false);
        if (ret)
                hns3_err(hw, "Deassert the soft reset fail, ret = %d", ret);

        return ret;

tqp_reset_fail:
        hns3_send_reset_tqp_cmd(hw, queue_id, false);
        return ret;
}

static int
hns3vf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id)
{
        uint8_t msg_data[2];
        int ret;

        memcpy(msg_data, &queue_id, sizeof(uint16_t));

        ret = hns3_send_mbx_msg(hw, HNS3_MBX_QUEUE_RESET, 0, msg_data,
                                 sizeof(msg_data), true, NULL, 0);
        if (ret)
                hns3_err(hw, "fail to reset tqp, queue_id = %u, ret = %d.",
                         queue_id, ret);
        return ret;
}

static int
hns3_reset_rcb_cmd(struct hns3_hw *hw, uint8_t *reset_status)
{
        struct hns3_reset_cmd *req;
        struct hns3_cmd_desc desc;
        int ret;

        hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
        req = (struct hns3_reset_cmd *)desc.data;
        hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_RCB_B, 1);

        /*
         * The start qid should be the global qid of the first tqp of the
         * function which should be reset in this port. Since our PF not
         * support take over of VFs, so we only need to reset function 0,
         * and its start qid is always 0.
         */
        req->fun_reset_rcb_vqid_start = rte_cpu_to_le_16(0);
        req->fun_reset_rcb_vqid_num = rte_cpu_to_le_16(hw->cfg_max_queues);

        ret = hns3_cmd_send(hw, &desc, 1);
        if (ret) {
                hns3_err(hw, "fail to send rcb reset cmd, ret = %d.", ret);
                return ret;
        }

        *reset_status = req->fun_reset_rcb_return_status;
        return 0;
}

static int
hns3pf_reset_all_tqps(struct hns3_hw *hw)
{
#define HNS3_RESET_RCB_NOT_SUPPORT      0U
#define HNS3_RESET_ALL_TQP_SUCCESS      1U
        uint8_t reset_status;
        int ret;
        int i;

        ret = hns3_reset_rcb_cmd(hw, &reset_status);
        if (ret)
                return ret;

        /*
         * If the firmware version is low, it may not support the rcb reset
         * which means reset all the tqps at a time. In this case, we should
         * reset tqps one by one.
         */
        if (reset_status == HNS3_RESET_RCB_NOT_SUPPORT) {
                for (i = 0; i < hw->cfg_max_queues; i++) {
                        ret = hns3pf_reset_tqp(hw, i);
                        if (ret) {
                                hns3_err(hw,
                                  "fail to reset tqp, queue_id = %d, ret = %d.",
                                  i, ret);
                                return ret;
                        }
                }
        } else if (reset_status != HNS3_RESET_ALL_TQP_SUCCESS) {
                hns3_err(hw, "fail to reset all tqps, reset_status = %u.",
                                reset_status);
                return -EIO;
        }

        return 0;
}

static int
hns3vf_reset_all_tqps(struct hns3_hw *hw)
{
#define HNS3VF_RESET_ALL_TQP_DONE       1U
        uint8_t reset_status;
        uint8_t msg_data[2];
        int ret;
        int i;

        memset(msg_data, 0, sizeof(uint16_t));
        ret = hns3_send_mbx_msg(hw, HNS3_MBX_QUEUE_RESET, 0, msg_data,
                                sizeof(msg_data), true, &reset_status,
                                sizeof(reset_status));
        if (ret) {
                hns3_err(hw, "fail to send rcb reset mbx, ret = %d.", ret);
                return ret;
        }

        if (reset_status == HNS3VF_RESET_ALL_TQP_DONE)
                return 0;

        /*
         * If the firmware version or kernel PF version is low, it may not
         * support the rcb reset which means reset all the tqps at a time.
         * In this case, we should reset tqps one by one.
         */
        for (i = 1; i < hw->cfg_max_queues; i++) {
                ret = hns3vf_reset_tqp(hw, i);
                if (ret)
                        return ret;
        }

        return 0;
}

int
hns3_reset_all_tqps(struct hns3_adapter *hns)
{
        struct hns3_hw *hw = &hns->hw;
        int ret, i;

        /* Disable all queues before reset all queues */
        for (i = 0; i < hw->cfg_max_queues; i++) {
                ret = hns3_tqp_enable(hw, i, false);
                if (ret) {
                        hns3_err(hw,
                            "fail to disable tqps before tqps reset, ret = %d.",
                            ret);
                        return ret;
                }
        }

        if (hns->is_vf)
                return hns3vf_reset_all_tqps(hw);
        else
                return hns3pf_reset_all_tqps(hw);
}

static int
hns3_send_reset_queue_cmd(struct hns3_hw *hw, uint16_t queue_id,
                          enum hns3_ring_type queue_type, bool enable)
{
        struct hns3_reset_tqp_queue_cmd *req;
        struct hns3_cmd_desc desc;
        int queue_direction;
        int ret;

        hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE_INDEP, false);

        req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
        req->tqp_id = rte_cpu_to_le_16(queue_id);
        queue_direction = queue_type == HNS3_RING_TYPE_TX ? 0 : 1;
        req->queue_direction = rte_cpu_to_le_16(queue_direction);
        hns3_set_bit(req->reset_req, HNS3_TQP_RESET_B, enable ? 1 : 0);

        ret = hns3_cmd_send(hw, &desc, 1);
        if (ret)
                hns3_err(hw, "send queue reset cmd error, queue_id = %u, "
                         "queue_type = %s, ret = %d.", queue_id,
                         queue_type == HNS3_RING_TYPE_TX ? "Tx" : "Rx", ret);
        return ret;
}

static int
hns3_get_queue_reset_status(struct hns3_hw *hw, uint16_t queue_id,
                            enum hns3_ring_type queue_type,
                            uint8_t *reset_status)
{
        struct hns3_reset_tqp_queue_cmd *req;
        struct hns3_cmd_desc desc;
        int queue_direction;
        int ret;

        hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE_INDEP, true);

        req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
        req->tqp_id = rte_cpu_to_le_16(queue_id);
        queue_direction = queue_type == HNS3_RING_TYPE_TX ? 0 : 1;
        req->queue_direction = rte_cpu_to_le_16(queue_direction);

        ret = hns3_cmd_send(hw, &desc, 1);
        if (ret) {
                hns3_err(hw, "get queue reset status error, queue_id = %u "
                         "queue_type = %s, ret = %d.", queue_id,
                         queue_type == HNS3_RING_TYPE_TX ? "Tx" : "Rx", ret);
                return ret;
        }

        *reset_status = hns3_get_bit(req->ready_to_reset, HNS3_TQP_RESET_B);
        return  ret;
}

static int
hns3_reset_queue(struct hns3_hw *hw, uint16_t queue_id,
                 enum hns3_ring_type queue_type)
{
#define HNS3_QUEUE_RESET_TRY_MS 200
        struct hns3_tx_queue *txq;
        struct hns3_rx_queue *rxq;
        uint32_t reset_wait_times;
        uint32_t max_wait_times;
        uint8_t reset_status;
        int ret;

        if (queue_type == HNS3_RING_TYPE_TX) {
                txq = hw->data->tx_queues[queue_id];
                hns3_enable_txq(txq, false);
        } else {
                rxq = hw->data->rx_queues[queue_id];
                hns3_enable_rxq(rxq, false);
        }

        ret = hns3_send_reset_queue_cmd(hw, queue_id, queue_type, true);
        if (ret) {
                hns3_err(hw, "send reset queue cmd fail, ret = %d.", ret);
                return ret;
        }

        reset_wait_times = 0;
        max_wait_times = HNS3_QUEUE_RESET_TRY_MS / HNS3_POLL_RESPONE_MS;
        while (reset_wait_times < max_wait_times) {
                /* Wait for queue hw reset */
                rte_delay_ms(HNS3_POLL_RESPONE_MS);
                ret = hns3_get_queue_reset_status(hw, queue_id,
                                                queue_type, &reset_status);
                if (ret)
                        goto queue_reset_fail;

                if (reset_status)
                        break;
                reset_wait_times++;
        }

        if (!reset_status) {
                hns3_err(hw, "reset queue timeout, queue_id = %u, "
                             "queue_type = %s", queue_id,
                             queue_type == HNS3_RING_TYPE_TX ? "Tx" : "Rx");
                ret = -ETIMEDOUT;
                goto queue_reset_fail;
        }

        ret = hns3_send_reset_queue_cmd(hw, queue_id, queue_type, false);
        if (ret)
                hns3_err(hw, "deassert queue reset fail, ret = %d.", ret);

        return ret;

queue_reset_fail:
        hns3_send_reset_queue_cmd(hw, queue_id, queue_type, false);
        return ret;
}

uint32_t
hns3_get_tqp_intr_reg_offset(uint16_t tqp_intr_id)
{
        uint32_t reg_offset;

        /* Need an extend offset to config queues > 64 */
        if (tqp_intr_id < HNS3_MIN_EXT_TQP_INTR_ID)
                reg_offset = HNS3_TQP_INTR_REG_BASE +
                             tqp_intr_id * HNS3_TQP_INTR_LOW_ORDER_OFFSET;
        else
                reg_offset = HNS3_TQP_INTR_EXT_REG_BASE +
                             tqp_intr_id / HNS3_MIN_EXT_TQP_INTR_ID *
                             HNS3_TQP_INTR_HIGH_ORDER_OFFSET +
                             tqp_intr_id % HNS3_MIN_EXT_TQP_INTR_ID *
                             HNS3_TQP_INTR_LOW_ORDER_OFFSET;

        return reg_offset;
}

void
hns3_set_queue_intr_gl(struct hns3_hw *hw, uint16_t queue_id,
                       uint8_t gl_idx, uint16_t gl_value)
{
        uint32_t offset[] = {HNS3_TQP_INTR_GL0_REG,
                             HNS3_TQP_INTR_GL1_REG,
                             HNS3_TQP_INTR_GL2_REG};
        uint32_t addr, value;

        if (gl_idx >= RTE_DIM(offset) || gl_value > HNS3_TQP_INTR_GL_MAX)
                return;

        addr = offset[gl_idx] + hns3_get_tqp_intr_reg_offset(queue_id);
        if (hw->intr.gl_unit == HNS3_INTR_COALESCE_GL_UINT_1US)
                value = gl_value | HNS3_TQP_INTR_GL_UNIT_1US;
        else
                value = HNS3_GL_USEC_TO_REG(gl_value);

        hns3_write_dev(hw, addr, value);
}

void
hns3_set_queue_intr_rl(struct hns3_hw *hw, uint16_t queue_id, uint16_t rl_value)
{
        uint32_t addr, value;

        if (rl_value > HNS3_TQP_INTR_RL_MAX)
                return;

        addr = HNS3_TQP_INTR_RL_REG + hns3_get_tqp_intr_reg_offset(queue_id);
        value = HNS3_RL_USEC_TO_REG(rl_value);
        if (value > 0)
                value |= HNS3_TQP_INTR_RL_ENABLE_MASK;

        hns3_write_dev(hw, addr, value);
}

void
hns3_set_queue_intr_ql(struct hns3_hw *hw, uint16_t queue_id, uint16_t ql_value)
{
        uint32_t addr;

        /*
         * int_ql_max == 0 means the hardware does not support QL,
         * QL regs config is not permitted if QL is not supported,
         * here just return.
         */
        if (hw->intr.int_ql_max == HNS3_INTR_QL_NONE)
                return;

        addr = HNS3_TQP_INTR_TX_QL_REG + hns3_get_tqp_intr_reg_offset(queue_id);
        hns3_write_dev(hw, addr, ql_value);

        addr = HNS3_TQP_INTR_RX_QL_REG + hns3_get_tqp_intr_reg_offset(queue_id);
        hns3_write_dev(hw, addr, ql_value);
}

static void
hns3_queue_intr_enable(struct hns3_hw *hw, uint16_t queue_id, bool en)
{
        uint32_t addr, value;

        addr = HNS3_TQP_INTR_CTRL_REG + hns3_get_tqp_intr_reg_offset(queue_id);
        value = en ? 1 : 0;

        hns3_write_dev(hw, addr, value);
}

/*
 * Enable all rx queue interrupt when in interrupt rx mode.
 * This api was called before enable queue rx&tx (in normal start or reset
 * recover scenes), used to fix hardware rx queue interrupt enable was clear
 * when FLR.
 */
void
hns3_dev_all_rx_queue_intr_enable(struct hns3_hw *hw, bool en)
{
        struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
        uint16_t nb_rx_q = hw->data->nb_rx_queues;
        int i;

        if (dev->data->dev_conf.intr_conf.rxq == 0)
                return;

        for (i = 0; i < nb_rx_q; i++)
                hns3_queue_intr_enable(hw, i, en);
}

int
hns3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
{
        struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
        struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
        struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);

        if (dev->data->dev_conf.intr_conf.rxq == 0)
                return -ENOTSUP;

        hns3_queue_intr_enable(hw, queue_id, true);

        return rte_intr_ack(intr_handle);
}

int
hns3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
{
        struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);

        if (dev->data->dev_conf.intr_conf.rxq == 0)
                return -ENOTSUP;

        hns3_queue_intr_enable(hw, queue_id, false);

        return 0;
}

static int
hns3_init_rxq(struct hns3_adapter *hns, uint16_t idx)
{
        struct hns3_hw *hw = &hns->hw;
        struct hns3_rx_queue *rxq;
        int ret;

        PMD_INIT_FUNC_TRACE();

        rxq = (struct hns3_rx_queue *)hw->data->rx_queues[idx];
        ret = hns3_alloc_rx_queue_mbufs(hw, rxq);
        if (ret) {
                hns3_err(hw, "fail to alloc mbuf for Rx queue %u, ret = %d.",
                         idx, ret);
                return ret;
        }

        rxq->next_to_use = 0;
        rxq->rx_rearm_start = 0;
        rxq->rx_free_hold = 0;
        rxq->rx_rearm_nb = 0;
        rxq->pkt_first_seg = NULL;
        rxq->pkt_last_seg = NULL;
        hns3_init_rx_queue_hw(rxq);
        hns3_rxq_vec_setup(rxq);

        return 0;
}

static void
hns3_init_fake_rxq(struct hns3_adapter *hns, uint16_t idx)
{
        struct hns3_hw *hw = &hns->hw;
        struct hns3_rx_queue *rxq;

        rxq = (struct hns3_rx_queue *)hw->fkq_data.rx_queues[idx];
        rxq->next_to_use = 0;
        rxq->rx_free_hold = 0;
        rxq->rx_rearm_start = 0;
        rxq->rx_rearm_nb = 0;
        hns3_init_rx_queue_hw(rxq);
}

static void
hns3_init_txq(struct hns3_tx_queue *txq)
{
        struct hns3_desc *desc;
        int i;

        /* Clear tx bd */
        desc = txq->tx_ring;
        for (i = 0; i < txq->nb_tx_desc; i++) {
                desc->tx.tp_fe_sc_vld_ra_ri = 0;
                desc++;
        }

        txq->next_to_use = 0;
        txq->next_to_clean = 0;
        txq->tx_bd_ready = txq->nb_tx_desc - 1;
        hns3_init_tx_queue_hw(txq);
}

static void
hns3_init_tx_ring_tc(struct hns3_adapter *hns)
{
        struct hns3_hw *hw = &hns->hw;
        struct hns3_tx_queue *txq;
        int i, num;

        for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
                struct hns3_tc_queue_info *tc_queue = &hw->tc_queue[i];
                int j;

                if (!tc_queue->enable)
                        continue;

                for (j = 0; j < tc_queue->tqp_count; j++) {
                        num = tc_queue->tqp_offset + j;
                        txq = (struct hns3_tx_queue *)hw->data->tx_queues[num];
                        if (txq == NULL)
                                continue;

                        hns3_write_dev(txq, HNS3_RING_TX_TC_REG, tc_queue->tc);
                }
        }
}

static int
hns3_init_rx_queues(struct hns3_adapter *hns)
{
        struct hns3_hw *hw = &hns->hw;
        struct hns3_rx_queue *rxq;
        uint16_t i, j;
        int ret;

        /* Initialize RSS for queues */
        ret = hns3_config_rss(hns);
        if (ret) {
                hns3_err(hw, "failed to configure rss, ret = %d.", ret);
                return ret;
        }

        for (i = 0; i < hw->data->nb_rx_queues; i++) {
                rxq = (struct hns3_rx_queue *)hw->data->rx_queues[i];
                if (!rxq) {
                        hns3_err(hw, "Rx queue %u not available or setup.", i);
                        goto out;
                }

                if (rxq->rx_deferred_start)
                        continue;

                ret = hns3_init_rxq(hns, i);
                if (ret) {
                        hns3_err(hw, "failed to init Rx queue %u, ret = %d.", i,
                                 ret);
                        goto out;
                }
        }

        for (i = 0; i < hw->fkq_data.nb_fake_rx_queues; i++)
                hns3_init_fake_rxq(hns, i);

        return 0;

out:
        for (j = 0; j < i; j++) {
                rxq = (struct hns3_rx_queue *)hw->data->rx_queues[j];
                hns3_rx_queue_release_mbufs(rxq);
        }

        return ret;
}

static int
hns3_init_tx_queues(struct hns3_adapter *hns)
{
        struct hns3_hw *hw = &hns->hw;
        struct hns3_tx_queue *txq;
        uint16_t i;

        for (i = 0; i < hw->data->nb_tx_queues; i++) {
                txq = (struct hns3_tx_queue *)hw->data->tx_queues[i];
                if (!txq) {
                        hns3_err(hw, "Tx queue %u not available or setup.", i);
                        return -EINVAL;
                }

                if (txq->tx_deferred_start)
                        continue;
                hns3_init_txq(txq);
        }

        for (i = 0; i < hw->fkq_data.nb_fake_tx_queues; i++) {
                txq = (struct hns3_tx_queue *)hw->fkq_data.tx_queues[i];
                hns3_init_txq(txq);
        }
        hns3_init_tx_ring_tc(hns);

        return 0;
}

/*
 * Init all queues.
 * Note: just init and setup queues, and don't enable tqps.
 */
int
hns3_init_queues(struct hns3_adapter *hns, bool reset_queue)
{
        struct hns3_hw *hw = &hns->hw;
        int ret;

        if (reset_queue) {
                ret = hns3_reset_all_tqps(hns);
                if (ret) {
                        hns3_err(hw, "failed to reset all queues, ret = %d.",
                                 ret);
                        return ret;
                }
        }

        ret = hns3_init_rx_queues(hns);
        if (ret) {
                hns3_err(hw, "failed to init rx queues, ret = %d.", ret);
                return ret;
        }

        ret = hns3_init_tx_queues(hns);
        if (ret) {
                hns3_dev_release_mbufs(hns);
                hns3_err(hw, "failed to init tx queues, ret = %d.", ret);
        }

        return ret;
}

void
hns3_start_tqps(struct hns3_hw *hw)
{
        struct hns3_tx_queue *txq;
        struct hns3_rx_queue *rxq;
        uint16_t i;

        hns3_enable_all_queues(hw, true);

        for (i = 0; i < hw->data->nb_tx_queues; i++) {
                txq = hw->data->tx_queues[i];
                if (txq->enabled)
                        hw->data->tx_queue_state[i] =
                                RTE_ETH_QUEUE_STATE_STARTED;
        }

        for (i = 0; i < hw->data->nb_rx_queues; i++) {
                rxq = hw->data->rx_queues[i];
                if (rxq->enabled)
                        hw->data->rx_queue_state[i] =
                                RTE_ETH_QUEUE_STATE_STARTED;
        }
}

void
hns3_stop_tqps(struct hns3_hw *hw)
{
        uint16_t i;

        hns3_enable_all_queues(hw, false);

        for (i = 0; i < hw->data->nb_tx_queues; i++)
                hw->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;

        for (i = 0; i < hw->data->nb_rx_queues; i++)
                hw->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
}

/*
 * Iterate over all Rx Queue, and call the callback() function for each Rx
 * queue.
 *
 * @param[in] dev
 *   The target eth dev.
 * @param[in] callback
 *   The function to call for each queue.
 *   if callback function return nonzero will stop iterate and return it's value
 * @param[in] arg
 *   The arguments to provide the callback function with.
 *
 * @return
 *   0 on success, otherwise with errno set.
 */
int
hns3_rxq_iterate(struct rte_eth_dev *dev,
                 int (*callback)(struct hns3_rx_queue *, void *), void *arg)
{
        uint32_t i;
        int ret;

        if (dev->data->rx_queues == NULL)
                return -EINVAL;

        for (i = 0; i < dev->data->nb_rx_queues; i++) {
                ret = callback(dev->data->rx_queues[i], arg);
                if (ret != 0)
                        return ret;
        }

        return 0;
}

static void*
hns3_alloc_rxq_and_dma_zone(struct rte_eth_dev *dev,
                            struct hns3_queue_info *q_info)
{
        struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
        const struct rte_memzone *rx_mz;
        struct hns3_rx_queue *rxq;
        unsigned int rx_desc;

        rxq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_rx_queue),
                                 RTE_CACHE_LINE_SIZE, q_info->socket_id);
        if (rxq == NULL) {
                hns3_err(hw, "Failed to allocate memory for No.%u rx ring!",
                         q_info->idx);
                return NULL;
        }

        /* Allocate rx ring hardware descriptors. */
        rxq->queue_id = q_info->idx;
        rxq->nb_rx_desc = q_info->nb_desc;

        /*
         * Allocate a litter more memory because rx vector functions
         * don't check boundaries each time.
         */
        rx_desc = (rxq->nb_rx_desc + HNS3_DEFAULT_RX_BURST) *
                        sizeof(struct hns3_desc);
        rx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx,
                                         rx_desc, HNS3_RING_BASE_ALIGN,
                                         q_info->socket_id);
        if (rx_mz == NULL) {
                hns3_err(hw, "Failed to reserve DMA memory for No.%u rx ring!",
                         q_info->idx);
                hns3_rx_queue_release(rxq);
                return NULL;
        }
        rxq->mz = rx_mz;
        rxq->rx_ring = (struct hns3_desc *)rx_mz->addr;
        rxq->rx_ring_phys_addr = rx_mz->iova;

        hns3_dbg(hw, "No.%u rx descriptors iova 0x%" PRIx64, q_info->idx,
                 rxq->rx_ring_phys_addr);

        return rxq;
}

static int
hns3_fake_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
                         uint16_t nb_desc, unsigned int socket_id)
{
        struct hns3_adapter *hns = dev->data->dev_private;
        struct hns3_hw *hw = &hns->hw;
        struct hns3_queue_info q_info;
        struct hns3_rx_queue *rxq;
        uint16_t nb_rx_q;

        if (hw->fkq_data.rx_queues[idx]) {
                hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]);
                hw->fkq_data.rx_queues[idx] = NULL;
        }

        q_info.idx = idx;
        q_info.socket_id = socket_id;
        q_info.nb_desc = nb_desc;
        q_info.type = "hns3 fake RX queue";
        q_info.ring_name = "rx_fake_ring";
        rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info);
        if (rxq == NULL) {
                hns3_err(hw, "Failed to setup No.%u fake rx ring.", idx);
                return -ENOMEM;
        }

        /* Don't need alloc sw_ring, because upper applications don't use it */
        rxq->sw_ring = NULL;

        rxq->hns = hns;
        rxq->rx_deferred_start = false;
        rxq->port_id = dev->data->port_id;
        rxq->configured = true;
        nb_rx_q = dev->data->nb_rx_queues;
        rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
                                (nb_rx_q + idx) * HNS3_TQP_REG_SIZE);
        rxq->rx_buf_len = HNS3_MIN_BD_BUF_SIZE;

        rte_spinlock_lock(&hw->lock);
        hw->fkq_data.rx_queues[idx] = rxq;
        rte_spinlock_unlock(&hw->lock);

        return 0;
}

static void*
hns3_alloc_txq_and_dma_zone(struct rte_eth_dev *dev,
                            struct hns3_queue_info *q_info)
{
        struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
        const struct rte_memzone *tx_mz;
        struct hns3_tx_queue *txq;
        struct hns3_desc *desc;
        unsigned int tx_desc;
        int i;

        txq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_tx_queue),
                                 RTE_CACHE_LINE_SIZE, q_info->socket_id);
        if (txq == NULL) {
                hns3_err(hw, "Failed to allocate memory for No.%u tx ring!",
                         q_info->idx);
                return NULL;
        }

        /* Allocate tx ring hardware descriptors. */
        txq->queue_id = q_info->idx;
        txq->nb_tx_desc = q_info->nb_desc;
        tx_desc = txq->nb_tx_desc * sizeof(struct hns3_desc);
        tx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx,
                                         tx_desc, HNS3_RING_BASE_ALIGN,
                                         q_info->socket_id);
        if (tx_mz == NULL) {
                hns3_err(hw, "Failed to reserve DMA memory for No.%u tx ring!",
                         q_info->idx);
                hns3_tx_queue_release(txq);
                return NULL;
        }
        txq->mz = tx_mz;
        txq->tx_ring = (struct hns3_desc *)tx_mz->addr;
        txq->tx_ring_phys_addr = tx_mz->iova;

        hns3_dbg(hw, "No.%u tx descriptors iova 0x%" PRIx64, q_info->idx,
                 txq->tx_ring_phys_addr);

        /* Clear tx bd */
        desc = txq->tx_ring;
        for (i = 0; i < txq->nb_tx_desc; i++) {
                desc->tx.tp_fe_sc_vld_ra_ri = 0;
                desc++;
        }

        return txq;
}

static int
hns3_fake_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
                         uint16_t nb_desc, unsigned int socket_id)
{
        struct hns3_adapter *hns = dev->data->dev_private;
        struct hns3_hw *hw = &hns->hw;
        struct hns3_queue_info q_info;
        struct hns3_tx_queue *txq;
        uint16_t nb_tx_q;

        if (hw->fkq_data.tx_queues[idx] != NULL) {
                hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]);
                hw->fkq_data.tx_queues[idx] = NULL;
        }

        q_info.idx = idx;
        q_info.socket_id = socket_id;
        q_info.nb_desc = nb_desc;
        q_info.type = "hns3 fake TX queue";
        q_info.ring_name = "tx_fake_ring";
        txq = hns3_alloc_txq_and_dma_zone(dev, &q_info);
        if (txq == NULL) {
                hns3_err(hw, "Failed to setup No.%u fake tx ring.", idx);
                return -ENOMEM;
        }

        /* Don't need alloc sw_ring, because upper applications don't use it */
        txq->sw_ring = NULL;
        txq->free = NULL;

        txq->hns = hns;
        txq->tx_deferred_start = false;
        txq->port_id = dev->data->port_id;
        txq->configured = true;
        nb_tx_q = dev->data->nb_tx_queues;
        txq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
                                (nb_tx_q + idx) * HNS3_TQP_REG_SIZE);

        rte_spinlock_lock(&hw->lock);
        hw->fkq_data.tx_queues[idx] = txq;
        rte_spinlock_unlock(&hw->lock);

        return 0;
}

static int
hns3_fake_rx_queue_config(struct hns3_hw *hw, uint16_t nb_queues)
{
        uint16_t old_nb_queues = hw->fkq_data.nb_fake_rx_queues;
        void **rxq;
        uint16_t i;

        if (hw->fkq_data.rx_queues == NULL && nb_queues != 0) {
                /* first time configuration */
                uint32_t size;
                size = sizeof(hw->fkq_data.rx_queues[0]) * nb_queues;
                hw->fkq_data.rx_queues = rte_zmalloc("fake_rx_queues", size,
                                                     RTE_CACHE_LINE_SIZE);
                if (hw->fkq_data.rx_queues == NULL) {
                        hw->fkq_data.nb_fake_rx_queues = 0;
                        return -ENOMEM;
                }
        } else if (hw->fkq_data.rx_queues != NULL && nb_queues != 0) {
                /* re-configure */
                rxq = hw->fkq_data.rx_queues;
                for (i = nb_queues; i < old_nb_queues; i++)
                        hns3_dev_rx_queue_release(rxq[i]);

                rxq = rte_realloc(rxq, sizeof(rxq[0]) * nb_queues,
                                  RTE_CACHE_LINE_SIZE);
                if (rxq == NULL)
                        return -ENOMEM;
                if (nb_queues > old_nb_queues) {
                        uint16_t new_qs = nb_queues - old_nb_queues;
                        memset(rxq + old_nb_queues, 0, sizeof(rxq[0]) * new_qs);
                }

                hw->fkq_data.rx_queues = rxq;
        } else if (hw->fkq_data.rx_queues != NULL && nb_queues == 0) {
                rxq = hw->fkq_data.rx_queues;
                for (i = nb_queues; i < old_nb_queues; i++)
                        hns3_dev_rx_queue_release(rxq[i]);

                rte_free(hw->fkq_data.rx_queues);
                hw->fkq_data.rx_queues = NULL;
        }

        hw->fkq_data.nb_fake_rx_queues = nb_queues;

        return 0;
}

static int
hns3_fake_tx_queue_config(struct hns3_hw *hw, uint16_t nb_queues)
{
        uint16_t old_nb_queues = hw->fkq_data.nb_fake_tx_queues;
        void **txq;
        uint16_t i;

        if (hw->fkq_data.tx_queues == NULL && nb_queues != 0) {
                /* first time configuration */
                uint32_t size;
                size = sizeof(hw->fkq_data.tx_queues[0]) * nb_queues;
                hw->fkq_data.tx_queues = rte_zmalloc("fake_tx_queues", size,
                                                     RTE_CACHE_LINE_SIZE);
                if (hw->fkq_data.tx_queues == NULL) {
                        hw->fkq_data.nb_fake_tx_queues = 0;
                        return -ENOMEM;
                }
        } else if (hw->fkq_data.tx_queues != NULL && nb_queues != 0) {
                /* re-configure */
                txq = hw->fkq_data.tx_queues;
                for (i = nb_queues; i < old_nb_queues; i++)
                        hns3_dev_tx_queue_release(txq[i]);
                txq = rte_realloc(txq, sizeof(txq[0]) * nb_queues,
                                  RTE_CACHE_LINE_SIZE);
                if (txq == NULL)
                        return -ENOMEM;
                if (nb_queues > old_nb_queues) {
                        uint16_t new_qs = nb_queues - old_nb_queues;
                        memset(txq + old_nb_queues, 0, sizeof(txq[0]) * new_qs);
                }

                hw->fkq_data.tx_queues = txq;
        } else if (hw->fkq_data.tx_queues != NULL && nb_queues == 0) {
                txq = hw->fkq_data.tx_queues;
                for (i = nb_queues; i < old_nb_queues; i++)
                        hns3_dev_tx_queue_release(txq[i]);

                rte_free(hw->fkq_data.tx_queues);
                hw->fkq_data.tx_queues = NULL;
        }
        hw->fkq_data.nb_fake_tx_queues = nb_queues;

        return 0;
}

int
hns3_set_fake_rx_or_tx_queues(struct rte_eth_dev *dev, uint16_t nb_rx_q,
                              uint16_t nb_tx_q)
{
        struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
        uint16_t rx_need_add_nb_q;
        uint16_t tx_need_add_nb_q;
        uint16_t port_id;
        uint16_t q;
        int ret;

        if (hns3_dev_indep_txrx_supported(hw))
                return 0;

        /* Setup new number of fake RX/TX queues and reconfigure device. */
        rx_need_add_nb_q = hw->cfg_max_queues - nb_rx_q;
        tx_need_add_nb_q = hw->cfg_max_queues - nb_tx_q;
        ret = hns3_fake_rx_queue_config(hw, rx_need_add_nb_q);
        if (ret) {
                hns3_err(hw, "Fail to configure fake rx queues: %d", ret);
                return ret;
        }

        ret = hns3_fake_tx_queue_config(hw, tx_need_add_nb_q);
        if (ret) {
                hns3_err(hw, "Fail to configure fake rx queues: %d", ret);
                goto cfg_fake_tx_q_fail;
        }

        /* Allocate and set up fake RX queue per Ethernet port. */
        port_id = hw->data->port_id;
        for (q = 0; q < rx_need_add_nb_q; q++) {
                ret = hns3_fake_rx_queue_setup(dev, q, HNS3_MIN_RING_DESC,
                                               rte_eth_dev_socket_id(port_id));
                if (ret)
                        goto setup_fake_rx_q_fail;
        }

        /* Allocate and set up fake TX queue per Ethernet port. */
        for (q = 0; q < tx_need_add_nb_q; q++) {
                ret = hns3_fake_tx_queue_setup(dev, q, HNS3_MIN_RING_DESC,
                                               rte_eth_dev_socket_id(port_id));
                if (ret)
                        goto setup_fake_tx_q_fail;
        }

        return 0;

setup_fake_tx_q_fail:
setup_fake_rx_q_fail:
        (void)hns3_fake_tx_queue_config(hw, 0);
cfg_fake_tx_q_fail:
        (void)hns3_fake_rx_queue_config(hw, 0);

        return ret;
}

void
hns3_dev_release_mbufs(struct hns3_adapter *hns)
{
        struct rte_eth_dev_data *dev_data = hns->hw.data;
        struct hns3_rx_queue *rxq;
        struct hns3_tx_queue *txq;
        int i;

        if (dev_data->rx_queues)
                for (i = 0; i < dev_data->nb_rx_queues; i++) {
                        rxq = dev_data->rx_queues[i];
                        if (rxq == NULL)
                                continue;
                        hns3_rx_queue_release_mbufs(rxq);
                }

        if (dev_data->tx_queues)
                for (i = 0; i < dev_data->nb_tx_queues; i++) {
                        txq = dev_data->tx_queues[i];
                        if (txq == NULL)
                                continue;
                        hns3_tx_queue_release_mbufs(txq);
                }
}

static int
hns3_rx_buf_len_calc(struct rte_mempool *mp, uint16_t *rx_buf_len)
{
        uint16_t vld_buf_size;
        uint16_t num_hw_specs;
        uint16_t i;

        /*
         * hns3 network engine only support to set 4 typical specification, and
         * different buffer size will affect the max packet_len and the max
         * number of segmentation when hw gro is turned on in receive side. The
         * relationship between them is as follows:
         *      rx_buf_size     |  max_gro_pkt_len  |  max_gro_nb_seg
         * ---------------------|-------------------|----------------
         * HNS3_4K_BD_BUF_SIZE  |        60KB       |       15
         * HNS3_2K_BD_BUF_SIZE  |        62KB       |       31
         * HNS3_1K_BD_BUF_SIZE  |        63KB       |       63
         * HNS3_512_BD_BUF_SIZE |      31.5KB       |       63
         */
        static const uint16_t hw_rx_buf_size[] = {
                HNS3_4K_BD_BUF_SIZE,
                HNS3_2K_BD_BUF_SIZE,
                HNS3_1K_BD_BUF_SIZE,
                HNS3_512_BD_BUF_SIZE
        };

        vld_buf_size = (uint16_t)(rte_pktmbuf_data_room_size(mp) -
                        RTE_PKTMBUF_HEADROOM);
        if (vld_buf_size < HNS3_MIN_BD_BUF_SIZE)
                return -EINVAL;

        num_hw_specs = RTE_DIM(hw_rx_buf_size);
        for (i = 0; i < num_hw_specs; i++) {
                if (vld_buf_size >= hw_rx_buf_size[i]) {
                        *rx_buf_len = hw_rx_buf_size[i];
                        break;
                }
        }
        return 0;
}

static int
hns3_rxq_conf_runtime_check(struct hns3_hw *hw, uint16_t buf_size,
                                uint16_t nb_desc)
{
        struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
        struct rte_eth_rxmode *rxmode = &hw->data->dev_conf.rxmode;
        eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
        uint16_t min_vec_bds;

        /*
         * HNS3 hardware network engine set scattered as default. If the driver
         * is not work in scattered mode and the pkts greater than buf_size
         * but smaller than max_rx_pkt_len will be distributed to multiple BDs.
         * Driver cannot handle this situation.
         */
        if (!hw->data->scattered_rx && rxmode->max_rx_pkt_len > buf_size) {
                hns3_err(hw, "max_rx_pkt_len is not allowed to be set greater "
                             "than rx_buf_len if scattered is off.");
                return -EINVAL;
        }

        if (pkt_burst == hns3_recv_pkts_vec) {
                min_vec_bds = HNS3_DEFAULT_RXQ_REARM_THRESH +
                              HNS3_DEFAULT_RX_BURST;
                if (nb_desc < min_vec_bds ||
                    nb_desc % HNS3_DEFAULT_RXQ_REARM_THRESH) {
                        hns3_err(hw, "if Rx burst mode is vector, "
                                 "number of descriptor is required to be "
                                 "bigger than min vector bds:%u, and could be "
                                 "divided by rxq rearm thresh:%u.",
                                 min_vec_bds, HNS3_DEFAULT_RXQ_REARM_THRESH);
                        return -EINVAL;
                }
        }
        return 0;
}

static int
hns3_rx_queue_conf_check(struct hns3_hw *hw, const struct rte_eth_rxconf *conf,
                         struct rte_mempool *mp, uint16_t nb_desc,
                         uint16_t *buf_size)
{
        int ret;

        if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC ||
            nb_desc % HNS3_ALIGN_RING_DESC) {
                hns3_err(hw, "Number (%u) of rx descriptors is invalid",
                         nb_desc);
                return -EINVAL;
        }

        if (conf->rx_drop_en == 0)
                hns3_warn(hw, "if no descriptors available, packets are always "
                          "dropped and rx_drop_en (1) is fixed on");

        if (hns3_rx_buf_len_calc(mp, buf_size)) {
                hns3_err(hw, "rxq mbufs' data room size (%u) is not enough! "
                                "minimal data room size (%u).",
                                rte_pktmbuf_data_room_size(mp),
                                HNS3_MIN_BD_BUF_SIZE + RTE_PKTMBUF_HEADROOM);
                return -EINVAL;
        }

        if (hw->data->dev_started) {
                ret = hns3_rxq_conf_runtime_check(hw, *buf_size, nb_desc);
                if (ret) {
                        hns3_err(hw, "Rx queue runtime setup fail.");
                        return ret;
                }
        }

        return 0;
}

uint32_t
hns3_get_tqp_reg_offset(uint16_t queue_id)
{
        uint32_t reg_offset;

        /* Need an extend offset to config queue > 1024 */
        if (queue_id < HNS3_MIN_EXTEND_QUEUE_ID)
                reg_offset = HNS3_TQP_REG_OFFSET + queue_id * HNS3_TQP_REG_SIZE;
        else
                reg_offset = HNS3_TQP_REG_OFFSET + HNS3_TQP_EXT_REG_OFFSET +
                             (queue_id - HNS3_MIN_EXTEND_QUEUE_ID) *
                             HNS3_TQP_REG_SIZE;

        return reg_offset;
}

int
hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
                    unsigned int socket_id, const struct rte_eth_rxconf *conf,
                    struct rte_mempool *mp)
{
        struct hns3_adapter *hns = dev->data->dev_private;
        struct hns3_hw *hw = &hns->hw;
        struct hns3_queue_info q_info;
        struct hns3_rx_queue *rxq;
        uint16_t rx_buf_size;
        int rx_entry_len;
        int ret;

        ret = hns3_rx_queue_conf_check(hw, conf, mp, nb_desc, &rx_buf_size);
        if (ret)
                return ret;

        if (dev->data->rx_queues[idx]) {
                hns3_rx_queue_release(dev->data->rx_queues[idx]);
                dev->data->rx_queues[idx] = NULL;
        }

        q_info.idx = idx;
        q_info.socket_id = socket_id;
        q_info.nb_desc = nb_desc;
        q_info.type = "hns3 RX queue";
        q_info.ring_name = "rx_ring";

        rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info);
        if (rxq == NULL) {
                hns3_err(hw,
                         "Failed to alloc mem and reserve DMA mem for rx ring!");
                return -ENOMEM;
        }

        rxq->hns = hns;
        rxq->ptype_tbl = &hns->ptype_tbl;
        rxq->mb_pool = mp;
        rxq->rx_free_thresh = (conf->rx_free_thresh > 0) ?
                conf->rx_free_thresh : HNS3_DEFAULT_RX_FREE_THRESH;

        rxq->rx_deferred_start = conf->rx_deferred_start;
        if (rxq->rx_deferred_start && !hns3_dev_indep_txrx_supported(hw)) {
                hns3_warn(hw, "deferred start is not supported.");
                rxq->rx_deferred_start = false;
        }

        rx_entry_len = (rxq->nb_rx_desc + HNS3_DEFAULT_RX_BURST) *
                        sizeof(struct hns3_entry);
        rxq->sw_ring = rte_zmalloc_socket("hns3 RX sw ring", rx_entry_len,
                                          RTE_CACHE_LINE_SIZE, socket_id);
        if (rxq->sw_ring == NULL) {
                hns3_err(hw, "Failed to allocate memory for rx sw ring!");
                hns3_rx_queue_release(rxq);
                return -ENOMEM;
        }

        rxq->next_to_use = 0;
        rxq->rx_free_hold = 0;
        rxq->rx_rearm_start = 0;
        rxq->rx_rearm_nb = 0;
        rxq->pkt_first_seg = NULL;
        rxq->pkt_last_seg = NULL;
        rxq->port_id = dev->data->port_id;
        /*
         * For hns3 PF device, if the VLAN mode is HW_SHIFT_AND_DISCARD_MODE,
         * the pvid_sw_discard_en in the queue struct should not be changed,
         * because PVID-related operations do not need to be processed by PMD
         * driver. For hns3 VF device, whether it needs to process PVID depends
         * on the configuration of PF kernel mode netdevice driver. And the
         * related PF configuration is delivered through the mailbox and finally
         * reflectd in port_base_vlan_cfg.
         */
        if (hns->is_vf || hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
                rxq->pvid_sw_discard_en = hw->port_base_vlan_cfg.state ==
                                       HNS3_PORT_BASE_VLAN_ENABLE;
        else
                rxq->pvid_sw_discard_en = false;
        rxq->ptype_en = hns3_dev_rxd_adv_layout_supported(hw) ? true : false;
        rxq->configured = true;
        rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
                                idx * HNS3_TQP_REG_SIZE);
        rxq->io_base = (void *)((char *)hw->io_base +
                                        hns3_get_tqp_reg_offset(idx));
        rxq->io_head_reg = (volatile void *)((char *)rxq->io_base +
                           HNS3_RING_RX_HEAD_REG);
        rxq->rx_buf_len = rx_buf_size;
        memset(&rxq->basic_stats, 0, sizeof(struct hns3_rx_basic_stats));
        memset(&rxq->err_stats, 0, sizeof(struct hns3_rx_bd_errors_stats));
        memset(&rxq->dfx_stats, 0, sizeof(struct hns3_rx_dfx_stats));

        /* CRC len set here is used for amending packet length */
        if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
                rxq->crc_len = RTE_ETHER_CRC_LEN;
        else
                rxq->crc_len = 0;

        rxq->bulk_mbuf_num = 0;

        rte_spinlock_lock(&hw->lock);
        dev->data->rx_queues[idx] = rxq;
        rte_spinlock_unlock(&hw->lock);

        return 0;
}

void
hns3_rx_scattered_reset(struct rte_eth_dev *dev)
{
        struct hns3_adapter *hns = dev->data->dev_private;
        struct hns3_hw *hw = &hns->hw;

        hw->rx_buf_len = 0;
        dev->data->scattered_rx = false;
}

void
hns3_rx_scattered_calc(struct rte_eth_dev *dev)
{
        struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
        struct hns3_adapter *hns = dev->data->dev_private;
        struct hns3_hw *hw = &hns->hw;
        struct hns3_rx_queue *rxq;
        uint32_t queue_id;

        if (dev->data->rx_queues == NULL)
                return;

        for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
                rxq = dev->data->rx_queues[queue_id];
                if (hw->rx_buf_len == 0)
                        hw->rx_buf_len = rxq->rx_buf_len;
                else
                        hw->rx_buf_len = RTE_MIN(hw->rx_buf_len,
                                                 rxq->rx_buf_len);
        }

        if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_SCATTER ||
            dev_conf->rxmode.max_rx_pkt_len > hw->rx_buf_len)
                dev->data->scattered_rx = true;
}

const uint32_t *
hns3_dev_supported_ptypes_get(struct rte_eth_dev *dev)
{
        static const uint32_t ptypes[] = {
                RTE_PTYPE_L2_ETHER,
                RTE_PTYPE_L2_ETHER_LLDP,
                RTE_PTYPE_L2_ETHER_ARP,
                RTE_PTYPE_L3_IPV4,
                RTE_PTYPE_L3_IPV4_EXT,
                RTE_PTYPE_L3_IPV6,
                RTE_PTYPE_L3_IPV6_EXT,
                RTE_PTYPE_L4_IGMP,
                RTE_PTYPE_L4_ICMP,
                RTE_PTYPE_L4_SCTP,
                RTE_PTYPE_L4_TCP,
                RTE_PTYPE_L4_UDP,
                RTE_PTYPE_TUNNEL_GRE,
                RTE_PTYPE_INNER_L2_ETHER,
                RTE_PTYPE_INNER_L3_IPV4,
                RTE_PTYPE_INNER_L3_IPV6,
                RTE_PTYPE_INNER_L3_IPV4_EXT,
                RTE_PTYPE_INNER_L3_IPV6_EXT,
                RTE_PTYPE_INNER_L4_UDP,
                RTE_PTYPE_INNER_L4_TCP,
                RTE_PTYPE_INNER_L4_SCTP,
                RTE_PTYPE_INNER_L4_ICMP,
                RTE_PTYPE_TUNNEL_VXLAN,
                RTE_PTYPE_TUNNEL_NVGRE,
                RTE_PTYPE_UNKNOWN
        };
        static const uint32_t adv_layout_ptypes[] = {
                RTE_PTYPE_L2_ETHER,
                RTE_PTYPE_L2_ETHER_TIMESYNC,
                RTE_PTYPE_L2_ETHER_LLDP,
                RTE_PTYPE_L2_ETHER_ARP,
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
                RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,

                RTE_PTYPE_L4_FRAG,
                RTE_PTYPE_L4_NONFRAG,
                RTE_PTYPE_L4_UDP,
                RTE_PTYPE_L4_TCP,
                RTE_PTYPE_L4_SCTP,
                RTE_PTYPE_L4_IGMP,
                RTE_PTYPE_L4_ICMP,
                RTE_PTYPE_TUNNEL_GRE,
                RTE_PTYPE_TUNNEL_GRENAT,
                RTE_PTYPE_INNER_L2_ETHER,
                RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
                RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
                RTE_PTYPE_INNER_L4_FRAG,
                RTE_PTYPE_INNER_L4_ICMP,
                RTE_PTYPE_INNER_L4_NONFRAG,
                RTE_PTYPE_INNER_L4_UDP,
                RTE_PTYPE_INNER_L4_TCP,
                RTE_PTYPE_INNER_L4_SCTP,
                RTE_PTYPE_INNER_L4_ICMP,
                RTE_PTYPE_UNKNOWN
        };
        struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);

        if (dev->rx_pkt_burst == hns3_recv_pkts_simple ||
            dev->rx_pkt_burst == hns3_recv_scattered_pkts ||
            dev->rx_pkt_burst == hns3_recv_pkts_vec ||
            dev->rx_pkt_burst == hns3_recv_pkts_vec_sve) {
                if (hns3_dev_rxd_adv_layout_supported(hw))
                        return adv_layout_ptypes;
                else
                        return ptypes;
        }

        return NULL;
}

static void
hns3_init_non_tunnel_ptype_tbl(struct hns3_ptype_table *tbl)
{
        tbl->l3table[0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4;
        tbl->l3table[1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6;
        tbl->l3table[2] = RTE_PTYPE_L2_ETHER_ARP;
        tbl->l3table[4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT;
        tbl->l3table[5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT;
        tbl->l3table[6] = RTE_PTYPE_L2_ETHER_LLDP;

        tbl->l4table[0] = RTE_PTYPE_L4_UDP;
        tbl->l4table[1] = RTE_PTYPE_L4_TCP;
        tbl->l4table[2] = RTE_PTYPE_TUNNEL_GRE;
        tbl->l4table[3] = RTE_PTYPE_L4_SCTP;
        tbl->l4table[4] = RTE_PTYPE_L4_IGMP;
        tbl->l4table[5] = RTE_PTYPE_L4_ICMP;
}

static void
hns3_init_tunnel_ptype_tbl(struct hns3_ptype_table *tbl)
{
        tbl->inner_l3table[0] = RTE_PTYPE_INNER_L2_ETHER |
                                RTE_PTYPE_INNER_L3_IPV4;
        tbl->inner_l3table[1] = RTE_PTYPE_INNER_L2_ETHER |
                                RTE_PTYPE_INNER_L3_IPV6;
        /* There is not a ptype for inner ARP/RARP */
        tbl->inner_l3table[2] = RTE_PTYPE_UNKNOWN;
        tbl->inner_l3table[3] = RTE_PTYPE_UNKNOWN;
        tbl->inner_l3table[4] = RTE_PTYPE_INNER_L2_ETHER |
                                RTE_PTYPE_INNER_L3_IPV4_EXT;
        tbl->inner_l3table[5] = RTE_PTYPE_INNER_L2_ETHER |
                                RTE_PTYPE_INNER_L3_IPV6_EXT;

        tbl->inner_l4table[0] = RTE_PTYPE_INNER_L4_UDP;
        tbl->inner_l4table[1] = RTE_PTYPE_INNER_L4_TCP;
        /* There is not a ptype for inner GRE */
        tbl->inner_l4table[2] = RTE_PTYPE_UNKNOWN;
        tbl->inner_l4table[3] = RTE_PTYPE_INNER_L4_SCTP;
        /* There is not a ptype for inner IGMP */
        tbl->inner_l4table[4] = RTE_PTYPE_UNKNOWN;
        tbl->inner_l4table[5] = RTE_PTYPE_INNER_L4_ICMP;

        tbl->ol3table[0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4;
        tbl->ol3table[1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6;
        tbl->ol3table[2] = RTE_PTYPE_UNKNOWN;
        tbl->ol3table[3] = RTE_PTYPE_UNKNOWN;
        tbl->ol3table[4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT;
        tbl->ol3table[5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT;

        tbl->ol4table[0] = RTE_PTYPE_UNKNOWN;
        tbl->ol4table[1] = RTE_PTYPE_L4_UDP | RTE_PTYPE_TUNNEL_VXLAN;
        tbl->ol4table[2] = RTE_PTYPE_TUNNEL_NVGRE;
}

static void
hns3_init_adv_layout_ptype(struct hns3_ptype_table *tbl)
{
        uint32_t *ptype = tbl->ptype;

        /* Non-tunnel L2 */
        ptype[1] = RTE_PTYPE_L2_ETHER_ARP;
        ptype[3] = RTE_PTYPE_L2_ETHER_LLDP;
        ptype[8] = RTE_PTYPE_L2_ETHER_TIMESYNC;

        /* Non-tunnel IPv4 */
        ptype[17] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_L4_FRAG;
        ptype[18] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_L4_NONFRAG;
        ptype[19] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_L4_UDP;
        ptype[20] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_L4_TCP;
        ptype[21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_TUNNEL_GRE;
        ptype[22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_L4_SCTP;
        ptype[23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_L4_IGMP;
        ptype[24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_L4_ICMP;
        /* The next ptype is PTP over IPv4 + UDP */
        ptype[25] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_L4_UDP;

        /* IPv4 --> GRE/Teredo/VXLAN */
        ptype[29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_TUNNEL_GRENAT;
        /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
        ptype[30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER;

        /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
        ptype[31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
                    RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_INNER_L4_FRAG;
        ptype[32] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
                    RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_INNER_L4_NONFRAG;
        ptype[33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
                    RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_INNER_L4_UDP;
        ptype[34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
                    RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_INNER_L4_TCP;
        ptype[35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
                    RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_INNER_L4_SCTP;
        /* The next ptype's inner L4 is IGMP */
        ptype[36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
                    RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
        ptype[37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
                    RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_INNER_L4_ICMP;

        /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
        ptype[39] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
                    RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
                    RTE_PTYPE_INNER_L4_FRAG;
        ptype[40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
                    RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
                    RTE_PTYPE_INNER_L4_NONFRAG;
        ptype[41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
                    RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
                    RTE_PTYPE_INNER_L4_UDP;
        ptype[42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
                    RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
                    RTE_PTYPE_INNER_L4_TCP;
        ptype[43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
                    RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
                    RTE_PTYPE_INNER_L4_SCTP;
        /* The next ptype's inner L4 is IGMP */
        ptype[44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
                    RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
        ptype[45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
                    RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
                    RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
                    RTE_PTYPE_INNER_L4_ICMP;

        /* Non-tunnel IPv6 */
        ptype[111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_L4_FRAG;
        ptype[112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_L4_NONFRAG;
        ptype[113] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_L4_UDP;
        ptype[114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_L4_TCP;
        ptype[115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_TUNNEL_GRE;
        ptype[116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_L4_SCTP;
        ptype[117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_L4_IGMP;
        ptype[118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_L4_ICMP;
        /* Special for PTP over IPv6 + UDP */
        ptype[119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_L4_UDP;

        /* IPv6 --> GRE/Teredo/VXLAN */
        ptype[123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_TUNNEL_GRENAT;
        /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
        ptype[124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER;

        /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
        ptype[125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
                     RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
                     RTE_PTYPE_INNER_L4_FRAG;
        ptype[126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
                     RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
                     RTE_PTYPE_INNER_L4_NONFRAG;
        ptype[127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
                     RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
                     RTE_PTYPE_INNER_L4_UDP;
        ptype[128] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
                     RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
                     RTE_PTYPE_INNER_L4_TCP;
        ptype[129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
                     RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
                     RTE_PTYPE_INNER_L4_SCTP;
        /* The next ptype's inner L4 is IGMP */
        ptype[130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
                     RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
        ptype[131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
                     RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
                     RTE_PTYPE_INNER_L4_ICMP;

        /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
        ptype[133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
                     RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_INNER_L4_FRAG;
        ptype[134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
                     RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_INNER_L4_NONFRAG;
        ptype[135] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
                     RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_INNER_L4_UDP;
        ptype[136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
                     RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_INNER_L4_TCP;
        ptype[137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
                     RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_INNER_L4_SCTP;
        /* The next ptype's inner L4 is IGMP */
        ptype[138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
                     RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
        ptype[139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
                     RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
                     RTE_PTYPE_INNER_L4_ICMP;
}

void
hns3_init_rx_ptype_tble(struct rte_eth_dev *dev)
{
        struct hns3_adapter *hns = dev->data->dev_private;
        struct hns3_ptype_table *tbl = &hns->ptype_tbl;

        memset(tbl, 0, sizeof(*tbl));

        hns3_init_non_tunnel_ptype_tbl(tbl);
        hns3_init_tunnel_ptype_tbl(tbl);
        hns3_init_adv_layout_ptype(tbl);
}

static inline void
hns3_rxd_to_vlan_tci(struct hns3_rx_queue *rxq, struct rte_mbuf *mb,
                     uint32_t l234_info, const struct hns3_desc *rxd)
{
#define HNS3_STRP_STATUS_NUM            0x4

#define HNS3_NO_STRP_VLAN_VLD           0x0
#define HNS3_INNER_STRP_VLAN_VLD        0x1
#define HNS3_OUTER_STRP_VLAN_VLD        0x2
        uint32_t strip_status;
        uint32_t report_mode;

        /*
         * Since HW limitation, the vlan tag will always be inserted into RX
         * descriptor when strip the tag from packet, driver needs to determine
         * reporting which tag to mbuf according to the PVID configuration
         * and vlan striped status.
         */
        static const uint32_t report_type[][HNS3_STRP_STATUS_NUM] = {
                {
                        HNS3_NO_STRP_VLAN_VLD,
                        HNS3_OUTER_STRP_VLAN_VLD,
                        HNS3_INNER_STRP_VLAN_VLD,
                        HNS3_OUTER_STRP_VLAN_VLD
                },
                {
                        HNS3_NO_STRP_VLAN_VLD,
                        HNS3_NO_STRP_VLAN_VLD,
                        HNS3_NO_STRP_VLAN_VLD,
                        HNS3_INNER_STRP_VLAN_VLD
                }
        };
        strip_status = hns3_get_field(l234_info, HNS3_RXD_STRP_TAGP_M,
                                      HNS3_RXD_STRP_TAGP_S);
        report_mode = report_type[rxq->pvid_sw_discard_en][strip_status];
        switch (report_mode) {
        case HNS3_NO_STRP_VLAN_VLD:
                mb->vlan_tci = 0;
                return;
        case HNS3_INNER_STRP_VLAN_VLD:
                mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
                mb->vlan_tci = rte_le_to_cpu_16(rxd->rx.vlan_tag);
                return;
        case HNS3_OUTER_STRP_VLAN_VLD:
                mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
                mb->vlan_tci = rte_le_to_cpu_16(rxd->rx.ot_vlan_tag);
                return;
        default:
                mb->vlan_tci = 0;
                return;
        }
}

static inline void
recalculate_data_len(struct rte_mbuf *first_seg, struct rte_mbuf *last_seg,
                    struct rte_mbuf *rxm, struct hns3_rx_queue *rxq,
                    uint16_t data_len)
{
        uint8_t crc_len = rxq->crc_len;

        if (data_len <= crc_len) {
                rte_pktmbuf_free_seg(rxm);
                first_seg->nb_segs--;
                last_seg->data_len = (uint16_t)(last_seg->data_len -
                        (crc_len - data_len));
                last_seg->next = NULL;
        } else
                rxm->data_len = (uint16_t)(data_len - crc_len);
}

static inline struct rte_mbuf *
hns3_rx_alloc_buffer(struct hns3_rx_queue *rxq)
{
        int ret;

        if (likely(rxq->bulk_mbuf_num > 0))
                return rxq->bulk_mbuf[--rxq->bulk_mbuf_num];

        ret = rte_mempool_get_bulk(rxq->mb_pool, (void **)rxq->bulk_mbuf,
                                   HNS3_BULK_ALLOC_MBUF_NUM);
        if (likely(ret == 0)) {
                rxq->bulk_mbuf_num = HNS3_BULK_ALLOC_MBUF_NUM;
                return rxq->bulk_mbuf[--rxq->bulk_mbuf_num];
        } else
                return rte_mbuf_raw_alloc(rxq->mb_pool);
}

static inline void
hns3_rx_ptp_timestamp_handle(struct hns3_rx_queue *rxq, struct rte_mbuf *mbuf,
                  volatile struct hns3_desc *rxd)
{
        struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(rxq->hns);
        uint64_t timestamp = rte_le_to_cpu_64(rxd->timestamp);

        mbuf->ol_flags |= PKT_RX_IEEE1588_PTP | PKT_RX_IEEE1588_TMST;
        if (hns3_timestamp_rx_dynflag > 0) {
                *RTE_MBUF_DYNFIELD(mbuf, hns3_timestamp_dynfield_offset,
                        rte_mbuf_timestamp_t *) = timestamp;
                mbuf->ol_flags |= hns3_timestamp_rx_dynflag;
        }

        pf->rx_timestamp = timestamp;
}

uint16_t
hns3_recv_pkts_simple(void *rx_queue,
                      struct rte_mbuf **rx_pkts,
                      uint16_t nb_pkts)
{
        volatile struct hns3_desc *rx_ring;  /* RX ring (desc) */
        volatile struct hns3_desc *rxdp;     /* pointer of the current desc */
        struct hns3_rx_queue *rxq;      /* RX queue */
        struct hns3_entry *sw_ring;
        struct hns3_entry *rxe;
        struct hns3_desc rxd;
        struct rte_mbuf *nmb;           /* pointer of the new mbuf */
        struct rte_mbuf *rxm;
        uint32_t bd_base_info;
        uint32_t l234_info;
        uint32_t ol_info;
        uint64_t dma_addr;
        uint16_t nb_rx_bd;
        uint16_t nb_rx;
        uint16_t rx_id;
        int ret;

        nb_rx = 0;
        nb_rx_bd = 0;
        rxq = rx_queue;
        rx_ring = rxq->rx_ring;
        sw_ring = rxq->sw_ring;
        rx_id = rxq->next_to_use;

        while (nb_rx < nb_pkts) {
                rxdp = &rx_ring[rx_id];
                bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info);
                if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
                        break;

                rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
                           (1u << HNS3_RXD_VLD_B)];

                nmb = hns3_rx_alloc_buffer(rxq);
                if (unlikely(nmb == NULL)) {
                        uint16_t port_id;

                        port_id = rxq->port_id;
                        rte_eth_devices[port_id].data->rx_mbuf_alloc_failed++;
                        break;
                }

                nb_rx_bd++;
                rxe = &sw_ring[rx_id];
                rx_id++;
                if (unlikely(rx_id == rxq->nb_rx_desc))
                        rx_id = 0;

                rte_prefetch0(sw_ring[rx_id].mbuf);
                if ((rx_id & HNS3_RX_RING_PREFETCTH_MASK) == 0) {
                        rte_prefetch0(&rx_ring[rx_id]);
                        rte_prefetch0(&sw_ring[rx_id]);
                }

                rxm = rxe->mbuf;
                rxm->ol_flags = 0;
                rxe->mbuf = nmb;

                if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B)))
                        hns3_rx_ptp_timestamp_handle(rxq, rxm, rxdp);

                dma_addr = rte_mbuf_data_iova_default(nmb);
                rxdp->addr = rte_cpu_to_le_64(dma_addr);
                rxdp->rx.bd_base_info = 0;

                rxm->data_off = RTE_PKTMBUF_HEADROOM;
                rxm->pkt_len = (uint16_t)(rte_le_to_cpu_16(rxd.rx.pkt_len)) -
                                rxq->crc_len;
                rxm->data_len = rxm->pkt_len;
                rxm->port = rxq->port_id;
                rxm->hash.rss = rte_le_to_cpu_32(rxd.rx.rss_hash);
                rxm->ol_flags |= PKT_RX_RSS_HASH;
                if (unlikely(bd_base_info & BIT(HNS3_RXD_LUM_B))) {
                        rxm->hash.fdir.hi =
                                rte_le_to_cpu_16(rxd.rx.fd_id);
                        rxm->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
                }
                rxm->nb_segs = 1;
                rxm->next = NULL;

                /* Load remained descriptor data and extract necessary fields */
                l234_info = rte_le_to_cpu_32(rxd.rx.l234_info);
                ol_info = rte_le_to_cpu_32(rxd.rx.ol_info);
                ret = hns3_handle_bdinfo(rxq, rxm, bd_base_info, l234_info);
                if (unlikely(ret))
                        goto pkt_err;

                rxm->packet_type = hns3_rx_calc_ptype(rxq, l234_info, ol_info);

                if (rxm->packet_type == RTE_PTYPE_L2_ETHER_TIMESYNC)
                        rxm->ol_flags |= PKT_RX_IEEE1588_PTP;

                hns3_rxd_to_vlan_tci(rxq, rxm, l234_info, &rxd);

                /* Increment bytes counter  */
                rxq->basic_stats.bytes += rxm->pkt_len;

                rx_pkts[nb_rx++] = rxm;
                continue;
pkt_err:
                rte_pktmbuf_free(rxm);
        }

        rxq->next_to_use = rx_id;
        rxq->rx_free_hold += nb_rx_bd;
        if (rxq->rx_free_hold > rxq->rx_free_thresh) {
                hns3_write_reg_opt(rxq->io_head_reg, rxq->rx_free_hold);
                rxq->rx_free_hold = 0;
        }

        return nb_rx;
}

uint16_t
hns3_recv_scattered_pkts(void *rx_queue,
                         struct rte_mbuf **rx_pkts,
                         uint16_t nb_pkts)
{
        volatile struct hns3_desc *rx_ring;  /* RX ring (desc) */
        volatile struct hns3_desc *rxdp;     /* pointer of the current desc */
        struct hns3_rx_queue *rxq;      /* RX queue */
        struct hns3_entry *sw_ring;
        struct hns3_entry *rxe;
        struct rte_mbuf *first_seg;
        struct rte_mbuf *last_seg;
        struct hns3_desc rxd;
        struct rte_mbuf *nmb;           /* pointer of the new mbuf */
        struct rte_mbuf *rxm;
        struct rte_eth_dev *dev;
        uint32_t bd_base_info;
        uint32_t l234_info;
        uint32_t gro_size;
        uint32_t ol_info;
        uint64_t dma_addr;
        uint16_t nb_rx_bd;
        uint16_t nb_rx;
        uint16_t rx_id;
        int ret;

        nb_rx = 0;
        nb_rx_bd = 0;
        rxq = rx_queue;

        rx_id = rxq->next_to_use;
        rx_ring = rxq->rx_ring;
        sw_ring = rxq->sw_ring;
        first_seg = rxq->pkt_first_seg;
        last_seg = rxq->pkt_last_seg;

        while (nb_rx < nb_pkts) {
                rxdp = &rx_ring[rx_id];
                bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info);
                if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
                        break;

                /*
                 * The interactive process between software and hardware of
                 * receiving a new packet in hns3 network engine:
                 * 1. Hardware network engine firstly writes the packet content
                 *    to the memory pointed by the 'addr' field of the Rx Buffer
                 *    Descriptor, secondly fills the result of parsing the
                 *    packet include the valid field into the Rx Buffer
                 *    Descriptor in one write operation.
                 * 2. Driver reads the Rx BD's valid field in the loop to check
                 *    whether it's valid, if valid then assign a new address to
                 *    the addr field, clear the valid field, get the other
                 *    information of the packet by parsing Rx BD's other fields,
                 *    finally write back the number of Rx BDs processed by the
                 *    driver to the HNS3_RING_RX_HEAD_REG register to inform
                 *    hardware.
                 * In the above process, the ordering is very important. We must
                 * make sure that CPU read Rx BD's other fields only after the
                 * Rx BD is valid.
                 *
                 * There are two type of re-ordering: compiler re-ordering and
                 * CPU re-ordering under the ARMv8 architecture.
                 * 1. we use volatile to deal with compiler re-ordering, so you
                 *    can see that rx_ring/rxdp defined with volatile.
                 * 2. we commonly use memory barrier to deal with CPU
                 *    re-ordering, but the cost is high.
                 *
                 * In order to solve the high cost of using memory barrier, we
                 * use the data dependency order under the ARMv8 architecture,
                 * for example:
                 *      instr01: load A
                 *      instr02: load B <- A
                 * the instr02 will always execute after instr01.
                 *
                 * To construct the data dependency ordering, we use the
                 * following assignment:
                 *      rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
                 *                 (1u<<HNS3_RXD_VLD_B)]
                 * Using gcc compiler under the ARMv8 architecture, the related
                 * assembly code example as follows:
                 * note: (1u << HNS3_RXD_VLD_B) equal 0x10
                 *      instr01: ldr w26, [x22, #28]  --read bd_base_info
                 *      instr02: and w0, w26, #0x10   --calc bd_base_info & 0x10
                 *      instr03: sub w0, w0, #0x10    --calc (bd_base_info &
                 *                                            0x10) - 0x10
                 *      instr04: add x0, x22, x0, lsl #5 --calc copy source addr
                 *      instr05: ldp x2, x3, [x0]
                 *      instr06: stp x2, x3, [x29, #256] --copy BD's [0 ~ 15]B
                 *      instr07: ldp x4, x5, [x0, #16]
                 *      instr08: stp x4, x5, [x29, #272] --copy BD's [16 ~ 31]B
                 * the instr05~08 depend on x0's value, x0 depent on w26's
                 * value, the w26 is the bd_base_info, this form the data
                 * dependency ordering.
                 * note: if BD is valid, (bd_base_info & (1u<<HNS3_RXD_VLD_B)) -
                 *       (1u<<HNS3_RXD_VLD_B) will always zero, so the
                 *       assignment is correct.
                 *
                 * So we use the data dependency ordering instead of memory
                 * barrier to improve receive performance.
                 */
                rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
                           (1u << HNS3_RXD_VLD_B)];

                nmb = hns3_rx_alloc_buffer(rxq);
                if (unlikely(nmb == NULL)) {
                        dev = &rte_eth_devices[rxq->port_id];
                        dev->data->rx_mbuf_alloc_failed++;
                        break;
                }

                nb_rx_bd++;
                rxe = &sw_ring[rx_id];
                rx_id++;
                if (unlikely(rx_id == rxq->nb_rx_desc))
                        rx_id = 0;

                rte_prefetch0(sw_ring[rx_id].mbuf);
                if ((rx_id & HNS3_RX_RING_PREFETCTH_MASK) == 0) {
                        rte_prefetch0(&rx_ring[rx_id]);
                        rte_prefetch0(&sw_ring[rx_id]);
                }

                rxm = rxe->mbuf;
                rxe->mbuf = nmb;

                dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
                rxdp->rx.bd_base_info = 0;
                rxdp->addr = dma_addr;

                if (first_seg == NULL) {
                        first_seg = rxm;
                        first_seg->nb_segs = 1;
                } else {
                        first_seg->nb_segs++;
                        last_seg->next = rxm;
                }

                rxm->data_off = RTE_PKTMBUF_HEADROOM;
                rxm->data_len = rte_le_to_cpu_16(rxd.rx.size);

                if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) {
                        last_seg = rxm;
                        rxm->next = NULL;
                        continue;
                }

                if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B)))
                        hns3_rx_ptp_timestamp_handle(rxq, first_seg, rxdp);

                /*
                 * The last buffer of the received packet. packet len from
                 * buffer description may contains CRC len, packet len should
                 * subtract it, same as data len.
                 */
                first_seg->pkt_len = rte_le_to_cpu_16(rxd.rx.pkt_len);

                /*
                 * This is the last buffer of the received packet. If the CRC
                 * is not stripped by the hardware:
                 *  - Subtract the CRC length from the total packet length.
                 *  - If the last buffer only contains the whole CRC or a part
                 *  of it, free the mbuf associated to the last buffer. If part
                 *  of the CRC is also contained in the previous mbuf, subtract
                 *  the length of that CRC part from the data length of the
                 *  previous mbuf.
                 */
                rxm->next = NULL;
                if (unlikely(rxq->crc_len > 0)) {
                        first_seg->pkt_len -= rxq->crc_len;
                        recalculate_data_len(first_seg, last_seg, rxm, rxq,
                                rxm->data_len);
                }

                first_seg->port = rxq->port_id;
                first_seg->hash.rss = rte_le_to_cpu_32(rxd.rx.rss_hash);
                first_seg->ol_flags = PKT_RX_RSS_HASH;
                if (unlikely(bd_base_info & BIT(HNS3_RXD_LUM_B))) {
                        first_seg->hash.fdir.hi =
                                rte_le_to_cpu_16(rxd.rx.fd_id);
                        first_seg->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
                }

                gro_size = hns3_get_field(bd_base_info, HNS3_RXD_GRO_SIZE_M,
                                          HNS3_RXD_GRO_SIZE_S);
                if (gro_size != 0) {
                        first_seg->ol_flags |= PKT_RX_LRO;
                        first_seg->tso_segsz = gro_size;
                }

                l234_info = rte_le_to_cpu_32(rxd.rx.l234_info);
                ol_info = rte_le_to_cpu_32(rxd.rx.ol_info);
                ret = hns3_handle_bdinfo(rxq, first_seg, bd_base_info,
                                         l234_info);
                if (unlikely(ret))
                        goto pkt_err;

                first_seg->packet_type = hns3_rx_calc_ptype(rxq,
                                                l234_info, ol_info);

                if (first_seg->packet_type == RTE_PTYPE_L2_ETHER_TIMESYNC)
                        rxm->ol_flags |= PKT_RX_IEEE1588_PTP;

                hns3_rxd_to_vlan_tci(rxq, first_seg, l234_info, &rxd);

                /* Increment bytes counter */
                rxq->basic_stats.bytes += first_seg->pkt_len;

                rx_pkts[nb_rx++] = first_seg;
                first_seg = NULL;
                continue;
pkt_err:
                rte_pktmbuf_free(first_seg);
                first_seg = NULL;
        }

        rxq->next_to_use = rx_id;
        rxq->pkt_first_seg = first_seg;
        rxq->pkt_last_seg = last_seg;

        rxq->rx_free_hold += nb_rx_bd;
        if (rxq->rx_free_hold > rxq->rx_free_thresh) {
                hns3_write_reg_opt(rxq->io_head_reg, rxq->rx_free_hold);
                rxq->rx_free_hold = 0;
        }

        return nb_rx;
}

void __rte_weak
hns3_rxq_vec_setup(__rte_unused struct hns3_rx_queue *rxq)
{
}

int __rte_weak
hns3_rx_check_vec_support(__rte_unused struct rte_eth_dev *dev)
{
        return -ENOTSUP;
}

uint16_t __rte_weak
hns3_recv_pkts_vec(__rte_unused void *tx_queue,
                   __rte_unused struct rte_mbuf **rx_pkts,
                   __rte_unused uint16_t nb_pkts)
{
        return 0;
}

uint16_t __rte_weak
hns3_recv_pkts_vec_sve(__rte_unused void *tx_queue,
                       __rte_unused struct rte_mbuf **rx_pkts,
                       __rte_unused uint16_t nb_pkts)
{
        return 0;
}

int
hns3_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
                       struct rte_eth_burst_mode *mode)
{
        static const struct {
                eth_rx_burst_t pkt_burst;
                const char *info;
        } burst_infos[] = {
                { hns3_recv_pkts_simple,        "Scalar Simple" },
                { hns3_recv_scattered_pkts,     "Scalar Scattered" },
                { hns3_recv_pkts_vec,           "Vector Neon"   },
                { hns3_recv_pkts_vec_sve,       "Vector Sve"    },
        };

        eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
        int ret = -EINVAL;
        unsigned int i;

        for (i = 0; i < RTE_DIM(burst_infos); i++) {
                if (pkt_burst == burst_infos[i].pkt_burst) {
                        snprintf(mode->info, sizeof(mode->info), "%s",
                                 burst_infos[i].info);
                        ret = 0;
                        break;
                }
        }

        return ret;
}

static bool
hns3_get_default_vec_support(void)
{
#if defined(RTE_ARCH_ARM64)
        if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_128)
                return false;
        if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON))
                return true;
#endif
        return false;
}

static bool
hns3_get_sve_support(void)
{
#if defined(RTE_HAS_SVE_ACLE)
        if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_256)
                return false;
        if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE))
                return true;
#endif
        return false;
}

static eth_rx_burst_t
hns3_get_rx_function(struct rte_eth_dev *dev)
{
        struct hns3_adapter *hns = dev->data->dev_private;
        uint64_t offloads = dev->data->dev_conf.rxmode.offloads;
        bool vec_allowed, sve_allowed, simple_allowed;
        bool vec_support;

        vec_support = hns3_rx_check_vec_support(dev) == 0;
        vec_allowed = vec_support && hns3_get_default_vec_support();
        sve_allowed = vec_support && hns3_get_sve_support();
        simple_allowed = !dev->data->scattered_rx &&
                         (offloads & DEV_RX_OFFLOAD_TCP_LRO) == 0;

        if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_VEC && vec_allowed)
                return hns3_recv_pkts_vec;
        if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_SVE && sve_allowed)
                return hns3_recv_pkts_vec_sve;
        if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_SIMPLE && simple_allowed)
                return hns3_recv_pkts_simple;
        if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_COMMON)
                return hns3_recv_scattered_pkts;

        if (vec_allowed)
                return hns3_recv_pkts_vec;
        if (simple_allowed)
                return hns3_recv_pkts_simple;

        return hns3_recv_scattered_pkts;
}

static int
hns3_tx_queue_conf_check(struct hns3_hw *hw, const struct rte_eth_txconf *conf,
                         uint16_t nb_desc, uint16_t *tx_rs_thresh,
                         uint16_t *tx_free_thresh, uint16_t idx)
{
#define HNS3_TX_RS_FREE_THRESH_GAP      8
        uint16_t rs_thresh, free_thresh, fast_free_thresh;

        if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC ||
            nb_desc % HNS3_ALIGN_RING_DESC) {
                hns3_err(hw, "number (%u) of tx descriptors is invalid",
                         nb_desc);
                return -EINVAL;
        }

        rs_thresh = (conf->tx_rs_thresh > 0) ?
                        conf->tx_rs_thresh : HNS3_DEFAULT_TX_RS_THRESH;
        free_thresh = (conf->tx_free_thresh > 0) ?
                        conf->tx_free_thresh : HNS3_DEFAULT_TX_FREE_THRESH;
        if (rs_thresh + free_thresh > nb_desc || nb_desc % rs_thresh ||
            rs_thresh >= nb_desc - HNS3_TX_RS_FREE_THRESH_GAP ||
            free_thresh >= nb_desc - HNS3_TX_RS_FREE_THRESH_GAP) {
                hns3_err(hw, "tx_rs_thresh (%u) tx_free_thresh (%u) nb_desc "
                         "(%u) of tx descriptors for port=%u queue=%u check "
                         "fail!",
                         rs_thresh, free_thresh, nb_desc, hw->data->port_id,
                         idx);
                return -EINVAL;
        }

        if (conf->tx_free_thresh == 0) {
                /* Fast free Tx memory buffer to improve cache hit rate */
                fast_free_thresh = nb_desc - rs_thresh;
                if (fast_free_thresh >=
                    HNS3_TX_FAST_FREE_AHEAD + HNS3_DEFAULT_TX_FREE_THRESH)
                        free_thresh = fast_free_thresh -
                                        HNS3_TX_FAST_FREE_AHEAD;
        }

        *tx_rs_thresh = rs_thresh;
        *tx_free_thresh = free_thresh;
        return 0;
}

static void *
hns3_tx_push_get_queue_tail_reg(struct rte_eth_dev *dev, uint16_t queue_id)
{
#define HNS3_TX_PUSH_TQP_REGION_SIZE            0x10000
#define HNS3_TX_PUSH_QUICK_DOORBELL_OFFSET      64
#define HNS3_TX_PUSH_PCI_BAR_INDEX              4

        struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
        uint8_t bar_id = HNS3_TX_PUSH_PCI_BAR_INDEX;

        /*
         * If device support Tx push then its PCIe bar45 must exist, and DPDK
         * framework will mmap the bar45 default in PCI probe stage.
         *
         * In the bar45, the first half is for RoCE (RDMA over Converged
         * Ethernet), and the second half is for NIC, every TQP occupy 64KB.
         *
         * The quick doorbell located at 64B offset in the TQP region.
         */
        return (char *)pci_dev->mem_resource[bar_id].addr +
                        (pci_dev->mem_resource[bar_id].len >> 1) +
                        HNS3_TX_PUSH_TQP_REGION_SIZE * queue_id +
                        HNS3_TX_PUSH_QUICK_DOORBELL_OFFSET;
}

void
hns3_tx_push_init(struct rte_eth_dev *dev)
{
        struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
        volatile uint32_t *reg;
        uint32_t val;

        if (!hns3_dev_tx_push_supported(hw))
                return;

        reg = (volatile uint32_t *)hns3_tx_push_get_queue_tail_reg(dev, 0);
        /*
         * Because the size of bar45 is about 8GB size, it may take a long time
         * to do the page fault in Tx process when work with vfio-pci, so use
         * one read operation to make kernel setup page table mapping for bar45
         * in the init stage.
         * Note: the bar45 is readable but the result is all 1.
         */
        val = *reg;
        RTE_SET_USED(val);
}

static void
hns3_tx_push_queue_init(struct rte_eth_dev *dev,
                        uint16_t queue_id,
                        struct hns3_tx_queue *txq)
{
        struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
        if (!hns3_dev_tx_push_supported(hw)) {
                txq->tx_push_enable = false;
                return;
        }

        txq->io_tail_reg = (volatile void *)hns3_tx_push_get_queue_tail_reg(dev,
                                                queue_id);
        txq->tx_push_enable = true;
}

int
hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
                    unsigned int socket_id, const struct rte_eth_txconf *conf)
{
        struct hns3_adapter *hns = dev->data->dev_private;
        uint16_t tx_rs_thresh, tx_free_thresh;
        struct hns3_hw *hw = &hns->hw;
        struct hns3_queue_info q_info;
        struct hns3_tx_queue *txq;
        int tx_entry_len;
        int ret;

        ret = hns3_tx_queue_conf_check(hw, conf, nb_desc,
                                       &tx_rs_thresh, &tx_free_thresh, idx);
        if (ret)
                return ret;

        if (dev->data->tx_queues[idx] != NULL) {
                hns3_tx_queue_release(dev->data->tx_queues[idx]);
                dev->data->tx_queues[idx] = NULL;
        }

        q_info.idx = idx;
        q_info.socket_id = socket_id;
        q_info.nb_desc = nb_desc;
        q_info.type = "hns3 TX queue";
        q_info.ring_name = "tx_ring";
        txq = hns3_alloc_txq_and_dma_zone(dev, &q_info);
        if (txq == NULL) {
                hns3_err(hw,
                         "Failed to alloc mem and reserve DMA mem for tx ring!");
                return -ENOMEM;
        }

        txq->tx_deferred_start = conf->tx_deferred_start;
        if (txq->tx_deferred_start && !hns3_dev_indep_txrx_supported(hw)) {
                hns3_warn(hw, "deferred start is not supported.");
                txq->tx_deferred_start = false;
        }