LXR dpdk/drivers/net/igc/base/igc

   1/* SPDX-License-Identifier: BSD-3-Clause
   2 * Copyright(c) 2001-2020 Intel Corporation
   3 */
   4
   5#ifndef _IGC_I225_H_
   6#define _IGC_I225_H_
   7
   8bool igc_get_flash_presence_i225(struct igc_hw *hw);
   9s32 igc_update_flash_i225(struct igc_hw *hw);
  10s32 igc_update_nvm_checksum_i225(struct igc_hw *hw);
  11s32 igc_validate_nvm_checksum_i225(struct igc_hw *hw);
  12s32 igc_write_nvm_srwr_i225(struct igc_hw *hw, u16 offset,
  13                              u16 words, u16 *data);
  14s32 igc_read_nvm_srrd_i225(struct igc_hw *hw, u16 offset,
  15                             u16 words, u16 *data);
  16s32 igc_read_invm_version_i225(struct igc_hw *hw,
  17                                 struct igc_fw_version *invm_ver);
  18s32 igc_set_flsw_flash_burst_counter_i225(struct igc_hw *hw,
  19                                            u32 burst_counter);
  20s32 igc_write_erase_flash_command_i225(struct igc_hw *hw, u32 opcode,
  21                                         u32 address);
  22s32 igc_check_for_link_i225(struct igc_hw *hw);
  23s32 igc_acquire_swfw_sync_i225(struct igc_hw *hw, u16 mask);
  24void igc_release_swfw_sync_i225(struct igc_hw *hw, u16 mask);
  25s32 igc_init_hw_i225(struct igc_hw *hw);
  26s32 igc_setup_copper_link_i225(struct igc_hw *hw);
  27s32 igc_set_d0_lplu_state_i225(struct igc_hw *hw, bool active);
  28s32 igc_set_d3_lplu_state_i225(struct igc_hw *hw, bool active);
  29s32 igc_set_eee_i225(struct igc_hw *hw, bool adv2p5G, bool adv1G,
  30                       bool adv100M);
  31
  32#define ID_LED_DEFAULT_I225             ((ID_LED_OFF1_ON2  << 8) | \
  33                                         (ID_LED_DEF1_DEF2 <<  4) | \
  34                                         (ID_LED_OFF1_OFF2))
  35#define ID_LED_DEFAULT_I225_SERDES      ((ID_LED_DEF1_DEF2 << 8) | \
  36                                         (ID_LED_DEF1_DEF2 <<  4) | \
  37                                         (ID_LED_OFF1_ON2))
  38
  39/* NVM offset defaults for I225 devices */
  40#define NVM_INIT_CTRL_2_DEFAULT_I225    0X7243
  41#define NVM_INIT_CTRL_4_DEFAULT_I225    0x00C1
  42#define NVM_LED_1_CFG_DEFAULT_I225      0x0184
  43#define NVM_LED_0_2_CFG_DEFAULT_I225    0x200C
  44
  45#define IGC_MRQC_ENABLE_RSS_4Q          0x00000002
  46#define IGC_MRQC_ENABLE_VMDQ                    0x00000003
  47#define IGC_MRQC_ENABLE_VMDQ_RSS_2Q             0x00000005
  48#define IGC_MRQC_RSS_FIELD_IPV4_UDP             0x00400000
  49#define IGC_MRQC_RSS_FIELD_IPV6_UDP             0x00800000
  50#define IGC_MRQC_RSS_FIELD_IPV6_UDP_EX  0x01000000
  51#define IGC_I225_SHADOW_RAM_SIZE                4096
  52#define IGC_I225_ERASE_CMD_OPCODE               0x02000000
  53#define IGC_I225_WRITE_CMD_OPCODE               0x01000000
  54#define IGC_FLSWCTL_DONE                        0x40000000
  55#define IGC_FLSWCTL_CMDV                        0x10000000
  56
  57/* SRRCTL bit definitions */
  58#define IGC_SRRCTL_BSIZEHDRSIZE_MASK            0x00000F00
  59#define IGC_SRRCTL_DESCTYPE_LEGACY              0x00000000
  60#define IGC_SRRCTL_DESCTYPE_HDR_SPLIT           0x04000000
  61#define IGC_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS    0x0A000000
  62#define IGC_SRRCTL_DESCTYPE_HDR_REPLICATION     0x06000000
  63#define IGC_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
  64#define IGC_SRRCTL_DESCTYPE_MASK                0x0E000000
  65#define IGC_SRRCTL_DROP_EN                      0x80000000
  66#define IGC_SRRCTL_BSIZEPKT_MASK                0x0000007F
  67#define IGC_SRRCTL_BSIZEHDR_MASK                0x00003F00
  68
  69#define IGC_RXDADV_RSSTYPE_MASK 0x0000000F
  70#define IGC_RXDADV_RSSTYPE_SHIFT        12
  71#define IGC_RXDADV_HDRBUFLEN_MASK       0x7FE0
  72#define IGC_RXDADV_HDRBUFLEN_SHIFT      5
  73#define IGC_RXDADV_SPLITHEADER_EN       0x00001000
  74#define IGC_RXDADV_SPH          0x8000
  75#define IGC_RXDADV_STAT_TS              0x10000 /* Pkt was time stamped */
  76#define IGC_RXDADV_ERR_HBO              0x00800000
  77
  78/* RSS Hash results */
  79#define IGC_RXDADV_RSSTYPE_NONE 0x00000000
  80#define IGC_RXDADV_RSSTYPE_IPV4_TCP     0x00000001
  81#define IGC_RXDADV_RSSTYPE_IPV4 0x00000002
  82#define IGC_RXDADV_RSSTYPE_IPV6_TCP     0x00000003
  83#define IGC_RXDADV_RSSTYPE_IPV6_EX      0x00000004
  84#define IGC_RXDADV_RSSTYPE_IPV6 0x00000005
  85#define IGC_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
  86#define IGC_RXDADV_RSSTYPE_IPV4_UDP     0x00000007
  87#define IGC_RXDADV_RSSTYPE_IPV6_UDP     0x00000008
  88#define IGC_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
  89
  90/* RSS Packet Types as indicated in the receive descriptor */
  91#define IGC_RXDADV_PKTTYPE_ILMASK       0x000000F0
  92#define IGC_RXDADV_PKTTYPE_TLMASK       0x00000F00
  93#define IGC_RXDADV_PKTTYPE_NONE 0x00000000
  94#define IGC_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPV4 hdr present */
  95#define IGC_RXDADV_PKTTYPE_IPV4_EX      0x00000020 /* IPV4 hdr + extensions */
  96#define IGC_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPV6 hdr present */
  97#define IGC_RXDADV_PKTTYPE_IPV6_EX      0x00000080 /* IPV6 hdr + extensions */
  98#define IGC_RXDADV_PKTTYPE_TCP  0x00000100 /* TCP hdr present */
  99#define IGC_RXDADV_PKTTYPE_UDP  0x00000200 /* UDP hdr present */
 100#define IGC_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
 101#define IGC_RXDADV_PKTTYPE_NFS  0x00000800 /* NFS hdr present */
 102
 103#define IGC_RXDADV_PKTTYPE_IPSEC_ESP    0x00001000 /* IPSec ESP */
 104#define IGC_RXDADV_PKTTYPE_IPSEC_AH     0x00002000 /* IPSec AH */
 105#define IGC_RXDADV_PKTTYPE_LINKSEC      0x00004000 /* LinkSec Encap */
 106#define IGC_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */
 107#define IGC_RXDADV_PKTTYPE_ETQF_MASK    0x00000070 /* ETQF has 8 indices */
 108#define IGC_RXDADV_PKTTYPE_ETQF_SHIFT   4 /* Right-shift 4 bits */
 109
 110#endif
 111