1
2
3
4
5#include "igc_api.h"
6
7static s32 igc_wait_autoneg(struct igc_hw *hw);
8static s32 igc_access_phy_wakeup_reg_bm(struct igc_hw *hw, u32 offset,
9 u16 *data, bool read, bool page_set);
10static u32 igc_get_phy_addr_for_hv_page(u32 page);
11static s32 igc_access_phy_debug_regs_hv(struct igc_hw *hw, u32 offset,
12 u16 *data, bool read);
13
14
15static const u16 igc_m88_cable_length_table[] = {
16 0, 50, 80, 110, 140, 140, IGC_CABLE_LENGTH_UNDEFINED };
17#define M88IGC_CABLE_LENGTH_TABLE_SIZE \
18 (sizeof(igc_m88_cable_length_table) / \
19 sizeof(igc_m88_cable_length_table[0]))
20
21static const u16 igc_igp_2_cable_length_table[] = {
22 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
23 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
24 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
25 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
26 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
27 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
28 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
29 124};
30#define IGP02IGC_CABLE_LENGTH_TABLE_SIZE \
31 (sizeof(igc_igp_2_cable_length_table) / \
32 sizeof(igc_igp_2_cable_length_table[0]))
33
34
35
36
37
38
39
40void igc_init_phy_ops_generic(struct igc_hw *hw)
41{
42 struct igc_phy_info *phy = &hw->phy;
43 DEBUGFUNC("igc_init_phy_ops_generic");
44
45
46 phy->ops.init_params = igc_null_ops_generic;
47 phy->ops.acquire = igc_null_ops_generic;
48 phy->ops.check_polarity = igc_null_ops_generic;
49 phy->ops.check_reset_block = igc_null_ops_generic;
50 phy->ops.commit = igc_null_ops_generic;
51 phy->ops.force_speed_duplex = igc_null_ops_generic;
52 phy->ops.get_cfg_done = igc_null_ops_generic;
53 phy->ops.get_cable_length = igc_null_ops_generic;
54 phy->ops.get_info = igc_null_ops_generic;
55 phy->ops.set_page = igc_null_set_page;
56 phy->ops.read_reg = igc_null_read_reg;
57 phy->ops.read_reg_locked = igc_null_read_reg;
58 phy->ops.read_reg_page = igc_null_read_reg;
59 phy->ops.release = igc_null_phy_generic;
60 phy->ops.reset = igc_null_ops_generic;
61 phy->ops.set_d0_lplu_state = igc_null_lplu_state;
62 phy->ops.set_d3_lplu_state = igc_null_lplu_state;
63 phy->ops.write_reg = igc_null_write_reg;
64 phy->ops.write_reg_locked = igc_null_write_reg;
65 phy->ops.write_reg_page = igc_null_write_reg;
66 phy->ops.power_up = igc_null_phy_generic;
67 phy->ops.power_down = igc_null_phy_generic;
68 phy->ops.read_i2c_byte = igc_read_i2c_byte_null;
69 phy->ops.write_i2c_byte = igc_write_i2c_byte_null;
70 phy->ops.cfg_on_link_up = igc_null_ops_generic;
71}
72
73
74
75
76
77
78s32 igc_null_set_page(struct igc_hw IGC_UNUSEDARG * hw,
79 u16 IGC_UNUSEDARG data)
80{
81 DEBUGFUNC("igc_null_set_page");
82 UNREFERENCED_2PARAMETER(hw, data);
83 return IGC_SUCCESS;
84}
85
86
87
88
89
90
91
92s32 igc_null_read_reg(struct igc_hw IGC_UNUSEDARG * hw,
93 u32 IGC_UNUSEDARG offset, u16 IGC_UNUSEDARG * data)
94{
95 DEBUGFUNC("igc_null_read_reg");
96 UNREFERENCED_3PARAMETER(hw, offset, data);
97 return IGC_SUCCESS;
98}
99
100
101
102
103
104void igc_null_phy_generic(struct igc_hw IGC_UNUSEDARG * hw)
105{
106 DEBUGFUNC("igc_null_phy_generic");
107 UNREFERENCED_1PARAMETER(hw);
108}
109
110
111
112
113
114
115s32 igc_null_lplu_state(struct igc_hw IGC_UNUSEDARG * hw,
116 bool IGC_UNUSEDARG active)
117{
118 DEBUGFUNC("igc_null_lplu_state");
119 UNREFERENCED_2PARAMETER(hw, active);
120 return IGC_SUCCESS;
121}
122
123
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126
127
128
129s32 igc_null_write_reg(struct igc_hw IGC_UNUSEDARG * hw,
130 u32 IGC_UNUSEDARG offset, u16 IGC_UNUSEDARG data)
131{
132 DEBUGFUNC("igc_null_write_reg");
133 UNREFERENCED_3PARAMETER(hw, offset, data);
134 return IGC_SUCCESS;
135}
136
137
138
139
140
141
142
143
144
145s32 igc_read_i2c_byte_null(struct igc_hw IGC_UNUSEDARG * hw,
146 u8 IGC_UNUSEDARG byte_offset,
147 u8 IGC_UNUSEDARG dev_addr,
148 u8 IGC_UNUSEDARG * data)
149{
150 DEBUGFUNC("igc_read_i2c_byte_null");
151 UNREFERENCED_4PARAMETER(hw, byte_offset, dev_addr, data);
152 return IGC_SUCCESS;
153}
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162
163s32 igc_write_i2c_byte_null(struct igc_hw IGC_UNUSEDARG * hw,
164 u8 IGC_UNUSEDARG byte_offset,
165 u8 IGC_UNUSEDARG dev_addr,
166 u8 IGC_UNUSEDARG data)
167{
168 DEBUGFUNC("igc_write_i2c_byte_null");
169 UNREFERENCED_4PARAMETER(hw, byte_offset, dev_addr, data);
170 return IGC_SUCCESS;
171}
172
173
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176
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178
179
180
181s32 igc_check_reset_block_generic(struct igc_hw *hw)
182{
183 u32 manc;
184
185 DEBUGFUNC("igc_check_reset_block");
186
187 manc = IGC_READ_REG(hw, IGC_MANC);
188
189 return (manc & IGC_MANC_BLK_PHY_RST_ON_IDE) ?
190 IGC_BLK_PHY_RESET : IGC_SUCCESS;
191}
192
193
194
195
196
197
198
199
200s32 igc_get_phy_id(struct igc_hw *hw)
201{
202 struct igc_phy_info *phy = &hw->phy;
203 s32 ret_val = IGC_SUCCESS;
204 u16 phy_id;
205 u16 retry_count = 0;
206
207 DEBUGFUNC("igc_get_phy_id");
208
209 if (!phy->ops.read_reg)
210 return IGC_SUCCESS;
211
212 while (retry_count < 2) {
213 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
214 if (ret_val)
215 return ret_val;
216
217 phy->id = (u32)(phy_id << 16);
218 usec_delay(20);
219 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
220 if (ret_val)
221 return ret_val;
222
223 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
224 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
225
226 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
227 return IGC_SUCCESS;
228
229 retry_count++;
230 }
231
232 return IGC_SUCCESS;
233}
234
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236
237
238
239
240
241s32 igc_phy_reset_dsp_generic(struct igc_hw *hw)
242{
243 s32 ret_val;
244
245 DEBUGFUNC("igc_phy_reset_dsp_generic");
246
247 if (!hw->phy.ops.write_reg)
248 return IGC_SUCCESS;
249
250 ret_val = hw->phy.ops.write_reg(hw, M88IGC_PHY_GEN_CONTROL, 0xC1);
251 if (ret_val)
252 return ret_val;
253
254 return hw->phy.ops.write_reg(hw, M88IGC_PHY_GEN_CONTROL, 0);
255}
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265
266s32 igc_read_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 *data)
267{
268 struct igc_phy_info *phy = &hw->phy;
269 u32 i, mdic = 0;
270
271 DEBUGFUNC("igc_read_phy_reg_mdic");
272
273 if (offset > MAX_PHY_REG_ADDRESS) {
274 DEBUGOUT1("PHY Address %d is out of range\n", offset);
275 return -IGC_ERR_PARAM;
276 }
277
278
279
280
281
282 mdic = ((offset << IGC_MDIC_REG_SHIFT) |
283 (phy->addr << IGC_MDIC_PHY_SHIFT) |
284 (IGC_MDIC_OP_READ));
285
286 IGC_WRITE_REG(hw, IGC_MDIC, mdic);
287
288
289
290
291
292 for (i = 0; i < (IGC_GEN_POLL_TIMEOUT * 3); i++) {
293 usec_delay_irq(50);
294 mdic = IGC_READ_REG(hw, IGC_MDIC);
295 if (mdic & IGC_MDIC_READY)
296 break;
297 }
298 if (!(mdic & IGC_MDIC_READY)) {
299 DEBUGOUT("MDI Read did not complete\n");
300 return -IGC_ERR_PHY;
301 }
302 if (mdic & IGC_MDIC_ERROR) {
303 DEBUGOUT("MDI Error\n");
304 return -IGC_ERR_PHY;
305 }
306 if (((mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT) != offset) {
307 DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n",
308 offset,
309 (mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT);
310 return -IGC_ERR_PHY;
311 }
312 *data = (u16)mdic;
313
314
315
316
317 if (hw->mac.type == igc_pch2lan)
318 usec_delay_irq(100);
319
320 return IGC_SUCCESS;
321}
322
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330
331s32 igc_write_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 data)
332{
333 struct igc_phy_info *phy = &hw->phy;
334 u32 i, mdic = 0;
335
336 DEBUGFUNC("igc_write_phy_reg_mdic");
337
338 if (offset > MAX_PHY_REG_ADDRESS) {
339 DEBUGOUT1("PHY Address %d is out of range\n", offset);
340 return -IGC_ERR_PARAM;
341 }
342
343
344
345
346
347 mdic = (((u32)data) |
348 (offset << IGC_MDIC_REG_SHIFT) |
349 (phy->addr << IGC_MDIC_PHY_SHIFT) |
350 (IGC_MDIC_OP_WRITE));
351
352 IGC_WRITE_REG(hw, IGC_MDIC, mdic);
353
354
355
356
357
358 for (i = 0; i < (IGC_GEN_POLL_TIMEOUT * 3); i++) {
359 usec_delay_irq(50);
360 mdic = IGC_READ_REG(hw, IGC_MDIC);
361 if (mdic & IGC_MDIC_READY)
362 break;
363 }
364 if (!(mdic & IGC_MDIC_READY)) {
365 DEBUGOUT("MDI Write did not complete\n");
366 return -IGC_ERR_PHY;
367 }
368 if (mdic & IGC_MDIC_ERROR) {
369 DEBUGOUT("MDI Error\n");
370 return -IGC_ERR_PHY;
371 }
372 if (((mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT) != offset) {
373 DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n",
374 offset,
375 (mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT);
376 return -IGC_ERR_PHY;
377 }
378
379
380
381
382 if (hw->mac.type == igc_pch2lan)
383 usec_delay_irq(100);
384
385 return IGC_SUCCESS;
386}
387
388
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391
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395
396
397s32 igc_read_phy_reg_i2c(struct igc_hw *hw, u32 offset, u16 *data)
398{
399 struct igc_phy_info *phy = &hw->phy;
400 u32 i, i2ccmd = 0;
401
402 DEBUGFUNC("igc_read_phy_reg_i2c");
403
404
405
406
407
408 i2ccmd = ((offset << IGC_I2CCMD_REG_ADDR_SHIFT) |
409 (phy->addr << IGC_I2CCMD_PHY_ADDR_SHIFT) |
410 (IGC_I2CCMD_OPCODE_READ));
411
412 IGC_WRITE_REG(hw, IGC_I2CCMD, i2ccmd);
413
414
415 for (i = 0; i < IGC_I2CCMD_PHY_TIMEOUT; i++) {
416 usec_delay(50);
417 i2ccmd = IGC_READ_REG(hw, IGC_I2CCMD);
418 if (i2ccmd & IGC_I2CCMD_READY)
419 break;
420 }
421 if (!(i2ccmd & IGC_I2CCMD_READY)) {
422 DEBUGOUT("I2CCMD Read did not complete\n");
423 return -IGC_ERR_PHY;
424 }
425 if (i2ccmd & IGC_I2CCMD_ERROR) {
426 DEBUGOUT("I2CCMD Error bit set\n");
427 return -IGC_ERR_PHY;
428 }
429
430
431 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
432
433 return IGC_SUCCESS;
434}
435
436
437
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439
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442
443
444s32 igc_write_phy_reg_i2c(struct igc_hw *hw, u32 offset, u16 data)
445{
446 struct igc_phy_info *phy = &hw->phy;
447 u32 i, i2ccmd = 0;
448 u16 phy_data_swapped;
449
450 DEBUGFUNC("igc_write_phy_reg_i2c");
451
452
453 if (hw->phy.addr == 0 || hw->phy.addr > 7) {
454 DEBUGOUT1("PHY I2C Address %d is out of range.\n",
455 hw->phy.addr);
456 return -IGC_ERR_CONFIG;
457 }
458
459
460 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
461
462
463
464
465
466 i2ccmd = ((offset << IGC_I2CCMD_REG_ADDR_SHIFT) |
467 (phy->addr << IGC_I2CCMD_PHY_ADDR_SHIFT) |
468 IGC_I2CCMD_OPCODE_WRITE |
469 phy_data_swapped);
470
471 IGC_WRITE_REG(hw, IGC_I2CCMD, i2ccmd);
472
473
474 for (i = 0; i < IGC_I2CCMD_PHY_TIMEOUT; i++) {
475 usec_delay(50);
476 i2ccmd = IGC_READ_REG(hw, IGC_I2CCMD);
477 if (i2ccmd & IGC_I2CCMD_READY)
478 break;
479 }
480 if (!(i2ccmd & IGC_I2CCMD_READY)) {
481 DEBUGOUT("I2CCMD Write did not complete\n");
482 return -IGC_ERR_PHY;
483 }
484 if (i2ccmd & IGC_I2CCMD_ERROR) {
485 DEBUGOUT("I2CCMD Error bit set\n");
486 return -IGC_ERR_PHY;
487 }
488
489 return IGC_SUCCESS;
490}
491
492
493
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495
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497
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504
505s32 igc_read_sfp_data_byte(struct igc_hw *hw, u16 offset, u8 *data)
506{
507 u32 i = 0;
508 u32 i2ccmd = 0;
509 u32 data_local = 0;
510
511 DEBUGFUNC("igc_read_sfp_data_byte");
512
513 if (offset > IGC_I2CCMD_SFP_DIAG_ADDR(255)) {
514 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
515 return -IGC_ERR_PHY;
516 }
517
518
519
520
521
522 i2ccmd = ((offset << IGC_I2CCMD_REG_ADDR_SHIFT) |
523 IGC_I2CCMD_OPCODE_READ);
524
525 IGC_WRITE_REG(hw, IGC_I2CCMD, i2ccmd);
526
527
528 for (i = 0; i < IGC_I2CCMD_PHY_TIMEOUT; i++) {
529 usec_delay(50);
530 data_local = IGC_READ_REG(hw, IGC_I2CCMD);
531 if (data_local & IGC_I2CCMD_READY)
532 break;
533 }
534 if (!(data_local & IGC_I2CCMD_READY)) {
535 DEBUGOUT("I2CCMD Read did not complete\n");
536 return -IGC_ERR_PHY;
537 }
538 if (data_local & IGC_I2CCMD_ERROR) {
539 DEBUGOUT("I2CCMD Error bit set\n");
540 return -IGC_ERR_PHY;
541 }
542 *data = (u8)data_local & 0xFF;
543
544 return IGC_SUCCESS;
545}
546
547
548
549
550
551
552
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554
555
556
557
558
559
560s32 igc_write_sfp_data_byte(struct igc_hw *hw, u16 offset, u8 data)
561{
562 u32 i = 0;
563 u32 i2ccmd = 0;
564 u32 data_local = 0;
565
566 DEBUGFUNC("igc_write_sfp_data_byte");
567
568 if (offset > IGC_I2CCMD_SFP_DIAG_ADDR(255)) {
569 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
570 return -IGC_ERR_PHY;
571 }
572
573
574
575
576
577
578
579
580
581 i2ccmd = ((offset << IGC_I2CCMD_REG_ADDR_SHIFT) |
582 IGC_I2CCMD_OPCODE_READ);
583
584 IGC_WRITE_REG(hw, IGC_I2CCMD, i2ccmd);
585 for (i = 0; i < IGC_I2CCMD_PHY_TIMEOUT; i++) {
586 usec_delay(50);
587
588
589
590 i2ccmd = IGC_READ_REG(hw, IGC_I2CCMD);
591 if (i2ccmd & IGC_I2CCMD_READY) {
592
593 if ((i2ccmd & IGC_I2CCMD_OPCODE_READ) ==
594 IGC_I2CCMD_OPCODE_READ) {
595
596
597
598 data_local = i2ccmd & 0xFF00;
599 data_local |= (u32)data;
600 i2ccmd = ((offset <<
601 IGC_I2CCMD_REG_ADDR_SHIFT) |
602 IGC_I2CCMD_OPCODE_WRITE | data_local);
603 IGC_WRITE_REG(hw, IGC_I2CCMD, i2ccmd);
604 } else {
605 break;
606 }
607 }
608 }
609 if (!(i2ccmd & IGC_I2CCMD_READY)) {
610 DEBUGOUT("I2CCMD Write did not complete\n");
611 return -IGC_ERR_PHY;
612 }
613 if (i2ccmd & IGC_I2CCMD_ERROR) {
614 DEBUGOUT("I2CCMD Error bit set\n");
615 return -IGC_ERR_PHY;
616 }
617 return IGC_SUCCESS;
618}
619
620
621
622
623
624
625
626
627
628
629
630s32 igc_read_phy_reg_m88(struct igc_hw *hw, u32 offset, u16 *data)
631{
632 s32 ret_val;
633
634 DEBUGFUNC("igc_read_phy_reg_m88");
635
636 if (!hw->phy.ops.acquire)
637 return IGC_SUCCESS;
638
639 ret_val = hw->phy.ops.acquire(hw);
640 if (ret_val)
641 return ret_val;
642
643 ret_val = igc_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
644 data);
645
646 hw->phy.ops.release(hw);
647
648 return ret_val;
649}
650
651
652
653
654
655
656
657
658
659
660s32 igc_write_phy_reg_m88(struct igc_hw *hw, u32 offset, u16 data)
661{
662 s32 ret_val;
663
664 DEBUGFUNC("igc_write_phy_reg_m88");
665
666 if (!hw->phy.ops.acquire)
667 return IGC_SUCCESS;
668
669 ret_val = hw->phy.ops.acquire(hw);
670 if (ret_val)
671 return ret_val;
672
673 ret_val = igc_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
674 data);
675
676 hw->phy.ops.release(hw);
677
678 return ret_val;
679}
680
681
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686
687
688
689
690s32 igc_set_page_igp(struct igc_hw *hw, u16 page)
691{
692 DEBUGFUNC("igc_set_page_igp");
693
694 DEBUGOUT1("Setting page 0x%x\n", page);
695
696 hw->phy.addr = 1;
697
698 return igc_write_phy_reg_mdic(hw, IGP01IGC_PHY_PAGE_SELECT, page);
699}
700
701
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710
711
712static s32 __igc_read_phy_reg_igp(struct igc_hw *hw, u32 offset, u16 *data,
713 bool locked)
714{
715 s32 ret_val = IGC_SUCCESS;
716
717 DEBUGFUNC("__igc_read_phy_reg_igp");
718
719 if (!locked) {
720 if (!hw->phy.ops.acquire)
721 return IGC_SUCCESS;
722
723 ret_val = hw->phy.ops.acquire(hw);
724 if (ret_val)
725 return ret_val;
726 }
727
728 if (offset > MAX_PHY_MULTI_PAGE_REG)
729 ret_val = igc_write_phy_reg_mdic(hw,
730 IGP01IGC_PHY_PAGE_SELECT,
731 (u16)offset);
732 if (!ret_val)
733 ret_val = igc_read_phy_reg_mdic(hw,
734 MAX_PHY_REG_ADDRESS & offset,
735 data);
736 if (!locked)
737 hw->phy.ops.release(hw);
738
739 return ret_val;
740}
741
742
743
744
745
746
747
748
749
750
751
752s32 igc_read_phy_reg_igp(struct igc_hw *hw, u32 offset, u16 *data)
753{
754 return __igc_read_phy_reg_igp(hw, offset, data, false);
755}
756
757
758
759
760
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762
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764
765
766s32 igc_read_phy_reg_igp_locked(struct igc_hw *hw, u32 offset, u16 *data)
767{
768 return __igc_read_phy_reg_igp(hw, offset, data, true);
769}
770
771
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779
780
781static s32 __igc_write_phy_reg_igp(struct igc_hw *hw, u32 offset, u16 data,
782 bool locked)
783{
784 s32 ret_val = IGC_SUCCESS;
785
786 DEBUGFUNC("igc_write_phy_reg_igp");
787
788 if (!locked) {
789 if (!hw->phy.ops.acquire)
790 return IGC_SUCCESS;
791
792 ret_val = hw->phy.ops.acquire(hw);
793 if (ret_val)
794 return ret_val;
795 }
796
797 if (offset > MAX_PHY_MULTI_PAGE_REG)
798 ret_val = igc_write_phy_reg_mdic(hw,
799 IGP01IGC_PHY_PAGE_SELECT,
800 (u16)offset);
801 if (!ret_val)
802 ret_val = igc_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
803 offset,
804 data);
805 if (!locked)
806 hw->phy.ops.release(hw);
807
808 return ret_val;
809}
810
811
812
813
814
815
816
817
818
819
820s32 igc_write_phy_reg_igp(struct igc_hw *hw, u32 offset, u16 data)
821{
822 return __igc_write_phy_reg_igp(hw, offset, data, false);
823}
824
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832
833
834s32 igc_write_phy_reg_igp_locked(struct igc_hw *hw, u32 offset, u16 data)
835{
836 return __igc_write_phy_reg_igp(hw, offset, data, true);
837}
838
839
840
841
842
843
844
845
846
847
848
849
850static s32 __igc_read_kmrn_reg(struct igc_hw *hw, u32 offset, u16 *data,
851 bool locked)
852{
853 u32 kmrnctrlsta;
854
855 DEBUGFUNC("__igc_read_kmrn_reg");
856
857 if (!locked) {
858 s32 ret_val = IGC_SUCCESS;
859
860 if (!hw->phy.ops.acquire)
861 return IGC_SUCCESS;
862
863 ret_val = hw->phy.ops.acquire(hw);
864 if (ret_val)
865 return ret_val;
866 }
867
868 kmrnctrlsta = ((offset << IGC_KMRNCTRLSTA_OFFSET_SHIFT) &
869 IGC_KMRNCTRLSTA_OFFSET) | IGC_KMRNCTRLSTA_REN;
870 IGC_WRITE_REG(hw, IGC_KMRNCTRLSTA, kmrnctrlsta);
871 IGC_WRITE_FLUSH(hw);
872
873 usec_delay(2);
874
875 kmrnctrlsta = IGC_READ_REG(hw, IGC_KMRNCTRLSTA);
876 *data = (u16)kmrnctrlsta;
877
878 if (!locked)
879 hw->phy.ops.release(hw);
880
881 return IGC_SUCCESS;
882}
883
884
885
886
887
888
889
890
891
892
893
894s32 igc_read_kmrn_reg_generic(struct igc_hw *hw, u32 offset, u16 *data)
895{
896 return __igc_read_kmrn_reg(hw, offset, data, false);
897}
898
899
900
901
902
903
904
905
906
907
908
909s32 igc_read_kmrn_reg_locked(struct igc_hw *hw, u32 offset, u16 *data)
910{
911 return __igc_read_kmrn_reg(hw, offset, data, true);
912}
913
914
915
916
917
918
919
920
921
922
923
924
925static s32 __igc_write_kmrn_reg(struct igc_hw *hw, u32 offset, u16 data,
926 bool locked)
927{
928 u32 kmrnctrlsta;
929
930 DEBUGFUNC("igc_write_kmrn_reg_generic");
931
932 if (!locked) {
933 s32 ret_val = IGC_SUCCESS;
934
935 if (!hw->phy.ops.acquire)
936 return IGC_SUCCESS;
937
938 ret_val = hw->phy.ops.acquire(hw);
939 if (ret_val)
940 return ret_val;
941 }
942
943 kmrnctrlsta = ((offset << IGC_KMRNCTRLSTA_OFFSET_SHIFT) &
944 IGC_KMRNCTRLSTA_OFFSET) | data;
945 IGC_WRITE_REG(hw, IGC_KMRNCTRLSTA, kmrnctrlsta);
946 IGC_WRITE_FLUSH(hw);
947
948 usec_delay(2);
949
950 if (!locked)
951 hw->phy.ops.release(hw);
952
953 return IGC_SUCCESS;
954}
955
956
957
958
959
960
961
962
963
964
965s32 igc_write_kmrn_reg_generic(struct igc_hw *hw, u32 offset, u16 data)
966{
967 return __igc_write_kmrn_reg(hw, offset, data, false);
968}
969
970
971
972
973
974
975
976
977
978
979s32 igc_write_kmrn_reg_locked(struct igc_hw *hw, u32 offset, u16 data)
980{
981 return __igc_write_kmrn_reg(hw, offset, data, true);
982}
983
984
985
986
987
988
989
990static s32 igc_set_master_slave_mode(struct igc_hw *hw)
991{
992 s32 ret_val;
993 u16 phy_data;
994
995
996 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
997 if (ret_val)
998 return ret_val;
999
1000
1001 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
1002 ((phy_data & CR_1000T_MS_VALUE) ?
1003 igc_ms_force_master :
1004 igc_ms_force_slave) : igc_ms_auto;
1005
1006 switch (hw->phy.ms_type) {
1007 case igc_ms_force_master:
1008 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1009 break;
1010 case igc_ms_force_slave:
1011 phy_data |= CR_1000T_MS_ENABLE;
1012 phy_data &= ~(CR_1000T_MS_VALUE);
1013 break;
1014 case igc_ms_auto:
1015 phy_data &= ~CR_1000T_MS_ENABLE;
1016
1017 default:
1018 break;
1019 }
1020
1021 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
1022}
1023
1024
1025
1026
1027
1028
1029
1030s32 igc_copper_link_setup_82577(struct igc_hw *hw)
1031{
1032 s32 ret_val;
1033 u16 phy_data;
1034
1035 DEBUGFUNC("igc_copper_link_setup_82577");
1036
1037 if (hw->phy.type == igc_phy_82580) {
1038 ret_val = hw->phy.ops.reset(hw);
1039 if (ret_val) {
1040 DEBUGOUT("Error resetting the PHY.\n");
1041 return ret_val;
1042 }
1043 }
1044
1045
1046 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
1047 if (ret_val)
1048 return ret_val;
1049
1050 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
1051
1052
1053 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
1054
1055 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
1056 if (ret_val)
1057 return ret_val;
1058
1059
1060 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
1061 if (ret_val)
1062 return ret_val;
1063 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
1064
1065
1066
1067
1068
1069 switch (hw->phy.mdix) {
1070 case 1:
1071 break;
1072 case 2:
1073 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
1074 break;
1075 case 0:
1076 default:
1077 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
1078 break;
1079 }
1080 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
1081 if (ret_val)
1082 return ret_val;
1083
1084 return igc_set_master_slave_mode(hw);
1085}
1086
1087
1088
1089
1090
1091
1092
1093
1094s32 igc_copper_link_setup_m88(struct igc_hw *hw)
1095{
1096 struct igc_phy_info *phy = &hw->phy;
1097 s32 ret_val;
1098 u16 phy_data;
1099
1100 DEBUGFUNC("igc_copper_link_setup_m88");
1101
1102
1103
1104 ret_val = phy->ops.read_reg(hw, M88IGC_PHY_SPEC_CTRL, &phy_data);
1105 if (ret_val)
1106 return ret_val;
1107
1108
1109 if (phy->type != igc_phy_bm)
1110 phy_data |= M88IGC_PSCR_ASSERT_CRS_ON_TX;
1111
1112
1113
1114
1115
1116
1117
1118
1119 phy_data &= ~M88IGC_PSCR_AUTO_X_MODE;
1120
1121 switch (phy->mdix) {
1122 case 1:
1123 phy_data |= M88IGC_PSCR_MDI_MANUAL_MODE;
1124 break;
1125 case 2:
1126 phy_data |= M88IGC_PSCR_MDIX_MANUAL_MODE;
1127 break;
1128 case 3:
1129 phy_data |= M88IGC_PSCR_AUTO_X_1000T;
1130 break;
1131 case 0:
1132 default:
1133 phy_data |= M88IGC_PSCR_AUTO_X_MODE;
1134 break;
1135 }
1136
1137
1138
1139
1140
1141
1142
1143 phy_data &= ~M88IGC_PSCR_POLARITY_REVERSAL;
1144 if (phy->disable_polarity_correction)
1145 phy_data |= M88IGC_PSCR_POLARITY_REVERSAL;
1146
1147
1148 if (phy->type == igc_phy_bm) {
1149
1150 if (phy->id == BMIGC_E_PHY_ID_R2) {
1151 phy_data &= ~BMIGC_PSCR_ENABLE_DOWNSHIFT;
1152 ret_val = phy->ops.write_reg(hw, M88IGC_PHY_SPEC_CTRL,
1153 phy_data);
1154 if (ret_val)
1155 return ret_val;
1156
1157 ret_val = phy->ops.commit(hw);
1158 if (ret_val) {
1159 DEBUGOUT("Error committing the PHY changes\n");
1160 return ret_val;
1161 }
1162 }
1163
1164 phy_data |= BMIGC_PSCR_ENABLE_DOWNSHIFT;
1165 }
1166
1167 ret_val = phy->ops.write_reg(hw, M88IGC_PHY_SPEC_CTRL, phy_data);
1168 if (ret_val)
1169 return ret_val;
1170
1171 if (phy->type == igc_phy_m88 && phy->revision < IGC_REVISION_4 &&
1172 phy->id != BMIGC_E_PHY_ID_R2) {
1173
1174
1175
1176 ret_val = phy->ops.read_reg(hw, M88IGC_EXT_PHY_SPEC_CTRL,
1177 &phy_data);
1178 if (ret_val)
1179 return ret_val;
1180
1181 phy_data |= M88IGC_EPSCR_TX_CLK_25;
1182
1183 if (phy->revision == IGC_REVISION_2 &&
1184 phy->id == M88E1111_I_PHY_ID) {
1185
1186 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
1187 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1188 } else {
1189
1190 phy_data &= ~(M88IGC_EPSCR_MASTER_DOWNSHIFT_MASK |
1191 M88IGC_EPSCR_SLAVE_DOWNSHIFT_MASK);
1192 phy_data |= (M88IGC_EPSCR_MASTER_DOWNSHIFT_1X |
1193 M88IGC_EPSCR_SLAVE_DOWNSHIFT_1X);
1194 }
1195 ret_val = phy->ops.write_reg(hw, M88IGC_EXT_PHY_SPEC_CTRL,
1196 phy_data);
1197 if (ret_val)
1198 return ret_val;
1199 }
1200
1201 if (phy->type == igc_phy_bm && phy->id == BMIGC_E_PHY_ID_R2) {
1202
1203 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
1204 if (ret_val)
1205 return ret_val;
1206
1207
1208 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
1209 if (ret_val)
1210 return ret_val;
1211 }
1212
1213
1214 ret_val = phy->ops.commit(hw);
1215 if (ret_val) {
1216 DEBUGOUT("Error committing the PHY changes\n");
1217 return ret_val;
1218 }
1219
1220 if (phy->type == igc_phy_82578) {
1221 ret_val = phy->ops.read_reg(hw, M88IGC_EXT_PHY_SPEC_CTRL,
1222 &phy_data);
1223 if (ret_val)
1224 return ret_val;
1225
1226
1227 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
1228 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
1229 ret_val = phy->ops.write_reg(hw, M88IGC_EXT_PHY_SPEC_CTRL,
1230 phy_data);
1231 if (ret_val)
1232 return ret_val;
1233 }
1234
1235 return IGC_SUCCESS;
1236}
1237
1238
1239
1240
1241
1242
1243
1244
1245s32 igc_copper_link_setup_m88_gen2(struct igc_hw *hw)
1246{
1247 struct igc_phy_info *phy = &hw->phy;
1248 s32 ret_val;
1249 u16 phy_data;
1250
1251 DEBUGFUNC("igc_copper_link_setup_m88_gen2");
1252
1253
1254
1255 ret_val = phy->ops.read_reg(hw, M88IGC_PHY_SPEC_CTRL, &phy_data);
1256 if (ret_val)
1257 return ret_val;
1258
1259
1260
1261
1262
1263
1264
1265
1266 phy_data &= ~M88IGC_PSCR_AUTO_X_MODE;
1267
1268 switch (phy->mdix) {
1269 case 1:
1270 phy_data |= M88IGC_PSCR_MDI_MANUAL_MODE;
1271 break;
1272 case 2:
1273 phy_data |= M88IGC_PSCR_MDIX_MANUAL_MODE;
1274 break;
1275 case 3:
1276
1277 if (phy->id != M88E1112_E_PHY_ID) {
1278 phy_data |= M88IGC_PSCR_AUTO_X_1000T;
1279 break;
1280 }
1281
1282 case 0:
1283 default:
1284 phy_data |= M88IGC_PSCR_AUTO_X_MODE;
1285 break;
1286 }
1287
1288
1289
1290
1291
1292
1293
1294 phy_data &= ~M88IGC_PSCR_POLARITY_REVERSAL;
1295 if (phy->disable_polarity_correction)
1296 phy_data |= M88IGC_PSCR_POLARITY_REVERSAL;
1297
1298
1299 if (phy->id == M88E1543_E_PHY_ID) {
1300 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;
1301 ret_val =
1302 phy->ops.write_reg(hw, M88IGC_PHY_SPEC_CTRL, phy_data);
1303 if (ret_val)
1304 return ret_val;
1305
1306 ret_val = phy->ops.commit(hw);
1307 if (ret_val) {
1308 DEBUGOUT("Error committing the PHY changes\n");
1309 return ret_val;
1310 }
1311 }
1312
1313 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
1314 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
1315 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
1316
1317 ret_val = phy->ops.write_reg(hw, M88IGC_PHY_SPEC_CTRL, phy_data);
1318 if (ret_val)
1319 return ret_val;
1320
1321
1322 ret_val = phy->ops.commit(hw);
1323 if (ret_val) {
1324 DEBUGOUT("Error committing the PHY changes\n");
1325 return ret_val;
1326 }
1327
1328 ret_val = igc_set_master_slave_mode(hw);
1329 if (ret_val)
1330 return ret_val;
1331
1332 return IGC_SUCCESS;
1333}
1334
1335
1336
1337
1338
1339
1340
1341
1342s32 igc_copper_link_setup_igp(struct igc_hw *hw)
1343{
1344 struct igc_phy_info *phy = &hw->phy;
1345 s32 ret_val;
1346 u16 data;
1347
1348 DEBUGFUNC("igc_copper_link_setup_igp");
1349
1350
1351 ret_val = hw->phy.ops.reset(hw);
1352 if (ret_val) {
1353 DEBUGOUT("Error resetting the PHY.\n");
1354 return ret_val;
1355 }
1356
1357
1358
1359
1360 msec_delay(100);
1361
1362
1363
1364
1365 if (phy->type == igc_phy_igp) {
1366
1367 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);
1368 if (ret_val) {
1369 DEBUGOUT("Error Disabling LPLU D3\n");
1370 return ret_val;
1371 }
1372 }
1373
1374
1375 if (hw->phy.ops.set_d0_lplu_state) {
1376 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
1377 if (ret_val) {
1378 DEBUGOUT("Error Disabling LPLU D0\n");
1379 return ret_val;
1380 }
1381 }
1382
1383 ret_val = phy->ops.read_reg(hw, IGP01IGC_PHY_PORT_CTRL, &data);
1384 if (ret_val)
1385 return ret_val;
1386
1387 data &= ~IGP01IGC_PSCR_AUTO_MDIX;
1388
1389 switch (phy->mdix) {
1390 case 1:
1391 data &= ~IGP01IGC_PSCR_FORCE_MDI_MDIX;
1392 break;
1393 case 2:
1394 data |= IGP01IGC_PSCR_FORCE_MDI_MDIX;
1395 break;
1396 case 0:
1397 default:
1398 data |= IGP01IGC_PSCR_AUTO_MDIX;
1399 break;
1400 }
1401 ret_val = phy->ops.write_reg(hw, IGP01IGC_PHY_PORT_CTRL, data);
1402 if (ret_val)
1403 return ret_val;
1404
1405
1406 if (hw->mac.autoneg) {
1407
1408
1409
1410
1411 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1412
1413 ret_val = phy->ops.read_reg(hw,
1414 IGP01IGC_PHY_PORT_CONFIG,
1415 &data);
1416 if (ret_val)
1417 return ret_val;
1418
1419 data &= ~IGP01IGC_PSCFR_SMART_SPEED;
1420 ret_val = phy->ops.write_reg(hw,
1421 IGP01IGC_PHY_PORT_CONFIG,
1422 data);
1423 if (ret_val)
1424 return ret_val;
1425
1426
1427 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1428 if (ret_val)
1429 return ret_val;
1430
1431 data &= ~CR_1000T_MS_ENABLE;
1432 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1433 if (ret_val)
1434 return ret_val;
1435 }
1436
1437 ret_val = igc_set_master_slave_mode(hw);
1438 }
1439
1440 return ret_val;
1441}
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452s32 igc_phy_setup_autoneg(struct igc_hw *hw)
1453{
1454 struct igc_phy_info *phy = &hw->phy;
1455 s32 ret_val;
1456 u16 mii_autoneg_adv_reg;
1457 u16 mii_1000t_ctrl_reg = 0;
1458 u16 aneg_multigbt_an_ctrl = 0;
1459
1460 DEBUGFUNC("igc_phy_setup_autoneg");
1461
1462 phy->autoneg_advertised &= phy->autoneg_mask;
1463
1464
1465 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1466 if (ret_val)
1467 return ret_val;
1468
1469 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1470
1471 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1472 &mii_1000t_ctrl_reg);
1473 if (ret_val)
1474 return ret_val;
1475 }
1476
1477 if ((phy->autoneg_mask & ADVERTISE_2500_FULL) &&
1478 hw->phy.id == I225_I_PHY_ID) {
1479
1480 ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK <<
1481 MMD_DEVADDR_SHIFT) |
1482 ANEG_MULTIGBT_AN_CTRL,
1483 &aneg_multigbt_an_ctrl);
1484
1485 if (ret_val)
1486 return ret_val;
1487 }
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1501 NWAY_AR_100TX_HD_CAPS |
1502 NWAY_AR_10T_FD_CAPS |
1503 NWAY_AR_10T_HD_CAPS);
1504 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1505
1506 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1507
1508
1509 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1510 DEBUGOUT("Advertise 10mb Half duplex\n");
1511 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1512 }
1513
1514
1515 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1516 DEBUGOUT("Advertise 10mb Full duplex\n");
1517 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1518 }
1519
1520
1521 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1522 DEBUGOUT("Advertise 100mb Half duplex\n");
1523 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1524 }
1525
1526
1527 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1528 DEBUGOUT("Advertise 100mb Full duplex\n");
1529 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1530 }
1531
1532
1533 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1534 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1535
1536
1537 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1538 DEBUGOUT("Advertise 1000mb Full duplex\n");
1539 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1540 }
1541
1542
1543 if (phy->autoneg_advertised & ADVERTISE_2500_HALF)
1544 DEBUGOUT("Advertise 2500mb Half duplex request denied!\n");
1545
1546
1547 if (phy->autoneg_advertised & ADVERTISE_2500_FULL) {
1548 DEBUGOUT("Advertise 2500mb Full duplex\n");
1549 aneg_multigbt_an_ctrl |= CR_2500T_FD_CAPS;
1550 } else {
1551 aneg_multigbt_an_ctrl &= ~CR_2500T_FD_CAPS;
1552 }
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571 switch (hw->fc.current_mode) {
1572 case igc_fc_none:
1573
1574
1575
1576 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1577 break;
1578 case igc_fc_rx_pause:
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1589 break;
1590 case igc_fc_tx_pause:
1591
1592
1593
1594 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1595 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1596 break;
1597 case igc_fc_full:
1598
1599
1600
1601 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1602 break;
1603 default:
1604 DEBUGOUT("Flow control param set incorrectly\n");
1605 return -IGC_ERR_CONFIG;
1606 }
1607
1608 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1609 if (ret_val)
1610 return ret_val;
1611
1612 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1613
1614 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1615 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
1616 mii_1000t_ctrl_reg);
1617
1618 if ((phy->autoneg_mask & ADVERTISE_2500_FULL) &&
1619 hw->phy.id == I225_I_PHY_ID)
1620 ret_val = phy->ops.write_reg(hw,
1621 (STANDARD_AN_REG_MASK <<
1622 MMD_DEVADDR_SHIFT) |
1623 ANEG_MULTIGBT_AN_CTRL,
1624 aneg_multigbt_an_ctrl);
1625
1626 return ret_val;
1627}
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638s32 igc_copper_link_autoneg(struct igc_hw *hw)
1639{
1640 struct igc_phy_info *phy = &hw->phy;
1641 s32 ret_val;
1642 u16 phy_ctrl;
1643
1644 DEBUGFUNC("igc_copper_link_autoneg");
1645
1646
1647
1648
1649 phy->autoneg_advertised &= phy->autoneg_mask;
1650
1651
1652
1653
1654 if (!phy->autoneg_advertised)
1655 phy->autoneg_advertised = phy->autoneg_mask;
1656
1657 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1658 ret_val = igc_phy_setup_autoneg(hw);
1659 if (ret_val) {
1660 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1661 return ret_val;
1662 }
1663 DEBUGOUT("Restarting Auto-Neg\n");
1664
1665
1666
1667
1668 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1669 if (ret_val)
1670 return ret_val;
1671
1672 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1673 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1674 if (ret_val)
1675 return ret_val;
1676
1677
1678
1679
1680 if (phy->autoneg_wait_to_complete) {
1681 ret_val = igc_wait_autoneg(hw);
1682 if (ret_val) {
1683 DEBUGOUT("Error while waiting for autoneg to complete\n");
1684 return ret_val;
1685 }
1686 }
1687
1688 hw->mac.get_link_status = true;
1689
1690 return ret_val;
1691}
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702s32 igc_setup_copper_link_generic(struct igc_hw *hw)
1703{
1704 s32 ret_val;
1705 bool link = false;
1706
1707 DEBUGFUNC("igc_setup_copper_link_generic");
1708
1709 if (hw->mac.autoneg) {
1710
1711
1712
1713 ret_val = igc_copper_link_autoneg(hw);
1714 if (ret_val)
1715 return ret_val;
1716 } else {
1717
1718
1719
1720 DEBUGOUT("Forcing Speed and Duplex\n");
1721 ret_val = hw->phy.ops.force_speed_duplex(hw);
1722 if (ret_val) {
1723 DEBUGOUT("Error Forcing Speed and Duplex\n");
1724 return ret_val;
1725 }
1726 }
1727
1728
1729
1730
1731 ret_val = igc_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1732 &link);
1733 if (ret_val)
1734 return ret_val;
1735
1736 if (link) {
1737 DEBUGOUT("Valid link established!!!\n");
1738 hw->mac.ops.config_collision_dist(hw);
1739 ret_val = igc_config_fc_after_link_up_generic(hw);
1740 } else {
1741 DEBUGOUT("Unable to establish link!!!\n");
1742 }
1743
1744 return ret_val;
1745}
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755s32 igc_phy_force_speed_duplex_igp(struct igc_hw *hw)
1756{
1757 struct igc_phy_info *phy = &hw->phy;
1758 s32 ret_val;
1759 u16 phy_data;
1760 bool link;
1761
1762 DEBUGFUNC("igc_phy_force_speed_duplex_igp");
1763
1764 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1765 if (ret_val)
1766 return ret_val;
1767
1768 igc_phy_force_speed_duplex_setup(hw, &phy_data);
1769
1770 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1771 if (ret_val)
1772 return ret_val;
1773
1774
1775
1776
1777 ret_val = phy->ops.read_reg(hw, IGP01IGC_PHY_PORT_CTRL, &phy_data);
1778 if (ret_val)
1779 return ret_val;
1780
1781 phy_data &= ~IGP01IGC_PSCR_AUTO_MDIX;
1782 phy_data &= ~IGP01IGC_PSCR_FORCE_MDI_MDIX;
1783
1784 ret_val = phy->ops.write_reg(hw, IGP01IGC_PHY_PORT_CTRL, phy_data);
1785 if (ret_val)
1786 return ret_val;
1787
1788 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1789
1790 usec_delay(1);
1791
1792 if (phy->autoneg_wait_to_complete) {
1793 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1794
1795 ret_val = igc_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1796 100000, &link);
1797 if (ret_val)
1798 return ret_val;
1799
1800 if (!link)
1801 DEBUGOUT("Link taking longer than expected.\n");
1802
1803
1804 ret_val = igc_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1805 100000, &link);
1806 }
1807
1808 return ret_val;
1809}
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821s32 igc_phy_force_speed_duplex_m88(struct igc_hw *hw)
1822{
1823 struct igc_phy_info *phy = &hw->phy;
1824 s32 ret_val;
1825 u16 phy_data;
1826 bool link;
1827
1828 DEBUGFUNC("igc_phy_force_speed_duplex_m88");
1829
1830
1831 if (phy->type != igc_phy_i210) {
1832
1833
1834
1835 ret_val = phy->ops.read_reg(hw, M88IGC_PHY_SPEC_CTRL,
1836 &phy_data);
1837 if (ret_val)
1838 return ret_val;
1839
1840 phy_data &= ~M88IGC_PSCR_AUTO_X_MODE;
1841 ret_val = phy->ops.write_reg(hw, M88IGC_PHY_SPEC_CTRL,
1842 phy_data);
1843 if (ret_val)
1844 return ret_val;
1845
1846 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1847 }
1848
1849 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1850 if (ret_val)
1851 return ret_val;
1852
1853 igc_phy_force_speed_duplex_setup(hw, &phy_data);
1854
1855 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1856 if (ret_val)
1857 return ret_val;
1858
1859
1860 ret_val = hw->phy.ops.commit(hw);
1861 if (ret_val)
1862 return ret_val;
1863
1864 if (phy->autoneg_wait_to_complete) {
1865 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1866
1867 ret_val = igc_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1868 100000, &link);
1869 if (ret_val)
1870 return ret_val;
1871
1872 if (!link) {
1873 bool reset_dsp = true;
1874
1875 switch (hw->phy.id) {
1876 case I347AT4_E_PHY_ID:
1877 case M88E1340M_E_PHY_ID:
1878 case M88E1112_E_PHY_ID:
1879 case M88E1543_E_PHY_ID:
1880 case M88E1512_E_PHY_ID:
1881 case I210_I_PHY_ID:
1882
1883 case I225_I_PHY_ID:
1884
1885 reset_dsp = false;
1886 break;
1887 default:
1888 if (hw->phy.type != igc_phy_m88)
1889 reset_dsp = false;
1890 break;
1891 }
1892
1893 if (!reset_dsp) {
1894 DEBUGOUT("Link taking longer than expected.\n");
1895 } else {
1896
1897
1898
1899 ret_val = phy->ops.write_reg(hw,
1900 M88IGC_PHY_PAGE_SELECT,
1901 0x001d);
1902 if (ret_val)
1903 return ret_val;
1904 ret_val = igc_phy_reset_dsp_generic(hw);
1905 if (ret_val)
1906 return ret_val;
1907 }
1908 }
1909
1910
1911 ret_val = igc_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1912 100000, &link);
1913 if (ret_val)
1914 return ret_val;
1915 }
1916
1917 if (hw->phy.type != igc_phy_m88)
1918 return IGC_SUCCESS;
1919
1920 if (hw->phy.id == I347AT4_E_PHY_ID ||
1921 hw->phy.id == M88E1340M_E_PHY_ID ||
1922 hw->phy.id == M88E1112_E_PHY_ID)
1923 return IGC_SUCCESS;
1924 if (hw->phy.id == I210_I_PHY_ID)
1925 return IGC_SUCCESS;
1926 if (hw->phy.id == I225_I_PHY_ID)
1927 return IGC_SUCCESS;
1928 if (hw->phy.id == M88E1543_E_PHY_ID || hw->phy.id == M88E1512_E_PHY_ID)
1929 return IGC_SUCCESS;
1930 ret_val = phy->ops.read_reg(hw, M88IGC_EXT_PHY_SPEC_CTRL, &phy_data);
1931 if (ret_val)
1932 return ret_val;
1933
1934
1935
1936
1937
1938 phy_data |= M88IGC_EPSCR_TX_CLK_25;
1939 ret_val = phy->ops.write_reg(hw, M88IGC_EXT_PHY_SPEC_CTRL, phy_data);
1940 if (ret_val)
1941 return ret_val;
1942
1943
1944
1945
1946 ret_val = phy->ops.read_reg(hw, M88IGC_PHY_SPEC_CTRL, &phy_data);
1947 if (ret_val)
1948 return ret_val;
1949
1950 phy_data |= M88IGC_PSCR_ASSERT_CRS_ON_TX;
1951 ret_val = phy->ops.write_reg(hw, M88IGC_PHY_SPEC_CTRL, phy_data);
1952
1953 return ret_val;
1954}
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964s32 igc_phy_force_speed_duplex_ife(struct igc_hw *hw)
1965{
1966 struct igc_phy_info *phy = &hw->phy;
1967 s32 ret_val;
1968 u16 data;
1969 bool link;
1970
1971 DEBUGFUNC("igc_phy_force_speed_duplex_ife");
1972
1973 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1974 if (ret_val)
1975 return ret_val;
1976
1977 igc_phy_force_speed_duplex_setup(hw, &data);
1978
1979 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1980 if (ret_val)
1981 return ret_val;
1982
1983
1984 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1985 if (ret_val)
1986 return ret_val;
1987
1988 data &= ~IFE_PMC_AUTO_MDIX;
1989 data &= ~IFE_PMC_FORCE_MDIX;
1990
1991 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1992 if (ret_val)
1993 return ret_val;
1994
1995 DEBUGOUT1("IFE PMC: %X\n", data);
1996
1997 usec_delay(1);
1998
1999 if (phy->autoneg_wait_to_complete) {
2000 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
2001
2002 ret_val = igc_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
2003 100000, &link);
2004 if (ret_val)
2005 return ret_val;
2006
2007 if (!link)
2008 DEBUGOUT("Link taking longer than expected.\n");
2009
2010
2011 ret_val = igc_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
2012 100000, &link);
2013 if (ret_val)
2014 return ret_val;
2015 }
2016
2017 return IGC_SUCCESS;
2018}
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032void igc_phy_force_speed_duplex_setup(struct igc_hw *hw, u16 *phy_ctrl)
2033{
2034 struct igc_mac_info *mac = &hw->mac;
2035 u32 ctrl;
2036
2037 DEBUGFUNC("igc_phy_force_speed_duplex_setup");
2038
2039
2040 hw->fc.current_mode = igc_fc_none;
2041
2042
2043 ctrl = IGC_READ_REG(hw, IGC_CTRL);
2044 ctrl |= (IGC_CTRL_FRCSPD | IGC_CTRL_FRCDPX);
2045 ctrl &= ~IGC_CTRL_SPD_SEL;
2046
2047
2048 ctrl &= ~IGC_CTRL_ASDE;
2049
2050
2051 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
2052
2053
2054 if (mac->forced_speed_duplex & IGC_ALL_HALF_DUPLEX) {
2055 ctrl &= ~IGC_CTRL_FD;
2056 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
2057 DEBUGOUT("Half Duplex\n");
2058 } else {
2059 ctrl |= IGC_CTRL_FD;
2060 *phy_ctrl |= MII_CR_FULL_DUPLEX;
2061 DEBUGOUT("Full Duplex\n");
2062 }
2063
2064
2065 if (mac->forced_speed_duplex & IGC_ALL_100_SPEED) {
2066 ctrl |= IGC_CTRL_SPD_100;
2067 *phy_ctrl |= MII_CR_SPEED_100;
2068 *phy_ctrl &= ~MII_CR_SPEED_1000;
2069 DEBUGOUT("Forcing 100mb\n");
2070 } else {
2071 ctrl &= ~(IGC_CTRL_SPD_1000 | IGC_CTRL_SPD_100);
2072 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2073 DEBUGOUT("Forcing 10mb\n");
2074 }
2075
2076 hw->mac.ops.config_collision_dist(hw);
2077
2078 IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
2079}
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095s32 igc_set_d3_lplu_state_generic(struct igc_hw *hw, bool active)
2096{
2097 struct igc_phy_info *phy = &hw->phy;
2098 s32 ret_val;
2099 u16 data;
2100
2101 DEBUGFUNC("igc_set_d3_lplu_state_generic");
2102
2103 if (!hw->phy.ops.read_reg)
2104 return IGC_SUCCESS;
2105
2106 ret_val = phy->ops.read_reg(hw, IGP02IGC_PHY_POWER_MGMT, &data);
2107 if (ret_val)
2108 return ret_val;
2109
2110 if (!active) {
2111 data &= ~IGP02IGC_PM_D3_LPLU;
2112 ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT,
2113 data);
2114 if (ret_val)
2115 return ret_val;
2116
2117
2118
2119
2120
2121 if (phy->smart_speed == igc_smart_speed_on) {
2122 ret_val = phy->ops.read_reg(hw,
2123 IGP01IGC_PHY_PORT_CONFIG,
2124 &data);
2125 if (ret_val)
2126 return ret_val;
2127
2128 data |= IGP01IGC_PSCFR_SMART_SPEED;
2129 ret_val = phy->ops.write_reg(hw,
2130 IGP01IGC_PHY_PORT_CONFIG,
2131 data);
2132 if (ret_val)
2133 return ret_val;
2134 } else if (phy->smart_speed == igc_smart_speed_off) {
2135 ret_val = phy->ops.read_reg(hw,
2136 IGP01IGC_PHY_PORT_CONFIG,
2137 &data);
2138 if (ret_val)
2139 return ret_val;
2140
2141 data &= ~IGP01IGC_PSCFR_SMART_SPEED;
2142 ret_val = phy->ops.write_reg(hw,
2143 IGP01IGC_PHY_PORT_CONFIG,
2144 data);
2145 if (ret_val)
2146 return ret_val;
2147 }
2148 } else if ((phy->autoneg_advertised == IGC_ALL_SPEED_DUPLEX) ||
2149 (phy->autoneg_advertised == IGC_ALL_NOT_GIG) ||
2150 (phy->autoneg_advertised == IGC_ALL_10_SPEED)) {
2151 data |= IGP02IGC_PM_D3_LPLU;
2152 ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT,
2153 data);
2154 if (ret_val)
2155 return ret_val;
2156
2157
2158 ret_val = phy->ops.read_reg(hw, IGP01IGC_PHY_PORT_CONFIG,
2159 &data);
2160 if (ret_val)
2161 return ret_val;
2162
2163 data &= ~IGP01IGC_PSCFR_SMART_SPEED;
2164 ret_val = phy->ops.write_reg(hw, IGP01IGC_PHY_PORT_CONFIG,
2165 data);
2166 }
2167
2168 return ret_val;
2169}
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179s32 igc_check_downshift_generic(struct igc_hw *hw)
2180{
2181 struct igc_phy_info *phy = &hw->phy;
2182 s32 ret_val;
2183 u16 phy_data, offset, mask;
2184
2185 DEBUGFUNC("igc_check_downshift_generic");
2186
2187 switch (phy->type) {
2188 case igc_phy_i210:
2189 case igc_phy_m88:
2190 case igc_phy_gg82563:
2191 case igc_phy_bm:
2192 case igc_phy_82578:
2193 offset = M88IGC_PHY_SPEC_STATUS;
2194 mask = M88IGC_PSSR_DOWNSHIFT;
2195 break;
2196 case igc_phy_igp:
2197 case igc_phy_igp_2:
2198 case igc_phy_igp_3:
2199 offset = IGP01IGC_PHY_LINK_HEALTH;
2200 mask = IGP01IGC_PLHR_SS_DOWNGRADE;
2201 break;
2202 default:
2203
2204 phy->speed_downgraded = false;
2205 return IGC_SUCCESS;
2206 }
2207
2208 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2209
2210 if (!ret_val)
2211 phy->speed_downgraded = !!(phy_data & mask);
2212
2213 return ret_val;
2214}
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224s32 igc_check_polarity_m88(struct igc_hw *hw)
2225{
2226 struct igc_phy_info *phy = &hw->phy;
2227 s32 ret_val;
2228 u16 data;
2229
2230 DEBUGFUNC("igc_check_polarity_m88");
2231
2232 ret_val = phy->ops.read_reg(hw, M88IGC_PHY_SPEC_STATUS, &data);
2233
2234 if (!ret_val)
2235 phy->cable_polarity = ((data & M88IGC_PSSR_REV_POLARITY)
2236 ? igc_rev_polarity_reversed
2237 : igc_rev_polarity_normal);
2238
2239 return ret_val;
2240}
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251s32 igc_check_polarity_igp(struct igc_hw *hw)
2252{
2253 struct igc_phy_info *phy = &hw->phy;
2254 s32 ret_val;
2255 u16 data, offset, mask;
2256
2257 DEBUGFUNC("igc_check_polarity_igp");
2258
2259
2260
2261
2262 ret_val = phy->ops.read_reg(hw, IGP01IGC_PHY_PORT_STATUS, &data);
2263 if (ret_val)
2264 return ret_val;
2265
2266 if ((data & IGP01IGC_PSSR_SPEED_MASK) ==
2267 IGP01IGC_PSSR_SPEED_1000MBPS) {
2268 offset = IGP01IGC_PHY_PCS_INIT_REG;
2269 mask = IGP01IGC_PHY_POLARITY_MASK;
2270 } else {
2271
2272
2273
2274 offset = IGP01IGC_PHY_PORT_STATUS;
2275 mask = IGP01IGC_PSSR_POLARITY_REVERSED;
2276 }
2277
2278 ret_val = phy->ops.read_reg(hw, offset, &data);
2279
2280 if (!ret_val)
2281 phy->cable_polarity = ((data & mask)
2282 ? igc_rev_polarity_reversed
2283 : igc_rev_polarity_normal);
2284
2285 return ret_val;
2286}
2287
2288
2289
2290
2291
2292
2293
2294s32 igc_check_polarity_ife(struct igc_hw *hw)
2295{
2296 struct igc_phy_info *phy = &hw->phy;
2297 s32 ret_val;
2298 u16 phy_data, offset, mask;
2299
2300 DEBUGFUNC("igc_check_polarity_ife");
2301
2302
2303
2304 if (phy->polarity_correction) {
2305 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
2306 mask = IFE_PESC_POLARITY_REVERSED;
2307 } else {
2308 offset = IFE_PHY_SPECIAL_CONTROL;
2309 mask = IFE_PSC_FORCE_POLARITY;
2310 }
2311
2312 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2313
2314 if (!ret_val)
2315 phy->cable_polarity = ((phy_data & mask)
2316 ? igc_rev_polarity_reversed
2317 : igc_rev_polarity_normal);
2318
2319 return ret_val;
2320}
2321
2322
2323
2324
2325
2326
2327
2328
2329static s32 igc_wait_autoneg(struct igc_hw *hw)
2330{
2331 s32 ret_val = IGC_SUCCESS;
2332 u16 i, phy_status;
2333
2334 DEBUGFUNC("igc_wait_autoneg");
2335
2336 if (!hw->phy.ops.read_reg)
2337 return IGC_SUCCESS;
2338
2339
2340 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2341 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2342 if (ret_val)
2343 break;
2344 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2345 if (ret_val)
2346 break;
2347 if (phy_status & MII_SR_AUTONEG_COMPLETE)
2348 break;
2349 msec_delay(100);
2350 }
2351
2352
2353
2354
2355 return ret_val;
2356}
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367s32 igc_phy_has_link_generic(struct igc_hw *hw, u32 iterations,
2368 u32 usec_interval, bool *success)
2369{
2370 s32 ret_val = IGC_SUCCESS;
2371 u16 i, phy_status;
2372
2373 DEBUGFUNC("igc_phy_has_link_generic");
2374
2375 if (!hw->phy.ops.read_reg)
2376 return IGC_SUCCESS;
2377
2378 for (i = 0; i < iterations; i++) {
2379
2380
2381
2382
2383 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2384 if (ret_val) {
2385
2386
2387
2388
2389 if (usec_interval >= 1000)
2390 msec_delay(usec_interval / 1000);
2391 else
2392 usec_delay(usec_interval);
2393 }
2394 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2395 if (ret_val)
2396 break;
2397 if (phy_status & MII_SR_LINK_STATUS)
2398 break;
2399 if (usec_interval >= 1000)
2400 msec_delay(usec_interval / 1000);
2401 else
2402 usec_delay(usec_interval);
2403 }
2404
2405 *success = (i < iterations);
2406
2407 return ret_val;
2408}
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425s32 igc_get_cable_length_m88(struct igc_hw *hw)
2426{
2427 struct igc_phy_info *phy = &hw->phy;
2428 s32 ret_val;
2429 u16 phy_data, index;
2430
2431 DEBUGFUNC("igc_get_cable_length_m88");
2432
2433 ret_val = phy->ops.read_reg(hw, M88IGC_PHY_SPEC_STATUS, &phy_data);
2434 if (ret_val)
2435 return ret_val;
2436
2437 index = ((phy_data & M88IGC_PSSR_CABLE_LENGTH) >>
2438 M88IGC_PSSR_CABLE_LENGTH_SHIFT);
2439
2440 if (index >= M88IGC_CABLE_LENGTH_TABLE_SIZE - 1)
2441 return -IGC_ERR_PHY;
2442
2443 phy->min_cable_length = igc_m88_cable_length_table[index];
2444 phy->max_cable_length = igc_m88_cable_length_table[index + 1];
2445
2446 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2447
2448 return IGC_SUCCESS;
2449}
2450
2451s32 igc_get_cable_length_m88_gen2(struct igc_hw *hw)
2452{
2453 struct igc_phy_info *phy = &hw->phy;
2454 s32 ret_val = 0;
2455 u16 phy_data, phy_data2, is_cm;
2456 u16 index, default_page;
2457
2458 DEBUGFUNC("igc_get_cable_length_m88_gen2");
2459
2460 switch (hw->phy.id) {
2461 case I210_I_PHY_ID:
2462
2463 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2464 (I347AT4_PCDL + phy->addr),
2465 &phy_data);
2466 if (ret_val)
2467 return ret_val;
2468
2469
2470 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2471 I347AT4_PCDC, &phy_data2);
2472 if (ret_val)
2473 return ret_val;
2474
2475 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2476
2477
2478 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2479 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2480 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2481 break;
2482 case I225_I_PHY_ID:
2483 if (ret_val)
2484 return ret_val;
2485
2486 break;
2487 case M88E1543_E_PHY_ID:
2488 case M88E1512_E_PHY_ID:
2489 case M88E1340M_E_PHY_ID:
2490 case I347AT4_E_PHY_ID:
2491
2492 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2493 &default_page);
2494 if (ret_val)
2495 return ret_val;
2496
2497 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2498 if (ret_val)
2499 return ret_val;
2500
2501
2502 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2503 &phy_data);
2504 if (ret_val)
2505 return ret_val;
2506
2507
2508 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2509 if (ret_val)
2510 return ret_val;
2511
2512 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2513
2514
2515 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2516 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2517 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2518
2519
2520 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2521 default_page);
2522 if (ret_val)
2523 return ret_val;
2524 break;
2525
2526 case M88E1112_E_PHY_ID:
2527
2528 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2529 &default_page);
2530 if (ret_val)
2531 return ret_val;
2532
2533 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2534 if (ret_val)
2535 return ret_val;
2536
2537 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2538 &phy_data);
2539 if (ret_val)
2540 return ret_val;
2541
2542 index = (phy_data & M88IGC_PSSR_CABLE_LENGTH) >>
2543 M88IGC_PSSR_CABLE_LENGTH_SHIFT;
2544
2545 if (index >= M88IGC_CABLE_LENGTH_TABLE_SIZE - 1)
2546 return -IGC_ERR_PHY;
2547
2548 phy->min_cable_length = igc_m88_cable_length_table[index];
2549 phy->max_cable_length = igc_m88_cable_length_table[index + 1];
2550
2551 phy->cable_length = (phy->min_cable_length +
2552 phy->max_cable_length) / 2;
2553
2554
2555 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2556 default_page);
2557 if (ret_val)
2558 return ret_val;
2559
2560 break;
2561 default:
2562 return -IGC_ERR_PHY;
2563 }
2564
2565 return ret_val;
2566}
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579s32 igc_get_cable_length_igp_2(struct igc_hw *hw)
2580{
2581 struct igc_phy_info *phy = &hw->phy;
2582 s32 ret_val;
2583 u16 phy_data, i, agc_value = 0;
2584 u16 cur_agc_index, max_agc_index = 0;
2585 u16 min_agc_index = IGP02IGC_CABLE_LENGTH_TABLE_SIZE - 1;
2586 static const u16 agc_reg_array[IGP02IGC_PHY_CHANNEL_NUM] = {
2587 IGP02IGC_PHY_AGC_A,
2588 IGP02IGC_PHY_AGC_B,
2589 IGP02IGC_PHY_AGC_C,
2590 IGP02IGC_PHY_AGC_D
2591 };
2592
2593 DEBUGFUNC("igc_get_cable_length_igp_2");
2594
2595
2596 for (i = 0; i < IGP02IGC_PHY_CHANNEL_NUM; i++) {
2597 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2598 if (ret_val)
2599 return ret_val;
2600
2601
2602
2603
2604
2605
2606 cur_agc_index = ((phy_data >> IGP02IGC_AGC_LENGTH_SHIFT) &
2607 IGP02IGC_AGC_LENGTH_MASK);
2608
2609
2610 if (cur_agc_index >= IGP02IGC_CABLE_LENGTH_TABLE_SIZE ||
2611 cur_agc_index == 0)
2612 return -IGC_ERR_PHY;
2613
2614
2615 if (igc_igp_2_cable_length_table[min_agc_index] >
2616 igc_igp_2_cable_length_table[cur_agc_index])
2617 min_agc_index = cur_agc_index;
2618 if (igc_igp_2_cable_length_table[max_agc_index] <
2619 igc_igp_2_cable_length_table[cur_agc_index])
2620 max_agc_index = cur_agc_index;
2621
2622 agc_value += igc_igp_2_cable_length_table[cur_agc_index];
2623 }
2624
2625 agc_value -= (igc_igp_2_cable_length_table[min_agc_index] +
2626 igc_igp_2_cable_length_table[max_agc_index]);
2627 agc_value /= (IGP02IGC_PHY_CHANNEL_NUM - 2);
2628
2629
2630 phy->min_cable_length = (((agc_value - IGP02IGC_AGC_RANGE) > 0) ?
2631 (agc_value - IGP02IGC_AGC_RANGE) : 0);
2632 phy->max_cable_length = agc_value + IGP02IGC_AGC_RANGE;
2633
2634 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2635
2636 return IGC_SUCCESS;
2637}
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649s32 igc_get_phy_info_m88(struct igc_hw *hw)
2650{
2651 struct igc_phy_info *phy = &hw->phy;
2652 s32 ret_val;
2653 u16 phy_data;
2654 bool link;
2655
2656 DEBUGFUNC("igc_get_phy_info_m88");
2657
2658 if (phy->media_type != igc_media_type_copper) {
2659 DEBUGOUT("Phy info is only valid for copper media\n");
2660 return -IGC_ERR_CONFIG;
2661 }
2662
2663 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link);
2664 if (ret_val)
2665 return ret_val;
2666
2667 if (!link) {
2668 DEBUGOUT("Phy info is only valid if link is up\n");
2669 return -IGC_ERR_CONFIG;
2670 }
2671
2672 ret_val = phy->ops.read_reg(hw, M88IGC_PHY_SPEC_CTRL, &phy_data);
2673 if (ret_val)
2674 return ret_val;
2675
2676 phy->polarity_correction = !!(phy_data &
2677 M88IGC_PSCR_POLARITY_REVERSAL);
2678
2679 ret_val = igc_check_polarity_m88(hw);
2680 if (ret_val)
2681 return ret_val;
2682
2683 ret_val = phy->ops.read_reg(hw, M88IGC_PHY_SPEC_STATUS, &phy_data);
2684 if (ret_val)
2685 return ret_val;
2686
2687 phy->is_mdix = !!(phy_data & M88IGC_PSSR_MDIX);
2688
2689 if ((phy_data & M88IGC_PSSR_SPEED) == M88IGC_PSSR_1000MBS) {
2690 ret_val = hw->phy.ops.get_cable_length(hw);
2691 if (ret_val)
2692 return ret_val;
2693
2694 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2695 if (ret_val)
2696 return ret_val;
2697
2698 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2699 ? igc_1000t_rx_status_ok
2700 : igc_1000t_rx_status_not_ok;
2701
2702 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2703 ? igc_1000t_rx_status_ok
2704 : igc_1000t_rx_status_not_ok;
2705 } else {
2706
2707 phy->cable_length = IGC_CABLE_LENGTH_UNDEFINED;
2708 phy->local_rx = igc_1000t_rx_status_undefined;
2709 phy->remote_rx = igc_1000t_rx_status_undefined;
2710 }
2711
2712 return ret_val;
2713}
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724s32 igc_get_phy_info_igp(struct igc_hw *hw)
2725{
2726 struct igc_phy_info *phy = &hw->phy;
2727 s32 ret_val;
2728 u16 data;
2729 bool link;
2730
2731 DEBUGFUNC("igc_get_phy_info_igp");
2732
2733 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link);
2734 if (ret_val)
2735 return ret_val;
2736
2737 if (!link) {
2738 DEBUGOUT("Phy info is only valid if link is up\n");
2739 return -IGC_ERR_CONFIG;
2740 }
2741
2742 phy->polarity_correction = true;
2743
2744 ret_val = igc_check_polarity_igp(hw);
2745 if (ret_val)
2746 return ret_val;
2747
2748 ret_val = phy->ops.read_reg(hw, IGP01IGC_PHY_PORT_STATUS, &data);
2749 if (ret_val)
2750 return ret_val;
2751
2752 phy->is_mdix = !!(data & IGP01IGC_PSSR_MDIX);
2753
2754 if ((data & IGP01IGC_PSSR_SPEED_MASK) ==
2755 IGP01IGC_PSSR_SPEED_1000MBPS) {
2756 ret_val = phy->ops.get_cable_length(hw);
2757 if (ret_val)
2758 return ret_val;
2759
2760 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2761 if (ret_val)
2762 return ret_val;
2763
2764 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2765 ? igc_1000t_rx_status_ok
2766 : igc_1000t_rx_status_not_ok;
2767
2768 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2769 ? igc_1000t_rx_status_ok
2770 : igc_1000t_rx_status_not_ok;
2771 } else {
2772 phy->cable_length = IGC_CABLE_LENGTH_UNDEFINED;
2773 phy->local_rx = igc_1000t_rx_status_undefined;
2774 phy->remote_rx = igc_1000t_rx_status_undefined;
2775 }
2776
2777 return ret_val;
2778}
2779
2780
2781
2782
2783
2784
2785
2786s32 igc_get_phy_info_ife(struct igc_hw *hw)
2787{
2788 struct igc_phy_info *phy = &hw->phy;
2789 s32 ret_val;
2790 u16 data;
2791 bool link;
2792
2793 DEBUGFUNC("igc_get_phy_info_ife");
2794
2795 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link);
2796 if (ret_val)
2797 return ret_val;
2798
2799 if (!link) {
2800 DEBUGOUT("Phy info is only valid if link is up\n");
2801 return -IGC_ERR_CONFIG;
2802 }
2803
2804 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2805 if (ret_val)
2806 return ret_val;
2807 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2808
2809 if (phy->polarity_correction) {
2810 ret_val = igc_check_polarity_ife(hw);
2811 if (ret_val)
2812 return ret_val;
2813 } else {
2814
2815 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2816 ? igc_rev_polarity_reversed
2817 : igc_rev_polarity_normal);
2818 }
2819
2820 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2821 if (ret_val)
2822 return ret_val;
2823
2824 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2825
2826
2827 phy->cable_length = IGC_CABLE_LENGTH_UNDEFINED;
2828 phy->local_rx = igc_1000t_rx_status_undefined;
2829 phy->remote_rx = igc_1000t_rx_status_undefined;
2830
2831 return IGC_SUCCESS;
2832}
2833
2834
2835
2836
2837
2838
2839
2840
2841s32 igc_phy_sw_reset_generic(struct igc_hw *hw)
2842{
2843 s32 ret_val;
2844 u16 phy_ctrl;
2845
2846 DEBUGFUNC("igc_phy_sw_reset_generic");
2847
2848 if (!hw->phy.ops.read_reg)
2849 return IGC_SUCCESS;
2850
2851 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2852 if (ret_val)
2853 return ret_val;
2854
2855 phy_ctrl |= MII_CR_RESET;
2856 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2857 if (ret_val)
2858 return ret_val;
2859
2860 usec_delay(1);
2861
2862 return ret_val;
2863}
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874s32 igc_phy_hw_reset_generic(struct igc_hw *hw)
2875{
2876 struct igc_phy_info *phy = &hw->phy;
2877 s32 ret_val;
2878 u32 ctrl;
2879
2880 DEBUGFUNC("igc_phy_hw_reset_generic");
2881
2882 if (phy->ops.check_reset_block) {
2883 ret_val = phy->ops.check_reset_block(hw);
2884 if (ret_val)
2885 return IGC_SUCCESS;
2886 }
2887
2888 ret_val = phy->ops.acquire(hw);
2889 if (ret_val)
2890 return ret_val;
2891
2892 ctrl = IGC_READ_REG(hw, IGC_CTRL);
2893 IGC_WRITE_REG(hw, IGC_CTRL, ctrl | IGC_CTRL_PHY_RST);
2894 IGC_WRITE_FLUSH(hw);
2895
2896 usec_delay(phy->reset_delay_us);
2897
2898 IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
2899 IGC_WRITE_FLUSH(hw);
2900
2901 usec_delay(150);
2902
2903 phy->ops.release(hw);
2904
2905 return ret_val;
2906}
2907
2908
2909
2910
2911
2912
2913
2914
2915s32 igc_get_cfg_done_generic(struct igc_hw IGC_UNUSEDARG * hw)
2916{
2917 DEBUGFUNC("igc_get_cfg_done_generic");
2918 UNREFERENCED_1PARAMETER(hw);
2919
2920 msec_delay_irq(10);
2921
2922 return IGC_SUCCESS;
2923}
2924
2925
2926
2927
2928
2929
2930
2931s32 igc_phy_init_script_igp3(struct igc_hw *hw)
2932{
2933 DEBUGOUT("Running IGP 3 PHY init script\n");
2934
2935
2936
2937 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2938
2939 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2940
2941 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2942
2943 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2944
2945 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2946
2947 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2948
2949 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2950
2951 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2952
2953 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2954
2955 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2956
2957 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2958
2959 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2960
2961 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2962
2963 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2964
2965 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2966
2967 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2968
2969 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2970
2971 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2972
2973 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2974
2975 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2976
2977 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2978
2979 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2980
2981 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2982
2983 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2984
2985 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2986
2987 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2988
2989
2990
2991 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2992
2993 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2994
2995
2996
2997 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2998
2999 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
3000
3001 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
3002
3003 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
3004
3005 return IGC_SUCCESS;
3006}
3007
3008
3009
3010
3011
3012
3013
3014enum igc_phy_type igc_get_phy_type_from_id(u32 phy_id)
3015{
3016 enum igc_phy_type phy_type = igc_phy_unknown;
3017
3018 switch (phy_id) {
3019 case M88IGC_I_PHY_ID:
3020 case M88IGC_E_PHY_ID:
3021 case M88E1111_I_PHY_ID:
3022 case M88E1011_I_PHY_ID:
3023 case M88E1543_E_PHY_ID:
3024 case M88E1512_E_PHY_ID:
3025 case I347AT4_E_PHY_ID:
3026 case M88E1112_E_PHY_ID:
3027 case M88E1340M_E_PHY_ID:
3028 phy_type = igc_phy_m88;
3029 break;
3030 case IGP01IGC_I_PHY_ID:
3031 phy_type = igc_phy_igp_2;
3032 break;
3033 case GG82563_E_PHY_ID:
3034 phy_type = igc_phy_gg82563;
3035 break;
3036 case IGP03IGC_E_PHY_ID:
3037 phy_type = igc_phy_igp_3;
3038 break;
3039 case IFE_E_PHY_ID:
3040 case IFE_PLUS_E_PHY_ID:
3041 case IFE_C_E_PHY_ID:
3042 phy_type = igc_phy_ife;
3043 break;
3044 case BMIGC_E_PHY_ID:
3045 case BMIGC_E_PHY_ID_R2:
3046 phy_type = igc_phy_bm;
3047 break;
3048 case I82578_E_PHY_ID:
3049 phy_type = igc_phy_82578;
3050 break;
3051 case I82577_E_PHY_ID:
3052 phy_type = igc_phy_82577;
3053 break;
3054 case I82579_E_PHY_ID:
3055 phy_type = igc_phy_82579;
3056 break;
3057 case I217_E_PHY_ID:
3058 phy_type = igc_phy_i217;
3059 break;
3060 case I82580_I_PHY_ID:
3061 phy_type = igc_phy_82580;
3062 break;
3063 case I210_I_PHY_ID:
3064 phy_type = igc_phy_i210;
3065 break;
3066 case I225_I_PHY_ID:
3067 phy_type = igc_phy_i225;
3068 break;
3069 default:
3070 phy_type = igc_phy_unknown;
3071 break;
3072 }
3073 return phy_type;
3074}
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084s32 igc_determine_phy_address(struct igc_hw *hw)
3085{
3086 u32 phy_addr = 0;
3087 u32 i;
3088 enum igc_phy_type phy_type = igc_phy_unknown;
3089
3090 hw->phy.id = phy_type;
3091
3092 for (phy_addr = 0; phy_addr < IGC_MAX_PHY_ADDR; phy_addr++) {
3093 hw->phy.addr = phy_addr;
3094 i = 0;
3095
3096 do {
3097 igc_get_phy_id(hw);
3098 phy_type = igc_get_phy_type_from_id(hw->phy.id);
3099
3100
3101
3102
3103 if (phy_type != igc_phy_unknown)
3104 return IGC_SUCCESS;
3105
3106 msec_delay(1);
3107 i++;
3108 } while (i < 10);
3109 }
3110
3111 return -IGC_ERR_PHY_TYPE;
3112}
3113
3114
3115
3116
3117
3118
3119
3120
3121static u32 igc_get_phy_addr_for_bm_page(u32 page, u32 reg)
3122{
3123 u32 phy_addr = 2;
3124
3125 if (page >= 768 || (page == 0 && reg == 25) || reg == 31)
3126 phy_addr = 1;
3127
3128 return phy_addr;
3129}
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140s32 igc_write_phy_reg_bm(struct igc_hw *hw, u32 offset, u16 data)
3141{
3142 s32 ret_val;
3143 u32 page = offset >> IGP_PAGE_SHIFT;
3144
3145 DEBUGFUNC("igc_write_phy_reg_bm");
3146
3147 ret_val = hw->phy.ops.acquire(hw);
3148 if (ret_val)
3149 return ret_val;
3150
3151
3152 if (page == BM_WUC_PAGE) {
3153 ret_val = igc_access_phy_wakeup_reg_bm(hw, offset, &data,
3154 false, false);
3155 goto release;
3156 }
3157
3158 hw->phy.addr = igc_get_phy_addr_for_bm_page(page, offset);
3159
3160 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3161 u32 page_shift, page_select;
3162
3163
3164
3165
3166
3167 if (hw->phy.addr == 1) {
3168 page_shift = IGP_PAGE_SHIFT;
3169 page_select = IGP01IGC_PHY_PAGE_SELECT;
3170 } else {
3171 page_shift = 0;
3172 page_select = BM_PHY_PAGE_SELECT;
3173 }
3174
3175
3176 ret_val = igc_write_phy_reg_mdic(hw, page_select,
3177 (page << page_shift));
3178 if (ret_val)
3179 goto release;
3180 }
3181
3182 ret_val = igc_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3183 data);
3184
3185release:
3186 hw->phy.ops.release(hw);
3187 return ret_val;
3188}
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200s32 igc_read_phy_reg_bm(struct igc_hw *hw, u32 offset, u16 *data)
3201{
3202 s32 ret_val;
3203 u32 page = offset >> IGP_PAGE_SHIFT;
3204
3205 DEBUGFUNC("igc_read_phy_reg_bm");
3206
3207 ret_val = hw->phy.ops.acquire(hw);
3208 if (ret_val)
3209 return ret_val;
3210
3211
3212 if (page == BM_WUC_PAGE) {
3213 ret_val = igc_access_phy_wakeup_reg_bm(hw, offset, data,
3214 true, false);
3215 goto release;
3216 }
3217
3218 hw->phy.addr = igc_get_phy_addr_for_bm_page(page, offset);
3219
3220 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3221 u32 page_shift, page_select;
3222
3223
3224
3225
3226
3227 if (hw->phy.addr == 1) {
3228 page_shift = IGP_PAGE_SHIFT;
3229 page_select = IGP01IGC_PHY_PAGE_SELECT;
3230 } else {
3231 page_shift = 0;
3232 page_select = BM_PHY_PAGE_SELECT;
3233 }
3234
3235
3236 ret_val = igc_write_phy_reg_mdic(hw, page_select,
3237 (page << page_shift));
3238 if (ret_val)
3239 goto release;
3240 }
3241
3242 ret_val = igc_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3243 data);
3244release:
3245 hw->phy.ops.release(hw);
3246 return ret_val;
3247}
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259s32 igc_read_phy_reg_bm2(struct igc_hw *hw, u32 offset, u16 *data)
3260{
3261 s32 ret_val;
3262 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3263
3264 DEBUGFUNC("igc_read_phy_reg_bm2");
3265
3266 ret_val = hw->phy.ops.acquire(hw);
3267 if (ret_val)
3268 return ret_val;
3269
3270
3271 if (page == BM_WUC_PAGE) {
3272 ret_val = igc_access_phy_wakeup_reg_bm(hw, offset, data,
3273 true, false);
3274 goto release;
3275 }
3276
3277 hw->phy.addr = 1;
3278
3279 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3280
3281 ret_val = igc_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3282 page);
3283
3284 if (ret_val)
3285 goto release;
3286 }
3287
3288 ret_val = igc_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3289 data);
3290release:
3291 hw->phy.ops.release(hw);
3292 return ret_val;
3293}
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304s32 igc_write_phy_reg_bm2(struct igc_hw *hw, u32 offset, u16 data)
3305{
3306 s32 ret_val;
3307 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3308
3309 DEBUGFUNC("igc_write_phy_reg_bm2");
3310
3311 ret_val = hw->phy.ops.acquire(hw);
3312 if (ret_val)
3313 return ret_val;
3314
3315
3316 if (page == BM_WUC_PAGE) {
3317 ret_val = igc_access_phy_wakeup_reg_bm(hw, offset, &data,
3318 false, false);
3319 goto release;
3320 }
3321
3322 hw->phy.addr = 1;
3323
3324 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3325
3326 ret_val = igc_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3327 page);
3328
3329 if (ret_val)
3330 goto release;
3331 }
3332
3333 ret_val = igc_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3334 data);
3335
3336release:
3337 hw->phy.ops.release(hw);
3338 return ret_val;
3339}
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349s32 igc_enable_phy_wakeup_reg_access_bm(struct igc_hw *hw, u16 *phy_reg)
3350{
3351 s32 ret_val;
3352 u16 temp;
3353
3354 DEBUGFUNC("igc_enable_phy_wakeup_reg_access_bm");
3355
3356 if (!phy_reg)
3357 return -IGC_ERR_PARAM;
3358
3359
3360 hw->phy.addr = 1;
3361
3362
3363 ret_val = igc_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3364 if (ret_val) {
3365 DEBUGOUT("Could not set Port Control page\n");
3366 return ret_val;
3367 }
3368
3369 ret_val = igc_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
3370 if (ret_val) {
3371 DEBUGOUT2("Could not read PHY register %d.%d\n",
3372 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3373 return ret_val;
3374 }
3375
3376
3377
3378
3379 temp = *phy_reg;
3380 temp |= BM_WUC_ENABLE_BIT;
3381 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
3382
3383 ret_val = igc_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
3384 if (ret_val) {
3385 DEBUGOUT2("Could not write PHY register %d.%d\n",
3386 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3387 return ret_val;
3388 }
3389
3390
3391
3392
3393 return igc_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
3394}
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407s32 igc_disable_phy_wakeup_reg_access_bm(struct igc_hw *hw, u16 *phy_reg)
3408{
3409 s32 ret_val;
3410
3411 DEBUGFUNC("igc_disable_phy_wakeup_reg_access_bm");
3412
3413 if (!phy_reg)
3414 return -IGC_ERR_PARAM;
3415
3416
3417 ret_val = igc_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3418 if (ret_val) {
3419 DEBUGOUT("Could not set Port Control page\n");
3420 return ret_val;
3421 }
3422
3423
3424 ret_val = igc_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
3425 if (ret_val)
3426 DEBUGOUT2("Could not restore PHY register %d.%d\n",
3427 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3428
3429 return ret_val;
3430}
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457static s32 igc_access_phy_wakeup_reg_bm(struct igc_hw *hw, u32 offset,
3458 u16 *data, bool read, bool page_set)
3459{
3460 s32 ret_val;
3461 u16 reg = BM_PHY_REG_NUM(offset);
3462 u16 page = BM_PHY_REG_PAGE(offset);
3463 u16 phy_reg = 0;
3464
3465 DEBUGFUNC("igc_access_phy_wakeup_reg_bm");
3466
3467
3468 if (hw->mac.type == igc_pchlan &&
3469 !(IGC_READ_REG(hw, IGC_PHY_CTRL) & IGC_PHY_CTRL_GBE_DISABLE))
3470 DEBUGOUT1("Attempting to access page %d while gig enabled.\n",
3471 page);
3472
3473 if (!page_set) {
3474
3475 ret_val = igc_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3476 if (ret_val) {
3477 DEBUGOUT("Could not enable PHY wakeup reg access\n");
3478 return ret_val;
3479 }
3480 }
3481
3482 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg);
3483
3484
3485 ret_val = igc_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
3486 if (ret_val) {
3487 DEBUGOUT1("Could not write address opcode to page %d\n", page);
3488 return ret_val;
3489 }
3490
3491 if (read) {
3492
3493 ret_val = igc_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3494 data);
3495 } else {
3496
3497 ret_val = igc_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3498 *data);
3499 }
3500
3501 if (ret_val) {
3502 DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg);
3503 return ret_val;
3504 }
3505
3506 if (!page_set)
3507 ret_val = igc_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3508
3509 return ret_val;
3510}
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520void igc_power_up_phy_copper(struct igc_hw *hw)
3521{
3522 u16 mii_reg = 0;
3523
3524
3525 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3526 mii_reg &= ~MII_CR_POWER_DOWN;
3527 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3528}
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538void igc_power_down_phy_copper(struct igc_hw *hw)
3539{
3540 u16 mii_reg = 0;
3541
3542
3543 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3544 mii_reg |= MII_CR_POWER_DOWN;
3545 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3546 msec_delay(1);
3547}
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561static s32 __igc_read_phy_reg_hv(struct igc_hw *hw, u32 offset, u16 *data,
3562 bool locked, bool page_set)
3563{
3564 s32 ret_val;
3565 u16 page = BM_PHY_REG_PAGE(offset);
3566 u16 reg = BM_PHY_REG_NUM(offset);
3567 u32 phy_addr = hw->phy.addr = igc_get_phy_addr_for_hv_page(page);
3568
3569 DEBUGFUNC("__igc_read_phy_reg_hv");
3570
3571 if (!locked) {
3572 ret_val = hw->phy.ops.acquire(hw);
3573 if (ret_val)
3574 return ret_val;
3575 }
3576
3577 if (page == BM_WUC_PAGE) {
3578 ret_val = igc_access_phy_wakeup_reg_bm(hw, offset, data,
3579 true, page_set);
3580 goto out;
3581 }
3582
3583 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3584 ret_val = igc_access_phy_debug_regs_hv(hw, offset,
3585 data, true);
3586 goto out;
3587 }
3588
3589 if (!page_set) {
3590 if (page == HV_INTC_FC_PAGE_START)
3591 page = 0;
3592
3593 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3594
3595 ret_val = igc_set_page_igp(hw,
3596 (page << IGP_PAGE_SHIFT));
3597
3598 hw->phy.addr = phy_addr;
3599
3600 if (ret_val)
3601 goto out;
3602 }
3603 }
3604
3605 DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3606 page << IGP_PAGE_SHIFT, reg);
3607
3608 ret_val = igc_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3609 data);
3610out:
3611 if (!locked)
3612 hw->phy.ops.release(hw);
3613
3614 return ret_val;
3615}
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627s32 igc_read_phy_reg_hv(struct igc_hw *hw, u32 offset, u16 *data)
3628{
3629 return __igc_read_phy_reg_hv(hw, offset, data, false, false);
3630}
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641s32 igc_read_phy_reg_hv_locked(struct igc_hw *hw, u32 offset, u16 *data)
3642{
3643 return __igc_read_phy_reg_hv(hw, offset, data, true, false);
3644}
3645
3646
3647
3648
3649
3650
3651
3652
3653
3654
3655s32 igc_read_phy_reg_page_hv(struct igc_hw *hw, u32 offset, u16 *data)
3656{
3657 return __igc_read_phy_reg_hv(hw, offset, data, true, true);
3658}
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671static s32 __igc_write_phy_reg_hv(struct igc_hw *hw, u32 offset, u16 data,
3672 bool locked, bool page_set)
3673{
3674 s32 ret_val;
3675 u16 page = BM_PHY_REG_PAGE(offset);
3676 u16 reg = BM_PHY_REG_NUM(offset);
3677 u32 phy_addr = hw->phy.addr = igc_get_phy_addr_for_hv_page(page);
3678
3679 DEBUGFUNC("__igc_write_phy_reg_hv");
3680
3681 if (!locked) {
3682 ret_val = hw->phy.ops.acquire(hw);
3683 if (ret_val)
3684 return ret_val;
3685 }
3686
3687 if (page == BM_WUC_PAGE) {
3688 ret_val = igc_access_phy_wakeup_reg_bm(hw, offset, &data,
3689 false, page_set);
3690 goto out;
3691 }
3692
3693 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3694 ret_val = igc_access_phy_debug_regs_hv(hw, offset,
3695 &data, false);
3696 goto out;
3697 }
3698
3699 if (!page_set) {
3700 if (page == HV_INTC_FC_PAGE_START)
3701 page = 0;
3702
3703
3704
3705
3706
3707 if (hw->phy.type == igc_phy_82578 &&
3708 hw->phy.revision >= 1 &&
3709 hw->phy.addr == 2 &&
3710 !(MAX_PHY_REG_ADDRESS & reg) &&
3711 (data & (1 << 11))) {
3712 u16 data2 = 0x7EFF;
3713 ret_val = igc_access_phy_debug_regs_hv(hw,
3714 (1 << 6) | 0x3,
3715 &data2, false);
3716 if (ret_val)
3717 goto out;
3718 }
3719
3720 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3721
3722 ret_val = igc_set_page_igp(hw,
3723 (page << IGP_PAGE_SHIFT));
3724
3725 hw->phy.addr = phy_addr;
3726
3727 if (ret_val)
3728 goto out;
3729 }
3730 }
3731
3732 DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3733 page << IGP_PAGE_SHIFT, reg);
3734
3735 ret_val = igc_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3736 data);
3737
3738out:
3739 if (!locked)
3740 hw->phy.ops.release(hw);
3741
3742 return ret_val;
3743}
3744
3745
3746
3747
3748
3749
3750
3751
3752
3753
3754s32 igc_write_phy_reg_hv(struct igc_hw *hw, u32 offset, u16 data)
3755{
3756 return __igc_write_phy_reg_hv(hw, offset, data, false, false);
3757}
3758
3759
3760
3761
3762
3763
3764
3765
3766
3767
3768s32 igc_write_phy_reg_hv_locked(struct igc_hw *hw, u32 offset, u16 data)
3769{
3770 return __igc_write_phy_reg_hv(hw, offset, data, true, false);
3771}
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781
3782s32 igc_write_phy_reg_page_hv(struct igc_hw *hw, u32 offset, u16 data)
3783{
3784 return __igc_write_phy_reg_hv(hw, offset, data, true, true);
3785}
3786
3787
3788
3789
3790
3791static u32 igc_get_phy_addr_for_hv_page(u32 page)
3792{
3793 u32 phy_addr = 2;
3794
3795 if (page >= HV_INTC_FC_PAGE_START)
3796 phy_addr = 1;
3797
3798 return phy_addr;
3799}
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811
3812
3813static s32 igc_access_phy_debug_regs_hv(struct igc_hw *hw, u32 offset,
3814 u16 *data, bool read)
3815{
3816 s32 ret_val;
3817 u32 addr_reg;
3818 u32 data_reg;
3819
3820 DEBUGFUNC("igc_access_phy_debug_regs_hv");
3821
3822
3823 addr_reg = ((hw->phy.type == igc_phy_82578) ?
3824 I82578_ADDR_REG : I82577_ADDR_REG);
3825 data_reg = addr_reg + 1;
3826
3827
3828 hw->phy.addr = 2;
3829
3830
3831 ret_val = igc_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3832 if (ret_val) {
3833 DEBUGOUT("Could not write the Address Offset port register\n");
3834 return ret_val;
3835 }
3836
3837
3838 if (read)
3839 ret_val = igc_read_phy_reg_mdic(hw, data_reg, data);
3840 else
3841 ret_val = igc_write_phy_reg_mdic(hw, data_reg, *data);
3842
3843 if (ret_val)
3844 DEBUGOUT("Could not access the Data port register\n");
3845
3846 return ret_val;
3847}
3848
3849
3850
3851
3852
3853
3854
3855
3856
3857
3858
3859
3860s32 igc_link_stall_workaround_hv(struct igc_hw *hw)
3861{
3862 s32 ret_val = IGC_SUCCESS;
3863 u16 data;
3864
3865 DEBUGFUNC("igc_link_stall_workaround_hv");
3866
3867 if (hw->phy.type != igc_phy_82578)
3868 return IGC_SUCCESS;
3869
3870
3871 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3872 if (data & PHY_CONTROL_LB)
3873 return IGC_SUCCESS;
3874
3875
3876 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3877 if (ret_val)
3878 return ret_val;
3879
3880 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3881 BM_CS_STATUS_SPEED_MASK);
3882
3883 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3884 BM_CS_STATUS_SPEED_1000))
3885 return IGC_SUCCESS;
3886
3887 msec_delay(200);
3888
3889
3890 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3891 (HV_MUX_DATA_CTRL_GEN_TO_MAC |
3892 HV_MUX_DATA_CTRL_FORCE_SPEED));
3893 if (ret_val)
3894 return ret_val;
3895
3896 return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3897 HV_MUX_DATA_CTRL_GEN_TO_MAC);
3898}
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908s32 igc_check_polarity_82577(struct igc_hw *hw)
3909{
3910 struct igc_phy_info *phy = &hw->phy;
3911 s32 ret_val;
3912 u16 data;
3913
3914 DEBUGFUNC("igc_check_polarity_82577");
3915
3916 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3917
3918 if (!ret_val)
3919 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3920 ? igc_rev_polarity_reversed
3921 : igc_rev_polarity_normal);
3922
3923 return ret_val;
3924}
3925
3926
3927
3928
3929
3930
3931
3932s32 igc_phy_force_speed_duplex_82577(struct igc_hw *hw)
3933{
3934 struct igc_phy_info *phy = &hw->phy;
3935 s32 ret_val;
3936 u16 phy_data;
3937 bool link = false;
3938
3939 DEBUGFUNC("igc_phy_force_speed_duplex_82577");
3940
3941 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3942 if (ret_val)
3943 return ret_val;
3944
3945 igc_phy_force_speed_duplex_setup(hw, &phy_data);
3946
3947 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3948 if (ret_val)
3949 return ret_val;
3950
3951 usec_delay(1);
3952
3953 if (phy->autoneg_wait_to_complete) {
3954 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3955
3956 ret_val = igc_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3957 100000, &link);
3958 if (ret_val)
3959 return ret_val;
3960
3961 if (!link)
3962 DEBUGOUT("Link taking longer than expected.\n");
3963
3964
3965 ret_val = igc_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3966 100000, &link);
3967 }
3968
3969 return ret_val;
3970}
3971
3972
3973
3974
3975
3976
3977
3978
3979
3980
3981s32 igc_get_phy_info_82577(struct igc_hw *hw)
3982{
3983 struct igc_phy_info *phy = &hw->phy;
3984 s32 ret_val;
3985 u16 data;
3986 bool link;
3987
3988 DEBUGFUNC("igc_get_phy_info_82577");
3989
3990 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link);
3991 if (ret_val)
3992 return ret_val;
3993
3994 if (!link) {
3995 DEBUGOUT("Phy info is only valid if link is up\n");
3996 return -IGC_ERR_CONFIG;
3997 }
3998
3999 phy->polarity_correction = true;
4000
4001 ret_val = igc_check_polarity_82577(hw);
4002 if (ret_val)
4003 return ret_val;
4004
4005 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
4006 if (ret_val)
4007 return ret_val;
4008
4009 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
4010
4011 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
4012 I82577_PHY_STATUS2_SPEED_1000MBPS) {
4013 ret_val = hw->phy.ops.get_cable_length(hw);
4014 if (ret_val)
4015 return ret_val;
4016
4017 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
4018 if (ret_val)
4019 return ret_val;
4020
4021 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
4022 ? igc_1000t_rx_status_ok
4023 : igc_1000t_rx_status_not_ok;
4024
4025 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
4026 ? igc_1000t_rx_status_ok
4027 : igc_1000t_rx_status_not_ok;
4028 } else {
4029 phy->cable_length = IGC_CABLE_LENGTH_UNDEFINED;
4030 phy->local_rx = igc_1000t_rx_status_undefined;
4031 phy->remote_rx = igc_1000t_rx_status_undefined;
4032 }
4033
4034 return IGC_SUCCESS;
4035}
4036
4037
4038
4039
4040
4041
4042
4043
4044s32 igc_get_cable_length_82577(struct igc_hw *hw)
4045{
4046 struct igc_phy_info *phy = &hw->phy;
4047 s32 ret_val;
4048 u16 phy_data, length;
4049
4050 DEBUGFUNC("igc_get_cable_length_82577");
4051
4052 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
4053 if (ret_val)
4054 return ret_val;
4055
4056 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
4057 I82577_DSTATUS_CABLE_LENGTH_SHIFT);
4058
4059 if (length == IGC_CABLE_LENGTH_UNDEFINED)
4060 return -IGC_ERR_PHY;
4061
4062 phy->cable_length = length;
4063
4064 return IGC_SUCCESS;
4065}
4066
4067
4068
4069
4070
4071
4072
4073
4074
4075
4076s32 igc_write_phy_reg_gs40g(struct igc_hw *hw, u32 offset, u16 data)
4077{
4078 s32 ret_val;
4079 u16 page = offset >> GS40G_PAGE_SHIFT;
4080
4081 DEBUGFUNC("igc_write_phy_reg_gs40g");
4082
4083 offset = offset & GS40G_OFFSET_MASK;
4084 ret_val = hw->phy.ops.acquire(hw);
4085 if (ret_val)
4086 return ret_val;
4087
4088 ret_val = igc_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4089 if (ret_val)
4090 goto release;
4091 ret_val = igc_write_phy_reg_mdic(hw, offset, data);
4092
4093release:
4094 hw->phy.ops.release(hw);
4095 return ret_val;
4096}
4097
4098
4099
4100
4101
4102
4103
4104
4105
4106
4107
4108s32 igc_read_phy_reg_gs40g(struct igc_hw *hw, u32 offset, u16 *data)
4109{
4110 s32 ret_val;
4111 u16 page = offset >> GS40G_PAGE_SHIFT;
4112
4113 DEBUGFUNC("igc_read_phy_reg_gs40g");
4114
4115 offset = offset & GS40G_OFFSET_MASK;
4116 ret_val = hw->phy.ops.acquire(hw);
4117 if (ret_val)
4118 return ret_val;
4119
4120 ret_val = igc_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4121 if (ret_val)
4122 goto release;
4123 ret_val = igc_read_phy_reg_mdic(hw, offset, data);
4124
4125release:
4126 hw->phy.ops.release(hw);
4127 return ret_val;
4128}
4129
4130
4131
4132
4133
4134
4135
4136
4137
4138
4139s32 igc_write_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 data)
4140{
4141 s32 ret_val;
4142 u8 dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT;
4143
4144 DEBUGFUNC("igc_write_phy_reg_gpy");
4145
4146 offset = offset & GPY_REG_MASK;
4147
4148 if (!dev_addr) {
4149 ret_val = hw->phy.ops.acquire(hw);
4150 if (ret_val)
4151 return ret_val;
4152 ret_val = igc_write_phy_reg_mdic(hw, offset, data);
4153 if (ret_val)
4154 return ret_val;
4155 hw->phy.ops.release(hw);
4156 } else {
4157 ret_val = igc_write_xmdio_reg(hw, (u16)offset, dev_addr,
4158 data);
4159 }
4160 return ret_val;
4161}
4162
4163
4164
4165
4166
4167
4168
4169
4170
4171
4172
4173s32 igc_read_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 *data)
4174{
4175 s32 ret_val;
4176 u8 dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT;
4177
4178 DEBUGFUNC("igc_read_phy_reg_gpy");
4179
4180 offset = offset & GPY_REG_MASK;
4181
4182 if (!dev_addr) {
4183 ret_val = hw->phy.ops.acquire(hw);
4184 if (ret_val)
4185 return ret_val;
4186 ret_val = igc_read_phy_reg_mdic(hw, offset, data);
4187 if (ret_val)
4188 return ret_val;
4189 hw->phy.ops.release(hw);
4190 } else {
4191 ret_val = igc_read_xmdio_reg(hw, (u16)offset, dev_addr,
4192 data);
4193 }
4194 return ret_val;
4195}
4196
4197
4198
4199
4200
4201
4202
4203
4204
4205
4206s32 igc_read_phy_reg_mphy(struct igc_hw *hw, u32 address, u32 *data)
4207{
4208 u32 mphy_ctrl = 0;
4209 bool locked = false;
4210 bool ready;
4211
4212 DEBUGFUNC("igc_read_phy_reg_mphy");
4213
4214
4215 ready = igc_is_mphy_ready(hw);
4216 if (!ready)
4217 return -IGC_ERR_PHY;
4218
4219
4220 mphy_ctrl = IGC_READ_REG(hw, IGC_MPHY_ADDR_CTRL);
4221 if (mphy_ctrl & IGC_MPHY_DIS_ACCESS) {
4222 locked = true;
4223 ready = igc_is_mphy_ready(hw);
4224 if (!ready)
4225 return -IGC_ERR_PHY;
4226 mphy_ctrl |= IGC_MPHY_ENA_ACCESS;
4227 IGC_WRITE_REG(hw, IGC_MPHY_ADDR_CTRL, mphy_ctrl);
4228 }
4229
4230
4231 ready = igc_is_mphy_ready(hw);
4232 if (!ready)
4233 return -IGC_ERR_PHY;
4234
4235
4236 mphy_ctrl = (mphy_ctrl & ~IGC_MPHY_ADDRESS_MASK &
4237 ~IGC_MPHY_ADDRESS_FNC_OVERRIDE) |
4238 (address & IGC_MPHY_ADDRESS_MASK);
4239 IGC_WRITE_REG(hw, IGC_MPHY_ADDR_CTRL, mphy_ctrl);
4240
4241
4242 ready = igc_is_mphy_ready(hw);
4243 if (!ready)
4244 return -IGC_ERR_PHY;
4245 *data = IGC_READ_REG(hw, IGC_MPHY_DATA);
4246
4247
4248 if (locked)
4249 ready = igc_is_mphy_ready(hw);
4250 if (!ready)
4251 return -IGC_ERR_PHY;
4252 IGC_WRITE_REG(hw, IGC_MPHY_ADDR_CTRL,
4253 IGC_MPHY_DIS_ACCESS);
4254
4255 return IGC_SUCCESS;
4256}
4257
4258
4259
4260
4261
4262
4263
4264
4265
4266
4267s32 igc_write_phy_reg_mphy(struct igc_hw *hw, u32 address, u32 data,
4268 bool line_override)
4269{
4270 u32 mphy_ctrl = 0;
4271 bool locked = false;
4272 bool ready;
4273
4274 DEBUGFUNC("igc_write_phy_reg_mphy");
4275
4276
4277 ready = igc_is_mphy_ready(hw);
4278 if (!ready)
4279 return -IGC_ERR_PHY;
4280
4281
4282 mphy_ctrl = IGC_READ_REG(hw, IGC_MPHY_ADDR_CTRL);
4283 if (mphy_ctrl & IGC_MPHY_DIS_ACCESS) {
4284 locked = true;
4285 ready = igc_is_mphy_ready(hw);
4286 if (!ready)
4287 return -IGC_ERR_PHY;
4288 mphy_ctrl |= IGC_MPHY_ENA_ACCESS;
4289 IGC_WRITE_REG(hw, IGC_MPHY_ADDR_CTRL, mphy_ctrl);
4290 }
4291
4292
4293 ready = igc_is_mphy_ready(hw);
4294 if (!ready)
4295 return -IGC_ERR_PHY;
4296
4297
4298 if (line_override)
4299 mphy_ctrl |= IGC_MPHY_ADDRESS_FNC_OVERRIDE;
4300 else
4301 mphy_ctrl &= ~IGC_MPHY_ADDRESS_FNC_OVERRIDE;
4302 mphy_ctrl = (mphy_ctrl & ~IGC_MPHY_ADDRESS_MASK) |
4303 (address & IGC_MPHY_ADDRESS_MASK);
4304 IGC_WRITE_REG(hw, IGC_MPHY_ADDR_CTRL, mphy_ctrl);
4305
4306
4307 ready = igc_is_mphy_ready(hw);
4308 if (!ready)
4309 return -IGC_ERR_PHY;
4310 IGC_WRITE_REG(hw, IGC_MPHY_DATA, data);
4311
4312
4313 if (locked)
4314 ready = igc_is_mphy_ready(hw);
4315 if (!ready)
4316 return -IGC_ERR_PHY;
4317 IGC_WRITE_REG(hw, IGC_MPHY_ADDR_CTRL,
4318 IGC_MPHY_DIS_ACCESS);
4319
4320 return IGC_SUCCESS;
4321}
4322
4323
4324
4325
4326
4327
4328
4329bool igc_is_mphy_ready(struct igc_hw *hw)
4330{
4331 u16 retry_count = 0;
4332 u32 mphy_ctrl = 0;
4333 bool ready = false;
4334
4335 while (retry_count < 2) {
4336 mphy_ctrl = IGC_READ_REG(hw, IGC_MPHY_ADDR_CTRL);
4337 if (mphy_ctrl & IGC_MPHY_BUSY) {
4338 usec_delay(20);
4339 retry_count++;
4340 continue;
4341 }
4342 ready = true;
4343 break;
4344 }
4345
4346 if (!ready)
4347 DEBUGOUT("ERROR READING mPHY control register, phy is busy.\n");
4348
4349 return ready;
4350}
4351
4352
4353
4354
4355
4356
4357
4358
4359
4360static s32 __igc_access_xmdio_reg(struct igc_hw *hw, u16 address,
4361 u8 dev_addr, u16 *data, bool read)
4362{
4363 s32 ret_val;
4364
4365 DEBUGFUNC("__igc_access_xmdio_reg");
4366
4367 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr);
4368 if (ret_val)
4369 return ret_val;
4370
4371 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address);
4372 if (ret_val)
4373 return ret_val;
4374
4375 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA |
4376 dev_addr);
4377 if (ret_val)
4378 return ret_val;
4379
4380 if (read)
4381 ret_val = hw->phy.ops.read_reg(hw, IGC_MMDAAD, data);
4382 else
4383 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data);
4384 if (ret_val)
4385 return ret_val;
4386
4387
4388 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0);
4389 if (ret_val)
4390 return ret_val;
4391
4392 return ret_val;
4393}
4394
4395
4396
4397
4398
4399
4400
4401
4402s32 igc_read_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr, u16 *data)
4403{
4404 DEBUGFUNC("igc_read_xmdio_reg");
4405
4406 return __igc_access_xmdio_reg(hw, addr, dev_addr, data, true);
4407}
4408
4409
4410
4411
4412
4413
4414
4415
4416s32 igc_write_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr, u16 data)
4417{
4418 DEBUGFUNC("igc_write_xmdio_reg");
4419
4420 return __igc_access_xmdio_reg(hw, addr, dev_addr, &data,
4421 false);
4422}
4423