/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2010-2016 Intel Corporation.
 * Copyright 2014 6WIND S.A.
 */

#include <sys/queue.h>

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <errno.h>
#include <stdint.h>
#include <stdarg.h>
#include <unistd.h>
#include <inttypes.h>

#include <rte_byteorder.h>
#include <rte_common.h>
#include <rte_cycles.h>
#include <rte_log.h>
#include <rte_debug.h>
#include <rte_interrupts.h>
#include <rte_pci.h>
#include <rte_memory.h>
#include <rte_memzone.h>
#include <rte_launch.h>
#include <rte_eal.h>
#include <rte_per_lcore.h>
#include <rte_lcore.h>
#include <rte_atomic.h>
#include <rte_branch_prediction.h>
#include <rte_mempool.h>
#include <rte_malloc.h>
#include <rte_mbuf.h>
#include <rte_ether.h>
#include <ethdev_driver.h>
#include <rte_security_driver.h>
#include <rte_prefetch.h>
#include <rte_udp.h>
#include <rte_tcp.h>
#include <rte_sctp.h>
#include <rte_string_fns.h>
#include <rte_errno.h>
#include <rte_ip.h>
#include <rte_net.h>
#include <rte_vect.h>

#include "ixgbe_logs.h"
#include "base/ixgbe_api.h"
#include "base/ixgbe_vf.h"
#include "ixgbe_ethdev.h"
#include "base/ixgbe_dcb.h"
#include "base/ixgbe_common.h"
#include "ixgbe_rxtx.h"

#ifdef RTE_LIBRTE_IEEE1588
#define IXGBE_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
#else
#define IXGBE_TX_IEEE1588_TMST 0
#endif
/* Bit Mask to indicate what bits required for building TX context */
#define IXGBE_TX_OFFLOAD_MASK (                  \
                PKT_TX_OUTER_IPV6 |              \
                PKT_TX_OUTER_IPV4 |              \
                PKT_TX_IPV6 |                    \
                PKT_TX_IPV4 |                    \
                PKT_TX_VLAN_PKT |                \
                PKT_TX_IP_CKSUM |                \
                PKT_TX_L4_MASK |                 \
                PKT_TX_TCP_SEG |                 \
                PKT_TX_MACSEC |                  \
                PKT_TX_OUTER_IP_CKSUM |          \
                PKT_TX_SEC_OFFLOAD |     \
                IXGBE_TX_IEEE1588_TMST)

#define IXGBE_TX_OFFLOAD_NOTSUP_MASK \
                (PKT_TX_OFFLOAD_MASK ^ IXGBE_TX_OFFLOAD_MASK)

#if 1
#define RTE_PMD_USE_PREFETCH
#endif

#ifdef RTE_PMD_USE_PREFETCH
/*
 * Prefetch a cache line into all cache levels.
 */
#define rte_ixgbe_prefetch(p)   rte_prefetch0(p)
#else
#define rte_ixgbe_prefetch(p)   do {} while (0)
#endif

/*********************************************************************
 *
 *  TX functions
 *
 **********************************************************************/

/*
 * Check for descriptors with their DD bit set and free mbufs.
 * Return the total number of buffers freed.
 */
static __rte_always_inline int
ixgbe_tx_free_bufs(struct ixgbe_tx_queue *txq)
{
        struct ixgbe_tx_entry *txep;
        uint32_t status;
        int i, nb_free = 0;
        struct rte_mbuf *m, *free[RTE_IXGBE_TX_MAX_FREE_BUF_SZ];

        /* check DD bit on threshold descriptor */
        status = txq->tx_ring[txq->tx_next_dd].wb.status;
        if (!(status & rte_cpu_to_le_32(IXGBE_ADVTXD_STAT_DD)))
                return 0;

        /*
         * first buffer to free from S/W ring is at index
         * tx_next_dd - (tx_rs_thresh-1)
         */
        txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);

        for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
                /* free buffers one at a time */
                m = rte_pktmbuf_prefree_seg(txep->mbuf);
                txep->mbuf = NULL;

                if (unlikely(m == NULL))
                        continue;

                if (nb_free >= RTE_IXGBE_TX_MAX_FREE_BUF_SZ ||
                    (nb_free > 0 && m->pool != free[0]->pool)) {
                        rte_mempool_put_bulk(free[0]->pool,
                                             (void **)free, nb_free);
                        nb_free = 0;
                }

                free[nb_free++] = m;
        }

        if (nb_free > 0)
                rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);

        /* buffers were freed, update counters */
        txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
        txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
        if (txq->tx_next_dd >= txq->nb_tx_desc)
                txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);

        return txq->tx_rs_thresh;
}

/* Populate 4 descriptors with data from 4 mbufs */
static inline void
tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
{
        uint64_t buf_dma_addr;
        uint32_t pkt_len;
        int i;

        for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
                buf_dma_addr = rte_mbuf_data_iova(*pkts);
                pkt_len = (*pkts)->data_len;

                /* write data to descriptor */
                txdp->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr);

                txdp->read.cmd_type_len =
                        rte_cpu_to_le_32((uint32_t)DCMD_DTYP_FLAGS | pkt_len);

                txdp->read.olinfo_status =
                        rte_cpu_to_le_32(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);

                rte_prefetch0(&(*pkts)->pool);
        }
}

/* Populate 1 descriptor with data from 1 mbuf */
static inline void
tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
{
        uint64_t buf_dma_addr;
        uint32_t pkt_len;

        buf_dma_addr = rte_mbuf_data_iova(*pkts);
        pkt_len = (*pkts)->data_len;

        /* write data to descriptor */
        txdp->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
        txdp->read.cmd_type_len =
                        rte_cpu_to_le_32((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
        txdp->read.olinfo_status =
                        rte_cpu_to_le_32(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
        rte_prefetch0(&(*pkts)->pool);
}

/*
 * Fill H/W descriptor ring with mbuf data.
 * Copy mbuf pointers to the S/W ring.
 */
static inline void
ixgbe_tx_fill_hw_ring(struct ixgbe_tx_queue *txq, struct rte_mbuf **pkts,
                      uint16_t nb_pkts)
{
        volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
        struct ixgbe_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
        const int N_PER_LOOP = 4;
        const int N_PER_LOOP_MASK = N_PER_LOOP-1;
        int mainpart, leftover;
        int i, j;

        /*
         * Process most of the packets in chunks of N pkts.  Any
         * leftover packets will get processed one at a time.
         */
        mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
        leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
        for (i = 0; i < mainpart; i += N_PER_LOOP) {
                /* Copy N mbuf pointers to the S/W ring */
                for (j = 0; j < N_PER_LOOP; ++j) {
                        (txep + i + j)->mbuf = *(pkts + i + j);
                }
                tx4(txdp + i, pkts + i);
        }

        if (unlikely(leftover > 0)) {
                for (i = 0; i < leftover; ++i) {
                        (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
                        tx1(txdp + mainpart + i, pkts + mainpart + i);
                }
        }
}

static inline uint16_t
tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
             uint16_t nb_pkts)
{
        struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
        volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
        uint16_t n = 0;

        /*
         * Begin scanning the H/W ring for done descriptors when the
         * number of available descriptors drops below tx_free_thresh.  For
         * each done descriptor, free the associated buffer.
         */
        if (txq->nb_tx_free < txq->tx_free_thresh)
                ixgbe_tx_free_bufs(txq);

        /* Only use descriptors that are available */
        nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
        if (unlikely(nb_pkts == 0))
                return 0;

        /* Use exactly nb_pkts descriptors */
        txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);

        /*
         * At this point, we know there are enough descriptors in the
         * ring to transmit all the packets.  This assumes that each
         * mbuf contains a single segment, and that no new offloads
         * are expected, which would require a new context descriptor.
         */

        /*
         * See if we're going to wrap-around. If so, handle the top
         * of the descriptor ring first, then do the bottom.  If not,
         * the processing looks just like the "bottom" part anyway...
         */
        if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
                n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
                ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);

                /*
                 * We know that the last descriptor in the ring will need to
                 * have its RS bit set because tx_rs_thresh has to be
                 * a divisor of the ring size
                 */
                tx_r[txq->tx_next_rs].read.cmd_type_len |=
                        rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
                txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);

                txq->tx_tail = 0;
        }

        /* Fill H/W descriptor ring with mbuf data */
        ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
        txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));

        /*
         * Determine if RS bit should be set
         * This is what we actually want:
         *   if ((txq->tx_tail - 1) >= txq->tx_next_rs)
         * but instead of subtracting 1 and doing >=, we can just do
         * greater than without subtracting.
         */
        if (txq->tx_tail > txq->tx_next_rs) {
                tx_r[txq->tx_next_rs].read.cmd_type_len |=
                        rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
                txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
                                                txq->tx_rs_thresh);
                if (txq->tx_next_rs >= txq->nb_tx_desc)
                        txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
        }

        /*
         * Check for wrap-around. This would only happen if we used
         * up to the last descriptor in the ring, no more, no less.
         */
        if (txq->tx_tail >= txq->nb_tx_desc)
                txq->tx_tail = 0;

        /* update tail pointer */
        rte_wmb();
        IXGBE_PCI_REG_WC_WRITE_RELAXED(txq->tdt_reg_addr, txq->tx_tail);

        return nb_pkts;
}

uint16_t
ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
                       uint16_t nb_pkts)
{
        uint16_t nb_tx;

        /* Try to transmit at least chunks of TX_MAX_BURST pkts */
        if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
                return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);

        /* transmit more than the max burst, in chunks of TX_MAX_BURST */
        nb_tx = 0;
        while (nb_pkts) {
                uint16_t ret, n;

                n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
                ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
                nb_tx = (uint16_t)(nb_tx + ret);
                nb_pkts = (uint16_t)(nb_pkts - ret);
                if (ret < n)
                        break;
        }

        return nb_tx;
}

static uint16_t
ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
                    uint16_t nb_pkts)
{
        uint16_t nb_tx = 0;
        struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;

        while (nb_pkts) {
                uint16_t ret, num;

                num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
                ret = ixgbe_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
                                                 num);
                nb_tx += ret;
                nb_pkts -= ret;
                if (ret < num)
                        break;
        }

        return nb_tx;
}

static inline void
ixgbe_set_xmit_ctx(struct ixgbe_tx_queue *txq,
                volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
                uint64_t ol_flags, union ixgbe_tx_offload tx_offload,
                __rte_unused uint64_t *mdata)
{
        uint32_t type_tucmd_mlhl;
        uint32_t mss_l4len_idx = 0;
        uint32_t ctx_idx;
        uint32_t vlan_macip_lens;
        union ixgbe_tx_offload tx_offload_mask;
        uint32_t seqnum_seed = 0;

        ctx_idx = txq->ctx_curr;
        tx_offload_mask.data[0] = 0;
        tx_offload_mask.data[1] = 0;
        type_tucmd_mlhl = 0;

        /* Specify which HW CTX to upload. */
        mss_l4len_idx |= (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);

        if (ol_flags & PKT_TX_VLAN_PKT) {
                tx_offload_mask.vlan_tci |= ~0;
        }

        /* check if TCP segmentation required for this packet */
        if (ol_flags & PKT_TX_TCP_SEG) {
                /* implies IP cksum in IPv4 */
                if (ol_flags & PKT_TX_IP_CKSUM)
                        type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4 |
                                IXGBE_ADVTXD_TUCMD_L4T_TCP |
                                IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
                else
                        type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV6 |
                                IXGBE_ADVTXD_TUCMD_L4T_TCP |
                                IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;

                tx_offload_mask.l2_len |= ~0;
                tx_offload_mask.l3_len |= ~0;
                tx_offload_mask.l4_len |= ~0;
                tx_offload_mask.tso_segsz |= ~0;
                mss_l4len_idx |= tx_offload.tso_segsz << IXGBE_ADVTXD_MSS_SHIFT;
                mss_l4len_idx |= tx_offload.l4_len << IXGBE_ADVTXD_L4LEN_SHIFT;
        } else { /* no TSO, check if hardware checksum is needed */
                if (ol_flags & PKT_TX_IP_CKSUM) {
                        type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
                        tx_offload_mask.l2_len |= ~0;
                        tx_offload_mask.l3_len |= ~0;
                }

                switch (ol_flags & PKT_TX_L4_MASK) {
                case PKT_TX_UDP_CKSUM:
                        type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
                                IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
                        mss_l4len_idx |= sizeof(struct rte_udp_hdr)
                                << IXGBE_ADVTXD_L4LEN_SHIFT;
                        tx_offload_mask.l2_len |= ~0;
                        tx_offload_mask.l3_len |= ~0;
                        break;
                case PKT_TX_TCP_CKSUM:
                        type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
                                IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
                        mss_l4len_idx |= sizeof(struct rte_tcp_hdr)
                                << IXGBE_ADVTXD_L4LEN_SHIFT;
                        tx_offload_mask.l2_len |= ~0;
                        tx_offload_mask.l3_len |= ~0;
                        break;
                case PKT_TX_SCTP_CKSUM:
                        type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
                                IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
                        mss_l4len_idx |= sizeof(struct rte_sctp_hdr)
                                << IXGBE_ADVTXD_L4LEN_SHIFT;
                        tx_offload_mask.l2_len |= ~0;
                        tx_offload_mask.l3_len |= ~0;
                        break;
                default:
                        type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
                                IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
                        break;
                }
        }

        if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
                tx_offload_mask.outer_l2_len |= ~0;
                tx_offload_mask.outer_l3_len |= ~0;
                tx_offload_mask.l2_len |= ~0;
                seqnum_seed |= tx_offload.outer_l3_len
                               << IXGBE_ADVTXD_OUTER_IPLEN;
                seqnum_seed |= tx_offload.l2_len
                               << IXGBE_ADVTXD_TUNNEL_LEN;
        }
#ifdef RTE_LIB_SECURITY
        if (ol_flags & PKT_TX_SEC_OFFLOAD) {
                union ixgbe_crypto_tx_desc_md *md =
                                (union ixgbe_crypto_tx_desc_md *)mdata;
                seqnum_seed |=
                        (IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK & md->sa_idx);
                type_tucmd_mlhl |= md->enc ?
                                (IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP |
                                IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN) : 0;
                type_tucmd_mlhl |=
                        (md->pad_len & IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK);
                tx_offload_mask.sa_idx |= ~0;
                tx_offload_mask.sec_pad_len |= ~0;
        }
#endif

        txq->ctx_cache[ctx_idx].flags = ol_flags;
        txq->ctx_cache[ctx_idx].tx_offload.data[0]  =
                tx_offload_mask.data[0] & tx_offload.data[0];
        txq->ctx_cache[ctx_idx].tx_offload.data[1]  =
                tx_offload_mask.data[1] & tx_offload.data[1];
        txq->ctx_cache[ctx_idx].tx_offload_mask    = tx_offload_mask;

        ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
        vlan_macip_lens = tx_offload.l3_len;
        if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
                vlan_macip_lens |= (tx_offload.outer_l2_len <<
                                    IXGBE_ADVTXD_MACLEN_SHIFT);
        else
                vlan_macip_lens |= (tx_offload.l2_len <<
                                    IXGBE_ADVTXD_MACLEN_SHIFT);
        vlan_macip_lens |= ((uint32_t)tx_offload.vlan_tci << IXGBE_ADVTXD_VLAN_SHIFT);
        ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
        ctx_txd->mss_l4len_idx   = rte_cpu_to_le_32(mss_l4len_idx);
        ctx_txd->seqnum_seed     = seqnum_seed;
}

/*
 * Check which hardware context can be used. Use the existing match
 * or create a new context descriptor.
 */
static inline uint32_t
what_advctx_update(struct ixgbe_tx_queue *txq, uint64_t flags,
                   union ixgbe_tx_offload tx_offload)
{
        /* If match with the current used context */
        if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
                   (txq->ctx_cache[txq->ctx_curr].tx_offload.data[0] ==
                    (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[0]
                     & tx_offload.data[0])) &&
                   (txq->ctx_cache[txq->ctx_curr].tx_offload.data[1] ==
                    (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[1]
                     & tx_offload.data[1]))))
                return txq->ctx_curr;

        /* What if match with the next context  */
        txq->ctx_curr ^= 1;
        if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
                   (txq->ctx_cache[txq->ctx_curr].tx_offload.data[0] ==
                    (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[0]
                     & tx_offload.data[0])) &&
                   (txq->ctx_cache[txq->ctx_curr].tx_offload.data[1] ==
                    (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[1]
                     & tx_offload.data[1]))))
                return txq->ctx_curr;

        /* Mismatch, use the previous context */
        return IXGBE_CTX_NUM;
}

static inline uint32_t
tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
{
        uint32_t tmp = 0;

        if ((ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM)
                tmp |= IXGBE_ADVTXD_POPTS_TXSM;
        if (ol_flags & PKT_TX_IP_CKSUM)
                tmp |= IXGBE_ADVTXD_POPTS_IXSM;
        if (ol_flags & PKT_TX_TCP_SEG)
                tmp |= IXGBE_ADVTXD_POPTS_TXSM;
        return tmp;
}

static inline uint32_t
tx_desc_ol_flags_to_cmdtype(uint64_t ol_flags)
{
        uint32_t cmdtype = 0;

        if (ol_flags & PKT_TX_VLAN_PKT)
                cmdtype |= IXGBE_ADVTXD_DCMD_VLE;
        if (ol_flags & PKT_TX_TCP_SEG)
                cmdtype |= IXGBE_ADVTXD_DCMD_TSE;
        if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
                cmdtype |= (1 << IXGBE_ADVTXD_OUTERIPCS_SHIFT);
        if (ol_flags & PKT_TX_MACSEC)
                cmdtype |= IXGBE_ADVTXD_MAC_LINKSEC;
        return cmdtype;
}

/* Default RS bit threshold values */
#ifndef DEFAULT_TX_RS_THRESH
#define DEFAULT_TX_RS_THRESH   32
#endif
#ifndef DEFAULT_TX_FREE_THRESH
#define DEFAULT_TX_FREE_THRESH 32
#endif

/* Reset transmit descriptors after they have been used */
static inline int
ixgbe_xmit_cleanup(struct ixgbe_tx_queue *txq)
{
        struct ixgbe_tx_entry *sw_ring = txq->sw_ring;
        volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
        uint16_t last_desc_cleaned = txq->last_desc_cleaned;
        uint16_t nb_tx_desc = txq->nb_tx_desc;
        uint16_t desc_to_clean_to;
        uint16_t nb_tx_to_clean;
        uint32_t status;

        /* Determine the last descriptor needing to be cleaned */
        desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
        if (desc_to_clean_to >= nb_tx_desc)
                desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);

        /* Check to make sure the last descriptor to clean is done */
        desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
        status = txr[desc_to_clean_to].wb.status;
        if (!(status & rte_cpu_to_le_32(IXGBE_TXD_STAT_DD))) {
                PMD_TX_LOG(DEBUG,
                           "TX descriptor %4u is not done"
                           "(port=%d queue=%d)",
                           desc_to_clean_to,
                           txq->port_id, txq->queue_id);
                /* Failed to clean any descriptors, better luck next time */
                return -(1);
        }

        /* Figure out how many descriptors will be cleaned */
        if (last_desc_cleaned > desc_to_clean_to)
                nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
                                                        desc_to_clean_to);
        else
                nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
                                                last_desc_cleaned);

        PMD_TX_LOG(DEBUG,
                   "Cleaning %4u TX descriptors: %4u to %4u "
                   "(port=%d queue=%d)",
                   nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
                   txq->port_id, txq->queue_id);

        /*
         * The last descriptor to clean is done, so that means all the
         * descriptors from the last descriptor that was cleaned
         * up to the last descriptor with the RS bit set
         * are done. Only reset the threshold descriptor.
         */
        txr[desc_to_clean_to].wb.status = 0;

        /* Update the txq to reflect the last descriptor that was cleaned */
        txq->last_desc_cleaned = desc_to_clean_to;
        txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);

        /* No Error */
        return 0;
}

uint16_t
ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
                uint16_t nb_pkts)
{
        struct ixgbe_tx_queue *txq;
        struct ixgbe_tx_entry *sw_ring;
        struct ixgbe_tx_entry *txe, *txn;
        volatile union ixgbe_adv_tx_desc *txr;
        volatile union ixgbe_adv_tx_desc *txd, *txp;
        struct rte_mbuf     *tx_pkt;
        struct rte_mbuf     *m_seg;
        uint64_t buf_dma_addr;
        uint32_t olinfo_status;
        uint32_t cmd_type_len;
        uint32_t pkt_len;
        uint16_t slen;
        uint64_t ol_flags;
        uint16_t tx_id;
        uint16_t tx_last;
        uint16_t nb_tx;
        uint16_t nb_used;
        uint64_t tx_ol_req;
        uint32_t ctx = 0;
        uint32_t new_ctx;
        union ixgbe_tx_offload tx_offload;
#ifdef RTE_LIB_SECURITY
        uint8_t use_ipsec;
#endif

        tx_offload.data[0] = 0;
        tx_offload.data[1] = 0;
        txq = tx_queue;
        sw_ring = txq->sw_ring;
        txr     = txq->tx_ring;
        tx_id   = txq->tx_tail;
        txe = &sw_ring[tx_id];
        txp = NULL;

        /* Determine if the descriptor ring needs to be cleaned. */
        if (txq->nb_tx_free < txq->tx_free_thresh)
                ixgbe_xmit_cleanup(txq);

        rte_prefetch0(&txe->mbuf->pool);

        /* TX loop */
        for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
                new_ctx = 0;
                tx_pkt = *tx_pkts++;
                pkt_len = tx_pkt->pkt_len;

                /*
                 * Determine how many (if any) context descriptors
                 * are needed for offload functionality.
                 */
                ol_flags = tx_pkt->ol_flags;
#ifdef RTE_LIB_SECURITY
                use_ipsec = txq->using_ipsec && (ol_flags & PKT_TX_SEC_OFFLOAD);
#endif

                /* If hardware offload required */
                tx_ol_req = ol_flags & IXGBE_TX_OFFLOAD_MASK;
                if (tx_ol_req) {
                        tx_offload.l2_len = tx_pkt->l2_len;
                        tx_offload.l3_len = tx_pkt->l3_len;
                        tx_offload.l4_len = tx_pkt->l4_len;
                        tx_offload.vlan_tci = tx_pkt->vlan_tci;
                        tx_offload.tso_segsz = tx_pkt->tso_segsz;
                        tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
                        tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
#ifdef RTE_LIB_SECURITY
                        if (use_ipsec) {
                                union ixgbe_crypto_tx_desc_md *ipsec_mdata =
                                        (union ixgbe_crypto_tx_desc_md *)
                                                rte_security_dynfield(tx_pkt);
                                tx_offload.sa_idx = ipsec_mdata->sa_idx;
                                tx_offload.sec_pad_len = ipsec_mdata->pad_len;
                        }
#endif

                        /* If new context need be built or reuse the exist ctx. */
                        ctx = what_advctx_update(txq, tx_ol_req,
                                tx_offload);
                        /* Only allocate context descriptor if required*/
                        new_ctx = (ctx == IXGBE_CTX_NUM);
                        ctx = txq->ctx_curr;
                }

                /*
                 * Keep track of how many descriptors are used this loop
                 * This will always be the number of segments + the number of
                 * Context descriptors required to transmit the packet
                 */
                nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);

                if (txp != NULL &&
                                nb_used + txq->nb_tx_used >= txq->tx_rs_thresh)
                        /* set RS on the previous packet in the burst */
                        txp->read.cmd_type_len |=
                                rte_cpu_to_le_32(IXGBE_TXD_CMD_RS);

                /*
                 * The number of descriptors that must be allocated for a
                 * packet is the number of segments of that packet, plus 1
                 * Context Descriptor for the hardware offload, if any.
                 * Determine the last TX descriptor to allocate in the TX ring
                 * for the packet, starting from the current position (tx_id)
                 * in the ring.
                 */
                tx_last = (uint16_t) (tx_id + nb_used - 1);

                /* Circular ring */
                if (tx_last >= txq->nb_tx_desc)
                        tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);

                PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
                           " tx_first=%u tx_last=%u",
                           (unsigned) txq->port_id,
                           (unsigned) txq->queue_id,
                           (unsigned) pkt_len,
                           (unsigned) tx_id,
                           (unsigned) tx_last);

                /*
                 * Make sure there are enough TX descriptors available to
                 * transmit the entire packet.
                 * nb_used better be less than or equal to txq->tx_rs_thresh
                 */
                if (nb_used > txq->nb_tx_free) {
                        PMD_TX_LOG(DEBUG,
                                   "Not enough free TX descriptors "
                                   "nb_used=%4u nb_free=%4u "
                                   "(port=%d queue=%d)",
                                   nb_used, txq->nb_tx_free,
                                   txq->port_id, txq->queue_id);

                        if (ixgbe_xmit_cleanup(txq) != 0) {
                                /* Could not clean any descriptors */
                                if (nb_tx == 0)
                                        return 0;
                                goto end_of_tx;
                        }

                        /* nb_used better be <= txq->tx_rs_thresh */
                        if (unlikely(nb_used > txq->tx_rs_thresh)) {
                                PMD_TX_LOG(DEBUG,
                                           "The number of descriptors needed to "
                                           "transmit the packet exceeds the "
                                           "RS bit threshold. This will impact "
                                           "performance."
                                           "nb_used=%4u nb_free=%4u "
                                           "tx_rs_thresh=%4u. "
                                           "(port=%d queue=%d)",
                                           nb_used, txq->nb_tx_free,
                                           txq->tx_rs_thresh,
                                           txq->port_id, txq->queue_id);
                                /*
                                 * Loop here until there are enough TX
                                 * descriptors or until the ring cannot be
                                 * cleaned.
                                 */
                                while (nb_used > txq->nb_tx_free) {
                                        if (ixgbe_xmit_cleanup(txq) != 0) {
                                                /*
                                                 * Could not clean any
                                                 * descriptors
                                                 */
                                                if (nb_tx == 0)
                                                        return 0;
                                                goto end_of_tx;
                                        }
                                }
                        }
                }

                /*
                 * By now there are enough free TX descriptors to transmit
                 * the packet.
                 */

                /*
                 * Set common flags of all TX Data Descriptors.
                 *
                 * The following bits must be set in all Data Descriptors:
                 *   - IXGBE_ADVTXD_DTYP_DATA
                 *   - IXGBE_ADVTXD_DCMD_DEXT
                 *
                 * The following bits must be set in the first Data Descriptor
                 * and are ignored in the other ones:
                 *   - IXGBE_ADVTXD_DCMD_IFCS
                 *   - IXGBE_ADVTXD_MAC_1588
                 *   - IXGBE_ADVTXD_DCMD_VLE
                 *
                 * The following bits must only be set in the last Data
                 * Descriptor:
                 *   - IXGBE_TXD_CMD_EOP
                 *
                 * The following bits can be set in any Data Descriptor, but
                 * are only set in the last Data Descriptor:
                 *   - IXGBE_TXD_CMD_RS
                 */
                cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
                        IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;

#ifdef RTE_LIBRTE_IEEE1588
                if (ol_flags & PKT_TX_IEEE1588_TMST)
                        cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
#endif

                olinfo_status = 0;
                if (tx_ol_req) {

                        if (ol_flags & PKT_TX_TCP_SEG) {
                                /* when TSO is on, paylen in descriptor is the
                                 * not the packet len but the tcp payload len */
                                pkt_len -= (tx_offload.l2_len +
                                        tx_offload.l3_len + tx_offload.l4_len);
                        }

                        /*
                         * Setup the TX Advanced Context Descriptor if required
                         */
                        if (new_ctx) {
                                volatile struct ixgbe_adv_tx_context_desc *
                                    ctx_txd;

                                ctx_txd = (volatile struct
                                    ixgbe_adv_tx_context_desc *)
                                    &txr[tx_id];

                                txn = &sw_ring[txe->next_id];
                                rte_prefetch0(&txn->mbuf->pool);

                                if (txe->mbuf != NULL) {
                                        rte_pktmbuf_free_seg(txe->mbuf);
                                        txe->mbuf = NULL;
                                }

                                ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
                                        tx_offload,
                                        rte_security_dynfield(tx_pkt));

                                txe->last_id = tx_last;
                                tx_id = txe->next_id;
                                txe = txn;
                        }

                        /*
                         * Setup the TX Advanced Data Descriptor,
                         * This path will go through
                         * whatever new/reuse the context descriptor
                         */
                        cmd_type_len  |= tx_desc_ol_flags_to_cmdtype(ol_flags);
                        olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
                        olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
                }

                olinfo_status |= (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
#ifdef RTE_LIB_SECURITY
                if (use_ipsec)
                        olinfo_status |= IXGBE_ADVTXD_POPTS_IPSEC;
#endif

                m_seg = tx_pkt;
                do {
                        txd = &txr[tx_id];
                        txn = &sw_ring[txe->next_id];
                        rte_prefetch0(&txn->mbuf->pool);

                        if (txe->mbuf != NULL)
                                rte_pktmbuf_free_seg(txe->mbuf);
                        txe->mbuf = m_seg;

                        /*
                         * Set up Transmit Data Descriptor.
                         */
                        slen = m_seg->data_len;
                        buf_dma_addr = rte_mbuf_data_iova(m_seg);
                        txd->read.buffer_addr =
                                rte_cpu_to_le_64(buf_dma_addr);
                        txd->read.cmd_type_len =
                                rte_cpu_to_le_32(cmd_type_len | slen);
                        txd->read.olinfo_status =
                                rte_cpu_to_le_32(olinfo_status);
                        txe->last_id = tx_last;
                        tx_id = txe->next_id;
                        txe = txn;
                        m_seg = m_seg->next;
                } while (m_seg != NULL);

                /*
                 * The last packet data descriptor needs End Of Packet (EOP)
                 */
                cmd_type_len |= IXGBE_TXD_CMD_EOP;
                txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
                txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);

                /* Set RS bit only on threshold packets' last descriptor */
                if (txq->nb_tx_used >= txq->tx_rs_thresh) {
                        PMD_TX_LOG(DEBUG,
                                   "Setting RS bit on TXD id="
                                   "%4u (port=%d queue=%d)",
                                   tx_last, txq->port_id, txq->queue_id);

                        cmd_type_len |= IXGBE_TXD_CMD_RS;

                        /* Update txq RS bit counters */
                        txq->nb_tx_used = 0;
                        txp = NULL;
                } else
                        txp = txd;

                txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
        }

end_of_tx:
        /* set RS on last packet in the burst */
        if (txp != NULL)
                txp->read.cmd_type_len |= rte_cpu_to_le_32(IXGBE_TXD_CMD_RS);

        rte_wmb();

        /*
         * Set the Transmit Descriptor Tail (TDT)
         */
        PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
                   (unsigned) txq->port_id, (unsigned) txq->queue_id,
                   (unsigned) tx_id, (unsigned) nb_tx);
        IXGBE_PCI_REG_WC_WRITE_RELAXED(txq->tdt_reg_addr, tx_id);
        txq->tx_tail = tx_id;

        return nb_tx;
}

/*********************************************************************
 *
 *  TX prep functions
 *
 **********************************************************************/
uint16_t
ixgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
{
        int i, ret;
        uint64_t ol_flags;
        struct rte_mbuf *m;
        struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;

        for (i = 0; i < nb_pkts; i++) {
                m = tx_pkts[i];
                ol_flags = m->ol_flags;

                /**
                 * Check if packet meets requirements for number of segments
                 *
                 * NOTE: for ixgbe it's always (40 - WTHRESH) for both TSO and
                 *       non-TSO
                 */

                if (m->nb_segs > IXGBE_TX_MAX_SEG - txq->wthresh) {
                        rte_errno = EINVAL;
                        return i;
                }

                if (ol_flags & IXGBE_TX_OFFLOAD_NOTSUP_MASK) {
                        rte_errno = ENOTSUP;
                        return i;
                }

                /* check the size of packet */
                if (m->pkt_len < IXGBE_TX_MIN_PKT_LEN) {
                        rte_errno = EINVAL;
                        return i;
                }

#ifdef RTE_ETHDEV_DEBUG_TX
                ret = rte_validate_tx_offload(m);
                if (ret != 0) {

                        rte_errno = -ret;
                        return i;
                }
#endif
                ret = rte_net_intel_cksum_prepare(m);
                if (ret != 0) {
                        rte_errno = -ret;
                        return i;
                }
        }

        return i;
}

/*********************************************************************
 *
 *  RX functions
 *
 **********************************************************************/

#define IXGBE_PACKET_TYPE_ETHER                         0X00
#define IXGBE_PACKET_TYPE_IPV4                          0X01
#define IXGBE_PACKET_TYPE_IPV4_TCP                      0X11
#define IXGBE_PACKET_TYPE_IPV4_UDP                      0X21
#define IXGBE_PACKET_TYPE_IPV4_SCTP                     0X41
#define IXGBE_PACKET_TYPE_IPV4_EXT                      0X03
#define IXGBE_PACKET_TYPE_IPV4_EXT_TCP                  0X13
#define IXGBE_PACKET_TYPE_IPV4_EXT_UDP                  0X23
#define IXGBE_PACKET_TYPE_IPV4_EXT_SCTP                 0X43
#define IXGBE_PACKET_TYPE_IPV6                          0X04
#define IXGBE_PACKET_TYPE_IPV6_TCP                      0X14
#define IXGBE_PACKET_TYPE_IPV6_UDP                      0X24
#define IXGBE_PACKET_TYPE_IPV6_SCTP                     0X44
#define IXGBE_PACKET_TYPE_IPV6_EXT                      0X0C
#define IXGBE_PACKET_TYPE_IPV6_EXT_TCP                  0X1C
#define IXGBE_PACKET_TYPE_IPV6_EXT_UDP                  0X2C
#define IXGBE_PACKET_TYPE_IPV6_EXT_SCTP                 0X4C
#define IXGBE_PACKET_TYPE_IPV4_IPV6                     0X05
#define IXGBE_PACKET_TYPE_IPV4_IPV6_TCP                 0X15
#define IXGBE_PACKET_TYPE_IPV4_IPV6_UDP                 0X25
#define IXGBE_PACKET_TYPE_IPV4_IPV6_SCTP                0X45
#define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6                 0X07
#define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_TCP             0X17
#define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_UDP             0X27
#define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_SCTP            0X47
#define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT                 0X0D
#define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_TCP             0X1D
#define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_UDP             0X2D
#define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_SCTP            0X4D
#define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT             0X0F
#define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_TCP         0X1F
#define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_UDP         0X2F
#define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_SCTP        0X4F

#define IXGBE_PACKET_TYPE_NVGRE                   0X00
#define IXGBE_PACKET_TYPE_NVGRE_IPV4              0X01
#define IXGBE_PACKET_TYPE_NVGRE_IPV4_TCP          0X11
#define IXGBE_PACKET_TYPE_NVGRE_IPV4_UDP          0X21
#define IXGBE_PACKET_TYPE_NVGRE_IPV4_SCTP         0X41
#define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT          0X03
#define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_TCP      0X13
#define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_UDP      0X23
#define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_SCTP     0X43
#define IXGBE_PACKET_TYPE_NVGRE_IPV6              0X04
#define IXGBE_PACKET_TYPE_NVGRE_IPV6_TCP          0X14
#define IXGBE_PACKET_TYPE_NVGRE_IPV6_UDP          0X24
#define IXGBE_PACKET_TYPE_NVGRE_IPV6_SCTP         0X44
#define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT          0X0C
#define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_TCP      0X1C
#define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_UDP      0X2C
#define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_SCTP     0X4C
#define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6         0X05
#define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_TCP     0X15
#define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_UDP     0X25
#define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT     0X0D
#define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_TCP 0X1D
#define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_UDP 0X2D

#define IXGBE_PACKET_TYPE_VXLAN                   0X80
#define IXGBE_PACKET_TYPE_VXLAN_IPV4              0X81
#define IXGBE_PACKET_TYPE_VXLAN_IPV4_TCP          0x91
#define IXGBE_PACKET_TYPE_VXLAN_IPV4_UDP          0xA1
#define IXGBE_PACKET_TYPE_VXLAN_IPV4_SCTP         0xC1
#define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT          0x83
#define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_TCP      0X93
#define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_UDP      0XA3
#define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_SCTP     0XC3
#define IXGBE_PACKET_TYPE_VXLAN_IPV6              0X84
#define IXGBE_PACKET_TYPE_VXLAN_IPV6_TCP          0X94
#define IXGBE_PACKET_TYPE_VXLAN_IPV6_UDP          0XA4
#define IXGBE_PACKET_TYPE_VXLAN_IPV6_SCTP         0XC4
#define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT          0X8C
#define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_TCP      0X9C
#define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_UDP      0XAC
#define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_SCTP     0XCC
#define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6         0X85
#define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_TCP     0X95
#define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_UDP     0XA5
#define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT     0X8D
#define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_TCP 0X9D
#define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_UDP 0XAD

/**
 * Use 2 different table for normal packet and tunnel packet
 * to save the space.
 */
const uint32_t
        ptype_table[IXGBE_PACKET_TYPE_MAX] __rte_cache_aligned = {
        [IXGBE_PACKET_TYPE_ETHER] = RTE_PTYPE_L2_ETHER,
        [IXGBE_PACKET_TYPE_IPV4] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4,
        [IXGBE_PACKET_TYPE_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
        [IXGBE_PACKET_TYPE_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
        [IXGBE_PACKET_TYPE_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_SCTP,
        [IXGBE_PACKET_TYPE_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT,
        [IXGBE_PACKET_TYPE_IPV4_EXT_TCP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_TCP,
        [IXGBE_PACKET_TYPE_IPV4_EXT_UDP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_UDP,
        [IXGBE_PACKET_TYPE_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_SCTP,
        [IXGBE_PACKET_TYPE_IPV6] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV6,
        [IXGBE_PACKET_TYPE_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
        [IXGBE_PACKET_TYPE_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
        [IXGBE_PACKET_TYPE_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_SCTP,
        [IXGBE_PACKET_TYPE_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV6_EXT,
        [IXGBE_PACKET_TYPE_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_TCP,
        [IXGBE_PACKET_TYPE_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_UDP,
        [IXGBE_PACKET_TYPE_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_SCTP,
        [IXGBE_PACKET_TYPE_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
                RTE_PTYPE_INNER_L3_IPV6,
        [IXGBE_PACKET_TYPE_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
                RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
        [IXGBE_PACKET_TYPE_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
        RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
        [IXGBE_PACKET_TYPE_IPV4_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
                RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_SCTP,
        [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
                RTE_PTYPE_INNER_L3_IPV6,
        [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
                RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
        [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
                RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
        [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
                RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_SCTP,
        [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
                RTE_PTYPE_INNER_L3_IPV6_EXT,
        [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
                RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
        [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
                RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
        [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
                RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_SCTP,
        [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
                RTE_PTYPE_INNER_L3_IPV6_EXT,
        [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
                RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
        [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
                RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
        [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_SCTP] =
                RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
                RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_SCTP,
};

const uint32_t
        ptype_table_tn[IXGBE_PACKET_TYPE_TN_MAX] __rte_cache_aligned = {
        [IXGBE_PACKET_TYPE_NVGRE] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
                RTE_PTYPE_INNER_L2_ETHER,
        [IXGBE_PACKET_TYPE_NVGRE_IPV4] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
                RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
        [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
                RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT,
        [IXGBE_PACKET_TYPE_NVGRE_IPV6] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
                RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6,
        [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
                RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
        [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
                RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT,
        [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
                RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
        [IXGBE_PACKET_TYPE_NVGRE_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
                RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4 |
                RTE_PTYPE_INNER_L4_TCP,
        [IXGBE_PACKET_TYPE_NVGRE_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
                RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6 |
                RTE_PTYPE_INNER_L4_TCP,
        [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
                RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
        [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
                RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT |
                RTE_PTYPE_INNER_L4_TCP,
        [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_TCP] =
                RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
                RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_INNER_L2_ETHER |
                RTE_PTYPE_INNER_L3_IPV4,
        [IXGBE_PACKET_TYPE_NVGRE_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
                RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4 |
                RTE_PTYPE_INNER_L4_UDP,
        [IXGBE_PACKET_TYPE_NVGRE_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
                RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6 |
                RTE_PTYPE_INNER_L4_UDP,
        [IXGBE_PACKET_TYPE_NVGRE_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
                RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6 |
                RTE_PTYPE_INNER_L4_SCTP,
        [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
                RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
        [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
                RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT |
                RTE_PTYPE_INNER_L4_UDP,
        [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
                RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT |
                RTE_PTYPE_INNER_L4_SCTP,
        [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_UDP] =
                RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
                RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_INNER_L2_ETHER |
                RTE_PTYPE_INNER_L3_IPV4,
        [IXGBE_PACKET_TYPE_NVGRE_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
                RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4 |
                RTE_PTYPE_INNER_L4_SCTP,
        [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
                RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT |
                RTE_PTYPE_INNER_L4_SCTP,
        [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_TCP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
                RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT |
                RTE_PTYPE_INNER_L4_TCP,
        [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_UDP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
                RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT |
                RTE_PTYPE_INNER_L4_UDP,

        [IXGBE_PACKET_TYPE_VXLAN] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
                RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER,
        [IXGBE_PACKET_TYPE_VXLAN_IPV4] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
                RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
                RTE_PTYPE_INNER_L3_IPV4,
        [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
                RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
                RTE_PTYPE_INNER_L3_IPV4_EXT,
        [IXGBE_PACKET_TYPE_VXLAN_IPV6] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
                RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
                RTE_PTYPE_INNER_L3_IPV6,
        [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
                RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
                RTE_PTYPE_INNER_L3_IPV4,
        [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
                RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
                RTE_PTYPE_INNER_L3_IPV6_EXT,
        [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
                RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
                RTE_PTYPE_INNER_L3_IPV4,
        [IXGBE_PACKET_TYPE_VXLAN_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
                RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
                RTE_PTYPE_INNER_L3_IPV4 | RTE_PTYPE_INNER_L4_TCP,
        [IXGBE_PACKET_TYPE_VXLAN_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
                RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
                RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
        [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
                RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
                RTE_PTYPE_INNER_L3_IPV4,
        [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
                RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
                RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
        [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_TCP] =
                RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
                RTE_PTYPE_L4_UDP | RTE_PTYPE_TUNNEL_VXLAN |
                RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
        [IXGBE_PACKET_TYPE_VXLAN_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
                RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
                RTE_PTYPE_INNER_L3_IPV4 | RTE_PTYPE_INNER_L4_UDP,
        [IXGBE_PACKET_TYPE_VXLAN_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
                RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
                RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
        [IXGBE_PACKET_TYPE_VXLAN_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
                RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
                RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_SCTP,
        [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
                RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
                RTE_PTYPE_INNER_L3_IPV4,
        [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
                RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
                RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
        [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
                RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
                RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_SCTP,
        [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_UDP] =
                RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
                RTE_PTYPE_L4_UDP | RTE_PTYPE_TUNNEL_VXLAN |
                RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
        [IXGBE_PACKET_TYPE_VXLAN_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
                RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
                RTE_PTYPE_INNER_L3_IPV4 | RTE_PTYPE_INNER_L4_SCTP,
        [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
                RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
                RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_SCTP,
        [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_TCP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
                RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
                RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_TCP,
        [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_UDP] = RTE_PTYPE_L2_ETHER |
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
                RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
                RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_UDP,
};

static int
ixgbe_monitor_callback(const uint64_t value,
                const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
{
        const uint64_t m = rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD);
        /*
         * we expect the DD bit to be set to 1 if this descriptor was already
         * written to.
         */
        return (value & m) == m ? -1 : 0;
}

int
ixgbe_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
{
        volatile union ixgbe_adv_rx_desc *rxdp;
        struct ixgbe_rx_queue *rxq = rx_queue;
        uint16_t desc;

        desc = rxq->rx_tail;
        rxdp = &rxq->rx_ring[desc];
        /* watch for changes in status bit */
        pmc->addr = &rxdp->wb.upper.status_error;

        /* comparison callback */
        pmc->fn = ixgbe_monitor_callback;

        /* the registers are 32-bit */
        pmc->size = sizeof(uint32_t);

        return 0;
}

/* @note: fix ixgbe_dev_supported_ptypes_get() if any change here. */
static inline uint32_t
ixgbe_rxd_pkt_info_to_pkt_type(uint32_t pkt_info, uint16_t ptype_mask)
{

        if (unlikely(pkt_info & IXGBE_RXDADV_PKTTYPE_ETQF))
                return RTE_PTYPE_UNKNOWN;

        pkt_info = (pkt_info >> IXGBE_PACKET_TYPE_SHIFT) & ptype_mask;

        /* For tunnel packet */
        if (pkt_info & IXGBE_PACKET_TYPE_TUNNEL_BIT) {
                /* Remove the tunnel bit to save the space. */
                pkt_info &= IXGBE_PACKET_TYPE_MASK_TUNNEL;
                return ptype_table_tn[pkt_info];
        }

        /**
         * For x550, if it's not tunnel,
         * tunnel type bit should be set to 0.
         * Reuse 82599's mask.
         */
        pkt_info &= IXGBE_PACKET_TYPE_MASK_82599;

        return ptype_table[pkt_info];
}

static inline uint64_t
ixgbe_rxd_pkt_info_to_pkt_flags(uint16_t pkt_info)
{
        static uint64_t ip_rss_types_map[16] __rte_cache_aligned = {
                0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
                0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
                PKT_RX_RSS_HASH, 0, 0, 0,
                0, 0, 0,  PKT_RX_FDIR,
        };
#ifdef RTE_LIBRTE_IEEE1588
        static uint64_t ip_pkt_etqf_map[8] = {
                0, 0, 0, PKT_RX_IEEE1588_PTP,
                0, 0, 0, 0,
        };

        if (likely(pkt_info & IXGBE_RXDADV_PKTTYPE_ETQF))
                return ip_pkt_etqf_map[(pkt_info >> 4) & 0X07] |
                                ip_rss_types_map[pkt_info & 0XF];
        else
                return ip_rss_types_map[pkt_info & 0XF];
#else
        return ip_rss_types_map[pkt_info & 0XF];
#endif
}

static inline uint64_t
rx_desc_status_to_pkt_flags(uint32_t rx_status, uint64_t vlan_flags)
{
        uint64_t pkt_flags;

        /*
         * Check if VLAN present only.
         * Do not check whether L3/L4 rx checksum done by NIC or not,
         * That can be found from rte_eth_rxmode.offloads flag
         */
        pkt_flags = (rx_status & IXGBE_RXD_STAT_VP) ?  vlan_flags : 0;

#ifdef RTE_LIBRTE_IEEE1588
        if (rx_status & IXGBE_RXD_STAT_TMST)
                pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
#endif
        return pkt_flags;
}

static inline uint64_t
rx_desc_error_to_pkt_flags(uint32_t rx_status, uint16_t pkt_info,
                           uint8_t rx_udp_csum_zero_err)
{
        uint64_t pkt_flags;

        /*
         * Bit 31: IPE, IPv4 checksum error
         * Bit 30: L4I, L4I integrity error
         */
        static uint64_t error_to_pkt_flags_map[4] = {
                PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD,
                PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD,
                PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD,
                PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
        };
        pkt_flags = error_to_pkt_flags_map[(rx_status >>
                IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];

        /* Mask out the bad UDP checksum error if the hardware has UDP zero
         * checksum error issue, so that the software application will then
         * have to recompute the checksum itself if needed.
         */
        if ((rx_status & IXGBE_RXDADV_ERR_TCPE) &&
            (pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
            rx_udp_csum_zero_err)
                pkt_flags &= ~PKT_RX_L4_CKSUM_BAD;

        if ((rx_status & IXGBE_RXD_STAT_OUTERIPCS) &&
            (rx_status & IXGBE_RXDADV_ERR_OUTERIPER)) {
                pkt_flags |= PKT_RX_OUTER_IP_CKSUM_BAD;
        }

#ifdef RTE_LIB_SECURITY
        if (rx_status & IXGBE_RXD_STAT_SECP) {
                pkt_flags |= PKT_RX_SEC_OFFLOAD;
                if (rx_status & IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG)
                        pkt_flags |= PKT_RX_SEC_OFFLOAD_FAILED;
        }
#endif

        return pkt_flags;
}

/*
 * LOOK_AHEAD defines how many desc statuses to check beyond the
 * current descriptor.
 * It must be a pound define for optimal performance.
 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
 * function only works with LOOK_AHEAD=8.
 */
#define LOOK_AHEAD 8
#if (LOOK_AHEAD != 8)
#error "PMD IXGBE: LOOK_AHEAD must be 8\n"
#endif
static inline int
ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)
{
        volatile union ixgbe_adv_rx_desc *rxdp;
        struct ixgbe_rx_entry *rxep;
        struct rte_mbuf *mb;
        uint16_t pkt_len;
        uint64_t pkt_flags;
        int nb_dd;
        uint32_t s[LOOK_AHEAD];
        uint32_t pkt_info[LOOK_AHEAD];
        int i, j, nb_rx = 0;
        uint32_t status;
        uint64_t vlan_flags = rxq->vlan_flags;

        /* get references to current descriptor and S/W ring entry */
        rxdp = &rxq->rx_ring[rxq->rx_tail];
        rxep = &rxq->sw_ring[rxq->rx_tail];

        status = rxdp->wb.upper.status_error;
        /* check to make sure there is at least 1 packet to receive */
        if (!(status & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
                return 0;

        /*
         * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
         * reference packets that are ready to be received.
         */
        for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
             i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD) {
                /* Read desc statuses backwards to avoid race condition */
                for (j = 0; j < LOOK_AHEAD; j++)
                        s[j] = rte_le_to_cpu_32(rxdp[j].wb.upper.status_error);

                rte_smp_rmb();

                /* Compute how many status bits were set */
                for (nb_dd = 0; nb_dd < LOOK_AHEAD &&
                                (s[nb_dd] & IXGBE_RXDADV_STAT_DD); nb_dd++)
                        ;

                for (j = 0; j < nb_dd; j++)
                        pkt_info[j] = rte_le_to_cpu_32(rxdp[j].wb.lower.
                                                       lo_dword.data);

                nb_rx += nb_dd;

                /* Translate descriptor info to mbuf format */
                for (j = 0; j < nb_dd; ++j) {
                        mb = rxep[j].mbuf;
                        pkt_len = rte_le_to_cpu_16(rxdp[j].wb.upper.length) -
                                  rxq->crc_len;
                        mb->data_len = pkt_len;
                        mb->pkt_len = pkt_len;
                        mb->vlan_tci = rte_le_to_cpu_16(rxdp[j].wb.upper.vlan);

                        /* convert descriptor fields to rte mbuf flags */
                        pkt_flags = rx_desc_status_to_pkt_flags(s[j],
                                vlan_flags);
                        pkt_flags |= rx_desc_error_to_pkt_flags(s[j],
                                        (uint16_t)pkt_info[j],
                                        rxq->rx_udp_csum_zero_err);
                        pkt_flags |= ixgbe_rxd_pkt_info_to_pkt_flags
                                        ((uint16_t)pkt_info[j]);
                        mb->ol_flags = pkt_flags;
                        mb->packet_type =
                                ixgbe_rxd_pkt_info_to_pkt_type
                                        (pkt_info[j], rxq->pkt_type_mask);

                        if (likely(pkt_flags & PKT_RX_RSS_HASH))
                                mb->hash.rss = rte_le_to_cpu_32(
                                    rxdp[j].wb.lower.hi_dword.rss);
                        else if (pkt_flags & PKT_RX_FDIR) {
                                mb->hash.fdir.hash = rte_le_to_cpu_16(
                                    rxdp[j].wb.lower.hi_dword.csum_ip.csum) &
                                    IXGBE_ATR_HASH_MASK;
                                mb->hash.fdir.id = rte_le_to_cpu_16(
                                    rxdp[j].wb.lower.hi_dword.csum_ip.ip_id);
                        }
                }

                /* Move mbuf pointers from the S/W ring to the stage */
                for (j = 0; j < LOOK_AHEAD; ++j) {
                        rxq->rx_stage[i + j] = rxep[j].mbuf;
                }

                /* stop if all requested packets could not be received */
                if (nb_dd != LOOK_AHEAD)
                        break;
        }

        /* clear software ring entries so we can cleanup correctly */
        for (i = 0; i < nb_rx; ++i) {
                rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
        }


        return nb_rx;
}

static inline int
ixgbe_rx_alloc_bufs(struct ixgbe_rx_queue *rxq, bool reset_mbuf)
{
        volatile union ixgbe_adv_rx_desc *rxdp;
        struct ixgbe_rx_entry *rxep;
        struct rte_mbuf *mb;
        uint16_t alloc_idx;
        __le64 dma_addr;
        int diag, i;

        /* allocate buffers in bulk directly into the S/W ring */
        alloc_idx = rxq->rx_free_trigger - (rxq->rx_free_thresh - 1);
        rxep = &rxq->sw_ring[alloc_idx];
        diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
                                    rxq->rx_free_thresh);
        if (unlikely(diag != 0))
                return -ENOMEM;

        rxdp = &rxq->rx_ring[alloc_idx];
        for (i = 0; i < rxq->rx_free_thresh; ++i) {
                /* populate the static rte mbuf fields */
                mb = rxep[i].mbuf;
                if (reset_mbuf) {
                        mb->port = rxq->port_id;
                }

                rte_mbuf_refcnt_set(mb, 1);
                mb->data_off = RTE_PKTMBUF_HEADROOM;

                /* populate the descriptors */
                dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
                rxdp[i].read.hdr_addr = 0;
                rxdp[i].read.pkt_addr = dma_addr;
        }

        /* update state of internal queue structure */
        rxq->rx_free_trigger = rxq->rx_free_trigger + rxq->rx_free_thresh;
        if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
                rxq->rx_free_trigger = rxq->rx_free_thresh - 1;

        /* no errors */
        return 0;
}

static inline uint16_t
ixgbe_rx_fill_from_stage(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
                         uint16_t nb_pkts)
{
        struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
        int i;

        /* how many packets are ready to return? */
        nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);

        /* copy mbuf pointers to the application's packet list */
        for (i = 0; i < nb_pkts; ++i)
                rx_pkts[i] = stage[i];

        /* update internal queue state */
        rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
        rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);

        return nb_pkts;
}

static inline uint16_t
rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
             uint16_t nb_pkts)
{
        struct ixgbe_rx_queue *rxq = (struct ixgbe_rx_queue *)rx_queue;
        uint16_t nb_rx = 0;

        /* Any previously recv'd pkts will be returned from the Rx stage */
        if (rxq->rx_nb_avail)
                return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);

        /* Scan the H/W ring for packets to receive */
        nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);

        /* update internal queue state */
        rxq->rx_next_avail = 0;
        rxq->rx_nb_avail = nb_rx;
        rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);

        /* if required, allocate new buffers to replenish descriptors */
        if (rxq->rx_tail > rxq->rx_free_trigger) {
                uint16_t cur_free_trigger = rxq->rx_free_trigger;

                if (ixgbe_rx_alloc_bufs(rxq, true) != 0) {
                        int i, j;

                        PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
                                   "queue_id=%u", (unsigned) rxq->port_id,
                                   (unsigned) rxq->queue_id);

                        rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
                                rxq->rx_free_thresh;

                        /*
                         * Need to rewind any previous receives if we cannot
                         * allocate new buffers to replenish the old ones.
                         */
                        rxq->rx_nb_avail = 0;
                        rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
                        for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
                                rxq->sw_ring[j].mbuf = rxq->rx_stage[i];

                        return 0;
                }

                /* update tail pointer */
                rte_wmb();
                IXGBE_PCI_REG_WC_WRITE_RELAXED(rxq->rdt_reg_addr,
                                            cur_free_trigger);
        }

        if (rxq->rx_tail >= rxq->nb_rx_desc)
                rxq->rx_tail = 0;

        /* received any packets this loop? */
        if (rxq->rx_nb_avail)
                return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);

        return 0;
}

/* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
uint16_t
ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
                           uint16_t nb_pkts)
{
        uint16_t nb_rx;

        if (unlikely(nb_pkts == 0))
                return 0;

        if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
                return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);

        /* request is relatively large, chunk it up */
        nb_rx = 0;
        while (nb_pkts) {
                uint16_t ret, n;

                n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
                ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
                nb_rx = (uint16_t)(nb_rx + ret);
                nb_pkts = (uint16_t)(nb_pkts - ret);
                if (ret < n)
                        break;
        }

        return nb_rx;
}

uint16_t
ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
                uint16_t nb_pkts)
{
        struct ixgbe_rx_queue *rxq;
        volatile union ixgbe_adv_rx_desc *rx_ring;
        volatile union ixgbe_adv_rx_desc *rxdp;
        struct ixgbe_rx_entry *sw_ring;
        struct ixgbe_rx_entry *rxe;
        struct rte_mbuf *rxm;
        struct rte_mbuf *nmb;
        union ixgbe_adv_rx_desc rxd;
        uint64_t dma_addr;
        uint32_t staterr;
        uint32_t pkt_info;
        uint16_t pkt_len;
        uint16_t rx_id;
        uint16_t nb_rx;
        uint16_t nb_hold;
        uint64_t pkt_flags;
        uint64_t vlan_flags;

        nb_rx = 0;
        nb_hold = 0;
        rxq = rx_queue;
        rx_id = rxq->rx_tail;
        rx_ring = rxq->rx_ring;
        sw_ring = rxq->sw_ring;
        vlan_flags = rxq->vlan_flags;
        while (nb_rx < nb_pkts) {
                /*
                 * The order of operations here is important as the DD status
                 * bit must not be read after any other descriptor fields.
                 * rx_ring and rxdp are pointing to volatile data so the order
                 * of accesses cannot be reordered by the compiler. If they were
                 * not volatile, they could be reordered which could lead to
                 * using invalid descriptor fields when read from rxd.
                 */
                rxdp = &rx_ring[rx_id];
                staterr = rxdp->wb.upper.status_error;
                if (!(staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
                        break;
                rxd = *rxdp;

                /*
                 * End of packet.
                 *
                 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
                 * is likely to be invalid and to be dropped by the various
                 * validation checks performed by the network stack.
                 *
                 * Allocate a new mbuf to replenish the RX ring descriptor.
                 * If the allocation fails:
                 *    - arrange for that RX descriptor to be the first one
                 *      being parsed the next time the receive function is
                 *      invoked [on the same queue].
                 *
                 *    - Stop parsing the RX ring and return immediately.
                 *
                 * This policy do not drop the packet received in the RX
                 * descriptor for which the allocation of a new mbuf failed.
                 * Thus, it allows that packet to be later retrieved if
                 * mbuf have been freed in the mean time.
                 * As a side effect, holding RX descriptors instead of
                 * systematically giving them back to the NIC may lead to
                 * RX ring exhaustion situations.
                 * However, the NIC can gracefully prevent such situations
                 * to happen by sending specific "back-pressure" flow control
                 * frames to its peer(s).
                 */
                PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
                           "ext_err_stat=0x%08x pkt_len=%u",
                           (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
                           (unsigned) rx_id, (unsigned) staterr,
                           (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));

                nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
                if (nmb == NULL) {
                        PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
                                   "queue_id=%u", (unsigned) rxq->port_id,
                                   (unsigned) rxq->queue_id);
                        rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
                        break;
                }

                nb_hold++;
                rxe = &sw_ring[rx_id];
                rx_id++;
                if (rx_id == rxq->nb_rx_desc)
                        rx_id = 0;

                /* Prefetch next mbuf while processing current one. */
                rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);

                /*
                 * When next RX descriptor is on a cache-line boundary,
                 * prefetch the next 4 RX descriptors and the next 8 pointers
                 * to mbufs.
                 */
                if ((rx_id & 0x3) == 0) {
                        rte_ixgbe_prefetch(&rx_ring[rx_id]);
                        rte_ixgbe_prefetch(&sw_ring[rx_id]);
                }

                rxm = rxe->mbuf;
                rxe->mbuf = nmb;
                dma_addr =
                        rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
                rxdp->read.hdr_addr = 0;
                rxdp->read.pkt_addr = dma_addr;

                /*
                 * Initialize the returned mbuf.
                 * 1) setup generic mbuf fields:
                 *    - number of segments,
                 *    - next segment,
                 *    - packet length,
                 *    - RX port identifier.
                 * 2) integrate hardware offload data, if any:
                 *    - RSS flag & hash,
                 *    - IP checksum flag,
                 *    - VLAN TCI, if any,
                 *    - error flags.
                 */
                pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
                                      rxq->crc_len);
                rxm->data_off = RTE_PKTMBUF_HEADROOM;
                rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
                rxm->nb_segs = 1;
                rxm->next = NULL;
                rxm->pkt_len = pkt_len;
                rxm->data_len = pkt_len;
                rxm->port = rxq->port_id;

                pkt_info = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
                /* Only valid if PKT_RX_VLAN set in pkt_flags */
                rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);

                pkt_flags = rx_desc_status_to_pkt_flags(staterr, vlan_flags);
                pkt_flags = pkt_flags |
                        rx_desc_error_to_pkt_flags(staterr, (uint16_t)pkt_info,
                                                   rxq->rx_udp_csum_zero_err);
                pkt_flags = pkt_flags |
                        ixgbe_rxd_pkt_info_to_pkt_flags((uint16_t)pkt_info);
                rxm->ol_flags = pkt_flags;
                rxm->packet_type =
                        ixgbe_rxd_pkt_info_to_pkt_type(pkt_info,
                                                       rxq->pkt_type_mask);

                if (likely(pkt_flags & PKT_RX_RSS_HASH))
                        rxm->hash.rss = rte_le_to_cpu_32(
                                                rxd.wb.lower.hi_dword.rss);
                else if (pkt_flags & PKT_RX_FDIR) {
                        rxm->hash.fdir.hash = rte_le_to_cpu_16(
                                        rxd.wb.lower.hi_dword.csum_ip.csum) &
                                        IXGBE_ATR_HASH_MASK;
                        rxm->hash.fdir.id = rte_le_to_cpu_16(
                                        rxd.wb.lower.hi_dword.csum_ip.ip_id);
                }
                /*
                 * Store the mbuf address into the next entry of the array
                 * of returned packets.
                 */
                rx_pkts[nb_rx++] = rxm;
        }
        rxq->rx_tail = rx_id;

        /*
         * If the number of free RX descriptors is greater than the RX free
         * threshold of the queue, advance the Receive Descriptor Tail (RDT)
         * register.
         * Update the RDT with the value of the last processed RX descriptor
         * minus 1, to guarantee that the RDT register is never equal to the
         * RDH register, which creates a "full" ring situtation from the
         * hardware point of view...
         */
        nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
        if (nb_hold > rxq->rx_free_thresh) {
                PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
                           "nb_hold=%u nb_rx=%u",
                           (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
                           (unsigned) rx_id, (unsigned) nb_hold,
                           (unsigned) nb_rx);
                rx_id = (uint16_t) ((rx_id == 0) ?
                                     (rxq->nb_rx_desc - 1) : (rx_id - 1));
                IXGBE_PCI_REG_WC_WRITE(rxq->rdt_reg_addr, rx_id);
                nb_hold = 0;
        }
        rxq->nb_rx_hold = nb_hold;
        return nb_rx;
}

/**
 * Detect an RSC descriptor.
 */
static inline uint32_t
ixgbe_rsc_count(union ixgbe_adv_rx_desc *rx)
{
        return (rte_le_to_cpu_32(rx->wb.lower.lo_dword.data) &
                IXGBE_RXDADV_RSCCNT_MASK) >> IXGBE_RXDADV_RSCCNT_SHIFT;
}

/**
 * ixgbe_fill_cluster_head_buf - fill the first mbuf of the returned packet
 *
 * Fill the following info in the HEAD buffer of the Rx cluster:
 *    - RX port identifier
 *    - hardware offload data, if any:
 *      - RSS flag & hash
 *      - IP checksum flag
 *      - VLAN TCI, if any
 *      - error flags
 * @head HEAD of the packet cluster
 * @desc HW descriptor to get data from
 * @rxq Pointer to the Rx queue

 */
static inline void
ixgbe_fill_cluster_head_buf(
        struct rte_mbuf *head,
        union ixgbe_adv_rx_desc *desc,
        struct ixgbe_rx_queue *rxq,
        uint32_t staterr)
{
        uint32_t pkt_info;
        uint64_t pkt_flags;

        head->port = rxq->port_id;

        /* The vlan_tci field is only valid when PKT_RX_VLAN is
         * set in the pkt_flags field.
         */
        head->vlan_tci = rte_le_to_cpu_16(desc->wb.upper.vlan);
        pkt_info = rte_le_to_cpu_32(desc->wb.lower.lo_dword.data);
        pkt_flags = rx_desc_status_to_pkt_flags(staterr, rxq->vlan_flags);
        pkt_flags |= rx_desc_error_to_pkt_flags(staterr, (uint16_t)pkt_info,
                                                rxq->rx_udp_csum_zero_err);
        pkt_flags |= ixgbe_rxd_pkt_info_to_pkt_flags((uint16_t)pkt_info);
        head->ol_flags = pkt_flags;
        head->packet_type =
                ixgbe_rxd_pkt_info_to_pkt_type(pkt_info, rxq->pkt_type_mask);

        if (likely(pkt_flags & PKT_RX_RSS_HASH))
                head->hash.rss = rte_le_to_cpu_32(desc->wb.lower.hi_dword.rss);
        else if (pkt_flags & PKT_RX_FDIR) {
                head->hash.fdir.hash =
                        rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.csum)
                                                          & IXGBE_ATR_HASH_MASK;
                head->hash.fdir.id =
                        rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.ip_id);
        }
}

/**
 * ixgbe_recv_pkts_lro - receive handler for and LRO case.
 *
 * @rx_queue Rx queue handle
 * @rx_pkts table of received packets
 * @nb_pkts size of rx_pkts table
 * @bulk_alloc if TRUE bulk allocation is used for a HW ring refilling
 *
 * Handles the Rx HW ring completions when RSC feature is configured. Uses an
 * additional ring of ixgbe_rsc_entry's that will hold the relevant RSC info.
 *
 * We use the same logic as in Linux and in FreeBSD ixgbe drivers:
 * 1) When non-EOP RSC completion arrives:
 *    a) Update the HEAD of the current RSC aggregation cluster with the new
 *       segment's data length.
 *    b) Set the "next" pointer of the current segment to point to the segment
 *       at the NEXTP index.
 *    c) Pass the HEAD of RSC aggregation cluster on to the next NEXTP entry
 *       in the sw_rsc_ring.
 * 2) When EOP arrives we just update the cluster's total length and offload
 *    flags and deliver the cluster up to the upper layers. In our case - put it
 *    in the rx_pkts table.
 *
 * Returns the number of received packets/clusters (according to the "bulk
 * receive" interface).
 */
static inline uint16_t
ixgbe_recv_pkts_lro(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts,
                    bool bulk_alloc)
{
        struct ixgbe_rx_queue *rxq = rx_queue;
        volatile union ixgbe_adv_rx_desc *rx_ring = rxq->rx_ring;
        struct ixgbe_rx_entry *sw_ring = rxq->sw_ring;
        struct ixgbe_scattered_rx_entry *sw_sc_ring = rxq->sw_sc_ring;
        uint16_t rx_id = rxq->rx_tail;
        uint16_t nb_rx = 0;
        uint16_t nb_hold = rxq->nb_rx_hold;
        uint16_t prev_id = rxq->rx_tail;

        while (nb_rx < nb_pkts) {
                bool eop;
                struct ixgbe_rx_entry *rxe;
                struct ixgbe_scattered_rx_entry *sc_entry;
                struct ixgbe_scattered_rx_entry *next_sc_entry = NULL;
                struct ixgbe_rx_entry *next_rxe = NULL;
                struct rte_mbuf *first_seg;
                struct rte_mbuf *rxm;
                struct rte_mbuf *nmb = NULL;
                union ixgbe_adv_rx_desc rxd;
                uint16_t data_len;
                uint16_t next_id;
                volatile union ixgbe_adv_rx_desc *rxdp;
                uint32_t staterr;

next_desc:
                /*
                 * The code in this whole file uses the volatile pointer to
                 * ensure the read ordering of the status and the rest of the
                 * descriptor fields (on the compiler level only!!!). This is so
                 * UGLY - why not to just use the compiler barrier instead? DPDK
                 * even has the rte_compiler_barrier() for that.
                 *
                 * But most importantly this is just wrong because this doesn't
                 * ensure memory ordering in a general case at all. For
                 * instance, DPDK is supposed to work on Power CPUs where
                 * compiler barrier may just not be enough!
                 *
                 * I tried to write only this function properly to have a
                 * starting point (as a part of an LRO/RSC series) but the
                 * compiler cursed at me when I tried to cast away the
                 * "volatile" from rx_ring (yes, it's volatile too!!!). So, I'm
                 * keeping it the way it is for now.
                 *
                 * The code in this file is broken in so many other places and
                 * will just not work on a big endian CPU anyway therefore the
                 * lines below will have to be revisited together with the rest
                 * of the ixgbe PMD.
                 *
                 * TODO:
                 *    - Get rid of "volatile" and let the compiler do its job.
                 *    - Use the proper memory barrier (rte_rmb()) to ensure the
                 *      memory ordering below.
                 */
                rxdp = &rx_ring[rx_id];
                staterr = rte_le_to_cpu_32(rxdp->wb.upper.status_error);

                if (!(staterr & IXGBE_RXDADV_STAT_DD))
                        break;

                rxd = *rxdp;

                PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
                                  "staterr=0x%x data_len=%u",
                           rxq->port_id, rxq->queue_id, rx_id, staterr,
                           rte_le_to_cpu_16(rxd.wb.upper.length));

                if (!bulk_alloc) {
                        nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
                        if (nmb == NULL) {
                                PMD_RX_LOG(DEBUG, "RX mbuf alloc failed "
                                                  "port_id=%u queue_id=%u",
                                           rxq->port_id, rxq->queue_id);

                                rte_eth_devices[rxq->port_id].data->
                                                        rx_mbuf_alloc_failed++;
                                break;
                        }
                } else if (nb_hold > rxq->rx_free_thresh) {
                        uint16_t next_rdt = rxq->rx_free_trigger;

                        if (!ixgbe_rx_alloc_bufs(rxq, false)) {
                                rte_wmb();
                                IXGBE_PCI_REG_WC_WRITE_RELAXED(
                                                        rxq->rdt_reg_addr,
                                                        next_rdt);
                                nb_hold -= rxq->rx_free_thresh;
                        } else {
                                PMD_RX_LOG(DEBUG, "RX bulk alloc failed "
                                                  "port_id=%u queue_id=%u",
                                           rxq->port_id, rxq->queue_id);

                                rte_eth_devices[rxq->port_id].data->
                                                        rx_mbuf_alloc_failed++;
                                break;
                        }
                }

                nb_hold++;
                rxe = &sw_ring[rx_id];
                eop = staterr & IXGBE_RXDADV_STAT_EOP;

                next_id = rx_id + 1;
                if (next_id == rxq->nb_rx_desc)
                        next_id = 0;

                /* Prefetch next mbuf while processing current one. */
                rte_ixgbe_prefetch(sw_ring[next_id].mbuf);

                /*
                 * When next RX descriptor is on a cache-line boundary,
                 * prefetch the next 4 RX descriptors and the next 4 pointers
                 * to mbufs.
                 */
                if ((next_id & 0x3) == 0) {
                        rte_ixgbe_prefetch(&rx_ring[next_id]);
                        rte_ixgbe_prefetch(&sw_ring[next_id]);
                }

                rxm = rxe->mbuf;

                if (!bulk_alloc) {
                        __le64 dma =
                          rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
                        /*
                         * Update RX descriptor with the physical address of the
                         * new data buffer of the new allocated mbuf.
                         */
                        rxe->mbuf = nmb;

                        rxm->data_off = RTE_PKTMBUF_HEADROOM;
                        rxdp->read.hdr_addr = 0;
                        rxdp->read.pkt_addr = dma;
                } else
                        rxe->mbuf = NULL;

                /*
                 * Set data length & data buffer address of mbuf.
                 */
                data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
                rxm->data_len = data_len;

                if (!eop) {
                        uint16_t nextp_id;
                        /*
                         * Get next descriptor index:
                         *  - For RSC it's in the NEXTP field.
                         *  - For a scattered packet - it's just a following
                         *    descriptor.
                         */
                        if (ixgbe_rsc_count(&rxd))
                                nextp_id =
                                        (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
                                                       IXGBE_RXDADV_NEXTP_SHIFT;
                        else
                                nextp_id = next_id;

                        next_sc_entry = &sw_sc_ring[nextp_id];
                        next_rxe = &sw_ring[nextp_id];
                        rte_ixgbe_prefetch(next_rxe);
                }

                sc_entry = &sw_sc_ring[rx_id];
                first_seg = sc_entry->fbuf;
                sc_entry->fbuf = NULL;

                /*
                 * If this is the first buffer of the received packet,
                 * set the pointer to the first mbuf of the packet and
                 * initialize its context.
                 * Otherwise, update the total length and the number of segments
                 * of the current scattered packet, and update the pointer to
                 * the last mbuf of the current packet.
                 */
                if (first_seg == NULL) {
                        first_seg = rxm;
                        first_seg->pkt_len = data_len;
                        first_seg->nb_segs = 1;
                } else {
                        first_seg->pkt_len += data_len;
                        first_seg->nb_segs++;
                }

                prev_id = rx_id;
                rx_id = next_id;

                /*
                 * If this is not the last buffer of the received packet, update
                 * the pointer to the first mbuf at the NEXTP entry in the
                 * sw_sc_ring and continue to parse the RX ring.
                 */
                if (!eop && next_rxe) {
                        rxm->next = next_rxe->mbuf;
                        next_sc_entry->fbuf = first_seg;
                        goto next_desc;
                }

                /* Initialize the first mbuf of the returned packet */
                ixgbe_fill_cluster_head_buf(first_seg, &rxd, rxq, staterr);

                /*
                 * Deal with the case, when HW CRC srip is disabled.
                 * That can't happen when LRO is enabled, but still could
                 * happen for scattered RX mode.
                 */
                first_seg->pkt_len -= rxq->crc_len;
                if (unlikely(rxm->data_len <= rxq->crc_len)) {
                        struct rte_mbuf *lp;

                        for (lp = first_seg; lp->next != rxm; lp = lp->next)
                                ;

                        first_seg->nb_segs--;
                        lp->data_len -= rxq->crc_len - rxm->data_len;
                        lp->next = NULL;
                        rte_pktmbuf_free_seg(rxm);
                } else
                        rxm->data_len -= rxq->crc_len;

                /* Prefetch data of first segment, if configured to do so. */
                rte_packet_prefetch((char *)first_seg->buf_addr +
                        first_seg->data_off);

                /*
                 * Store the mbuf address into the next entry of the array
                 * of returned packets.
                 */
                rx_pkts[nb_rx++] = first_seg;
        }

        /*
         * Record index of the next RX descriptor to probe.
         */
        rxq->rx_tail = rx_id;

        /*
         * If the number of free RX descriptors is greater than the RX free
         * threshold of the queue, advance the Receive Descriptor Tail (RDT)
         * register.
         * Update the RDT with the value of the last processed RX descriptor
         * minus 1, to guarantee that the RDT register is never equal to the
         * RDH register, which creates a "full" ring situtation from the
         * hardware point of view...
         */
        if (!bulk_alloc && nb_hold > rxq->rx_free_thresh) {
                PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
                           "nb_hold=%u nb_rx=%u",
                           rxq->port_id, rxq->queue_id, rx_id, nb_hold, nb_rx);

                rte_wmb();
                IXGBE_PCI_REG_WC_WRITE_RELAXED(rxq->rdt_reg_addr, prev_id);
                nb_hold = 0;
        }

        rxq->nb_rx_hold = nb_hold;
        return nb_rx;
}

uint16_t
ixgbe_recv_pkts_lro_single_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
                                 uint16_t nb_pkts)
{
        return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, false);
}

uint16_t
ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
                               uint16_t nb_pkts)
{
        return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, true);
}

/*********************************************************************
 *
 *  Queue management functions
 *
 **********************************************************************/

static void __rte_cold
ixgbe_tx_queue_release_mbufs(struct ixgbe_tx_queue *txq)
{
        unsigned i;

        if (txq->sw_ring != NULL) {
                for (i = 0; i < txq->nb_tx_desc; i++) {
                        if (txq->sw_ring[i].mbuf != NULL) {
                                rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
                                txq->sw_ring[i].mbuf = NULL;
                        }
                }
        }
}

static int
ixgbe_tx_done_cleanup_full(struct ixgbe_tx_queue *txq, uint32_t free_cnt)
{
        struct ixgbe_tx_entry *swr_ring = txq->sw_ring;
        uint16_t i, tx_last, tx_id;
        uint16_t nb_tx_free_last;
        uint16_t nb_tx_to_clean;
        uint32_t pkt_cnt;

        /* Start free mbuf from the next of tx_tail */
        tx_last = txq->tx_tail;
        tx_id  = swr_ring[tx_last].next_id;

        if (txq->nb_tx_free == 0 && ixgbe_xmit_cleanup(txq))
                return 0;

        nb_tx_to_clean = txq->nb_tx_free;
        nb_tx_free_last = txq->nb_tx_free;
        if (!free_cnt)
                free_cnt = txq->nb_tx_desc;

        /* Loop through swr_ring to count the amount of
         * freeable mubfs and packets.
         */
        for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
                for (i = 0; i < nb_tx_to_clean &&
                        pkt_cnt < free_cnt &&
                        tx_id != tx_last; i++) {
                        if (swr_ring[tx_id].mbuf != NULL) {
                                rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
                                swr_ring[tx_id].mbuf = NULL;

                                /*
                                 * last segment in the packet,
                                 * increment packet count
                                 */
                                pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
                        }

                        tx_id = swr_ring[tx_id].next_id;
                }

                if (txq->tx_rs_thresh > txq->nb_tx_desc -
                        txq->nb_tx_free || tx_id == tx_last)
                        break;

                if (pkt_cnt < free_cnt) {
                        if (ixgbe_xmit_cleanup(txq))
                                break;

                        nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
                        nb_tx_free_last = txq->nb_tx_free;
                }
        }

        return (int)pkt_cnt;
}

static int
ixgbe_tx_done_cleanup_simple(struct ixgbe_tx_queue *txq,
                        uint32_t free_cnt)
{
        int i, n, cnt;

        if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
                free_cnt = txq->nb_tx_desc;

        cnt = free_cnt - free_cnt % txq->tx_rs_thresh;

        for (i = 0; i < cnt; i += n) {
                if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
                        break;

                n = ixgbe_tx_free_bufs(txq);

                if (n == 0)
                        break;
        }

        return i;
}

static int
ixgbe_tx_done_cleanup_vec(struct ixgbe_tx_queue *txq __rte_unused,
                        uint32_t free_cnt __rte_unused)
{
        return -ENOTSUP;
}

int
ixgbe_dev_tx_done_cleanup(void *tx_queue, uint32_t free_cnt)
{
        struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
        if (txq->offloads == 0 &&
#ifdef RTE_LIB_SECURITY
                        !(txq->using_ipsec) &&
#endif
                        txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST) {
                if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
                                rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128 &&
                                (rte_eal_process_type() != RTE_PROC_PRIMARY ||
                                        txq->sw_ring_v != NULL)) {
                        return ixgbe_tx_done_cleanup_vec(txq, free_cnt);
                } else {
                        return ixgbe_tx_done_cleanup_simple(txq, free_cnt);
                }
        }

        return ixgbe_tx_done_cleanup_full(txq, free_cnt);
}

static void __rte_cold
ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
{
        if (txq != NULL &&
            txq->sw_ring != NULL)
                rte_free(txq->sw_ring);
}

static void __rte_cold
ixgbe_tx_queue_release(struct ixgbe_tx_queue *txq)
{
        if (txq != NULL && txq->ops != NULL) {
                txq->ops->release_mbufs(txq);
                txq->ops->free_swring(txq);
                rte_free(txq);
        }
}

void __rte_cold
ixgbe_dev_tx_queue_release(void *txq)
{
        ixgbe_tx_queue_release(txq);
}

/* (Re)set dynamic ixgbe_tx_queue fields to defaults */
static void __rte_cold
ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
{
        static const union ixgbe_adv_tx_desc zeroed_desc = {{0}};
        struct ixgbe_tx_entry *txe = txq->sw_ring;
        uint16_t prev, i;

        /* Zero out HW ring memory */
        for (i = 0; i < txq->nb_tx_desc; i++) {
                txq->tx_ring[i] = zeroed_desc;
        }

        /* Initialize SW ring entries */
        prev = (uint16_t) (txq->nb_tx_desc - 1);
        for (i = 0; i < txq->nb_tx_desc; i++) {
                volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];

                txd->wb.status = rte_cpu_to_le_32(IXGBE_TXD_STAT_DD);
                txe[i].mbuf = NULL;
                txe[i].last_id = i;
                txe[prev].next_id = i;
                prev = i;
        }

        txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
        txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);

        txq->tx_tail = 0;
        txq->nb_tx_used = 0;
        /*
         * Always allow 1 descriptor to be un-allocated to avoid
         * a H/W race condition
         */
        txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
        txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
        txq->ctx_curr = 0;
        memset((void *)&txq->ctx_cache, 0,
                IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
}

static const struct ixgbe_txq_ops def_txq_ops = {
        .release_mbufs = ixgbe_tx_queue_release_mbufs,
        .free_swring = ixgbe_tx_free_swring,
        .reset = ixgbe_reset_tx_queue,
};

/* Takes an ethdev and a queue and sets up the tx function to be used based on
 * the queue parameters. Used in tx_queue_setup by primary process and then
 * in dev_init by secondary process when attaching to an existing ethdev.
 */
void __rte_cold
ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq)
{
        /* Use a simple Tx queue (no offloads, no multi segs) if possible */
        if ((txq->offloads == 0) &&
#ifdef RTE_LIB_SECURITY
                        !(txq->using_ipsec) &&
#endif
                        (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
                PMD_INIT_LOG(DEBUG, "Using simple tx code path");
                dev->tx_pkt_prepare = NULL;
                if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
                                rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128 &&
                                (rte_eal_process_type() != RTE_PROC_PRIMARY ||
                                        ixgbe_txq_vec_setup(txq) == 0)) {
                        PMD_INIT_LOG(DEBUG, "Vector tx enabled.");
                        dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
                } else
                dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
        } else {
                PMD_INIT_LOG(DEBUG, "Using full-featured tx code path");
                PMD_INIT_LOG(DEBUG,
                                " - offloads = 0x%" PRIx64,
                                txq->offloads);
                PMD_INIT_LOG(DEBUG,
                                " - tx_rs_thresh = %lu " "[RTE_PMD_IXGBE_TX_MAX_BURST=%lu]",
                                (unsigned long)txq->tx_rs_thresh,
                                (unsigned long)RTE_PMD_IXGBE_TX_MAX_BURST);
                dev->tx_pkt_burst = ixgbe_xmit_pkts;
                dev->tx_pkt_prepare = ixgbe_prep_pkts;
        }
}

uint64_t
ixgbe_get_tx_queue_offloads(struct rte_eth_dev *dev)
{
        RTE_SET_USED(dev);

        return 0;
}

uint64_t
ixgbe_get_tx_port_offloads(struct rte_eth_dev *dev)
{
        uint64_t tx_offload_capa;
        struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);

        tx_offload_capa =
                DEV_TX_OFFLOAD_VLAN_INSERT |
                DEV_TX_OFFLOAD_IPV4_CKSUM  |
                DEV_TX_OFFLOAD_UDP_CKSUM   |
                DEV_TX_OFFLOAD_TCP_CKSUM   |
                DEV_TX_OFFLOAD_SCTP_CKSUM  |
                DEV_TX_OFFLOAD_TCP_TSO     |
                DEV_TX_OFFLOAD_MULTI_SEGS;

        if (hw->mac.type == ixgbe_mac_82599EB ||
            hw->mac.type == ixgbe_mac_X540)
                tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;

        if (hw->mac.type == ixgbe_mac_X550 ||
            hw->mac.type == ixgbe_mac_X550EM_x ||
            hw->mac.type == ixgbe_mac_X550EM_a)
                tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;

#ifdef RTE_LIB_SECURITY
        if (dev->security_ctx)
                tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
#endif
        return tx_offload_capa;
}

int __rte_cold
ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
                         uint16_t queue_idx,
                         uint16_t nb_desc,
                         unsigned int socket_id,
                         const struct rte_eth_txconf *tx_conf)
{
        const struct rte_memzone *tz;
        struct ixgbe_tx_queue *txq;
        struct ixgbe_hw     *hw;
        uint16_t tx_rs_thresh, tx_free_thresh;
        uint64_t offloads;

        PMD_INIT_FUNC_TRACE();
        hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);

        offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;

        /*
         * Validate number of transmit descriptors.
         * It must not exceed hardware maximum, and must be multiple
         * of IXGBE_ALIGN.
         */
        if (nb_desc % IXGBE_TXD_ALIGN != 0 ||
                        (nb_desc > IXGBE_MAX_RING_DESC) ||
                        (nb_desc < IXGBE_MIN_RING_DESC)) {
                return -EINVAL;
        }

        /*
         * The following two parameters control the setting of the RS bit on
         * transmit descriptors.
         * TX descriptors will have their RS bit set after txq->tx_rs_thresh
         * descriptors have been used.
         * The TX descriptor ring will be cleaned after txq->tx_free_thresh
         * descriptors are used or if the number of descriptors required
         * to transmit a packet is greater than the number of free TX
         * descriptors.
         * The following constraints must be satisfied:
         *  tx_rs_thresh must be greater than 0.
         *  tx_rs_thresh must be less than the size of the ring minus 2.
         *  tx_rs_thresh must be less than or equal to tx_free_thresh.
         *  tx_rs_thresh must be a divisor of the ring size.
         *  tx_free_thresh must be greater than 0.
         *  tx_free_thresh must be less than the size of the ring minus 3.
         *  tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
         * One descriptor in the TX ring is used as a sentinel to avoid a
         * H/W race condition, hence the maximum threshold constraints.
         * When set to zero use default values.
         */
        tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
                        tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
        /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
        tx_rs_thresh = (DEFAULT_TX_RS_THRESH + tx_free_thresh > nb_desc) ?
                        nb_desc - tx_free_thresh : DEFAULT_TX_RS_THRESH;
        if (tx_conf->tx_rs_thresh > 0)
                tx_rs_thresh = tx_conf->tx_rs_thresh;
        if (tx_rs_thresh + tx_free_thresh > nb_desc) {
                PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
                             "exceed nb_desc. (tx_rs_thresh=%u "
                             "tx_free_thresh=%u nb_desc=%u port = %d queue=%d)",
                             (unsigned int)tx_rs_thresh,
                             (unsigned int)tx_free_thresh,
                             (unsigned int)nb_desc,
                             (int)dev->data->port_id,
                             (int)queue_idx);
                return -(EINVAL);
        }
        if (tx_rs_thresh >= (nb_desc - 2)) {
                PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the number "
                        "of TX descriptors minus 2. (tx_rs_thresh=%u "
                        "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
                        (int)dev->data->port_id, (int)queue_idx);
                return -(EINVAL);
        }
        if (tx_rs_thresh > DEFAULT_TX_RS_THRESH) {
                PMD_INIT_LOG(ERR, "tx_rs_thresh must be less or equal than %u. "
                        "(tx_rs_thresh=%u port=%d queue=%d)",
                        DEFAULT_TX_RS_THRESH, (unsigned int)tx_rs_thresh,
                        (int)dev->data->port_id, (int)queue_idx);
                return -(EINVAL);
        }
        if (tx_free_thresh >= (nb_desc - 3)) {
                PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
                             "tx_free_thresh must be less than the number of "
                             "TX descriptors minus 3. (tx_free_thresh=%u "
                             "port=%d queue=%d)",
                             (unsigned int)tx_free_thresh,
                             (int)dev->data->port_id, (int)queue_idx);
                return -(EINVAL);
        }
        if (tx_rs_thresh > tx_free_thresh) {
                PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
                             "tx_free_thresh. (tx_free_thresh=%u "
                             "tx_rs_thresh=%u port=%d queue=%d)",
                             (unsigned int)tx_free_thresh,
                             (unsigned int)tx_rs_thresh,
                             (int)dev->data->port_id,
                             (int)queue_idx);
                return -(EINVAL);
        }
        if ((nb_desc % tx_rs_thresh) != 0) {
                PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
                             "number of TX descriptors. (tx_rs_thresh=%u "
                             "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
                             (int)dev->data->port_id, (int)queue_idx);
                return -(EINVAL);
        }

        /*
         * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
         * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
         * by the NIC and all descriptors are written back after the NIC
         * accumulates WTHRESH descriptors.
         */
        if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
                PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
                             "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
                             "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
                             (int)dev->data->port_id, (int)queue_idx);
                return -(EINVAL);
        }

        /* Free memory prior to re-allocation if needed... */
        if (dev->data->tx_queues[queue_idx] != NULL) {
                ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
                dev->data->tx_queues[queue_idx] = NULL;
        }

        /* First allocate the tx queue data structure */
        txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct ixgbe_tx_queue),
                                 RTE_CACHE_LINE_SIZE, socket_id);
        if (txq == NULL)
                return -ENOMEM;

        /*
         * Allocate TX ring hardware descriptors. A memzone large enough to
         * handle the maximum ring size is allocated in order to allow for
         * resizing in later calls to the queue setup function.
         */
        tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
                        sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
                        IXGBE_ALIGN, socket_id);
        if (tz == NULL) {
                ixgbe_tx_queue_release(txq);
                return -ENOMEM;
        }

        txq->nb_tx_desc = nb_desc;
        txq->tx_rs_thresh = tx_rs_thresh;
        txq->tx_free_thresh = tx_free_thresh;
        txq->pthresh = tx_conf->tx_thresh.pthresh;
        txq->hthresh = tx_conf->tx_thresh.hthresh;
        txq->wthresh = tx_conf->tx_thresh.wthresh;
        txq->queue_id = queue_idx;
        txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
                queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
        txq->port_id = dev->data->port_id;
        txq->offloads = offloads;
        txq->ops = &def_txq_ops;
        txq->tx_deferred_start = tx_conf->tx_deferred_start;
#ifdef RTE_LIB_SECURITY
        txq->using_ipsec = !!(dev->data->dev_conf.txmode.offloads &
                        DEV_TX_OFFLOAD_SECURITY);
#endif

        /*
         * Modification to set VFTDT for virtual function if vf is detected
         */
        if (hw->mac.type == ixgbe_mac_82599_vf ||
            hw->mac.type == ixgbe_mac_X540_vf ||
            hw->mac.type == ixgbe_mac_X550_vf ||
            hw->mac.type == ixgbe_mac_X550EM_x_vf ||
            hw->mac.type == ixgbe_mac_X550EM_a_vf)
                txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
        else
                txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));

        txq->tx_ring_phys_addr = tz->iova;
        txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;

        /* Allocate software ring */
        txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
                                sizeof(struct ixgbe_tx_entry) * nb_desc,
                                RTE_CACHE_LINE_SIZE, socket_id);
        if (txq->sw_ring == NULL) {
                ixgbe_tx_queue_release(txq);
                return -ENOMEM;
        }
        PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
                     txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);

        /* set up vector or scalar TX function as appropriate */
        ixgbe_set_tx_function(dev, txq);

        txq->ops->reset(txq);

        dev->data->tx_queues[queue_idx] = txq;


        return 0;
}

/**
 * ixgbe_free_sc_cluster - free the not-yet-completed scattered cluster
 *
 * The "next" pointer of the last segment of (not-yet-completed) RSC clusters
 * in the sw_rsc_ring is not set to NULL but rather points to the next
 * mbuf of this RSC aggregation (that has not been completed yet and still
 * resides on the HW ring). So, instead of calling for rte_pktmbuf_free() we
 * will just free first "nb_segs" segments of the cluster explicitly by calling
 * an rte_pktmbuf_free_seg().
 *
 * @m scattered cluster head
 */
static void __rte_cold
ixgbe_free_sc_cluster(struct rte_mbuf *m)
{
        uint16_t i, nb_segs = m->nb_segs;
        struct rte_mbuf *next_seg;

        for (i = 0; i < nb_segs; i++) {
                next_seg = m->next;
                rte_pktmbuf_free_seg(m);
                m = next_seg;
        }
}

static void __rte_cold
ixgbe_rx_queue_release_mbufs(struct ixgbe_rx_queue *rxq)
{
        unsigned i;

        /* SSE Vector driver has a different way of releasing mbufs. */
        if (rxq->rx_using_sse) {
                ixgbe_rx_queue_release_mbufs_vec(rxq);
                return;
        }

        if (rxq->sw_ring != NULL) {
                for (i = 0; i < rxq->nb_rx_desc; i++) {
                        if (rxq->sw_ring[i].mbuf != NULL) {
                                rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
                                rxq->sw_ring[i].mbuf = NULL;
                        }
                }
                if (rxq->rx_nb_avail) {
                        for (i = 0; i < rxq->rx_nb_avail; ++i) {
                                struct rte_mbuf *mb;

                                mb = rxq->rx_stage[rxq->rx_next_avail + i];
                                rte_pktmbuf_free_seg(mb);
                        }
                        rxq->rx_nb_avail = 0;
                }
        }

        if (rxq->sw_sc_ring)
                for (i = 0; i < rxq->nb_rx_desc; i++)
                        if (rxq->sw_sc_ring[i].fbuf) {
                                ixgbe_free_sc_cluster(rxq->sw_sc_ring[i].fbuf);
                                rxq->sw_sc_ring[i].fbuf = NULL;
                        }
}

static void __rte_cold
ixgbe_rx_queue_release(struct ixgbe_rx_queue *rxq)
{
        if (rxq != NULL) {
                ixgbe_rx_queue_release_mbufs(rxq);
                rte_free(rxq->sw_ring);
                rte_free(rxq->sw_sc_ring);
                rte_free(rxq);
        }
}

void __rte_cold
ixgbe_dev_rx_queue_release(void *rxq)
{
        ixgbe_rx_queue_release(rxq);
}

/*
 * Check if Rx Burst Bulk Alloc function can be used.
 * Return
 *        0: the preconditions are satisfied and the bulk allocation function
 *           can be used.
 *  -EINVAL: the preconditions are NOT satisfied and the default Rx burst
 *           function must be used.
 */
static inline int __rte_cold
check_rx_burst_bulk_alloc_preconditions(struct ixgbe_rx_queue *rxq)
{
        int ret = 0;

        /*
         * Make sure the following pre-conditions are satisfied:
         *   rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
         *   rxq->rx_free_thresh < rxq->nb_rx_desc
         *   (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
         * Scattered packets are not supported.  This should be checked
         * outside of this function.
         */
        if (!(rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST)) {
                PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
                             "rxq->rx_free_thresh=%d, "
                             "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
                             rxq->rx_free_thresh, RTE_PMD_IXGBE_RX_MAX_BURST);
                ret = -EINVAL;
        } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
                PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
                             "rxq->rx_free_thresh=%d, "
                             "rxq->nb_rx_desc=%d",
                             rxq->rx_free_thresh, rxq->nb_rx_desc);
                ret = -EINVAL;
        } else if (!((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0)) {
                PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
                             "rxq->nb_rx_desc=%d, "
                             "rxq->rx_free_thresh=%d",
                             rxq->nb_rx_desc, rxq->rx_free_thresh);
                ret = -EINVAL;
        }

        return ret;
}

/* Reset dynamic ixgbe_rx_queue fields back to defaults */
static void __rte_cold
ixgbe_reset_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_rx_queue *rxq)
{
        static const union ixgbe_adv_rx_desc zeroed_desc = {{0}};
        unsigned i;
        uint16_t len = rxq->nb_rx_desc;

        /*
         * By default, the Rx queue setup function allocates enough memory for
         * IXGBE_MAX_RING_DESC.  The Rx Burst bulk allocation function requires
         * extra memory at the end of the descriptor ring to be zero'd out.
         */
        if (adapter->rx_bulk_alloc_allowed)
                /* zero out extra memory */
                len += RTE_PMD_IXGBE_RX_MAX_BURST;

        /*
         * Zero out HW ring memory. Zero out extra memory at the end of
         * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
         * reads extra memory as zeros.
         */
        for (i = 0; i < len; i++) {
                rxq->rx_ring[i] = zeroed_desc;
        }

        /*
         * initialize extra software ring entries. Space for these extra
         * entries is always allocated
         */
        memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
        for (i = rxq->nb_rx_desc; i < len; ++i) {
                rxq->sw_ring[i].mbuf = &rxq->fake_mbuf;
        }

        rxq->rx_nb_avail = 0;
        rxq->rx_next_avail = 0;
        rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
        rxq->rx_tail = 0;
        rxq->nb_rx_hold = 0;
        rxq->pkt_first_seg = NULL;
        rxq->pkt_last_seg = NULL;

#if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
        rxq->rxrearm_start = 0;
        rxq->rxrearm_nb = 0;
#endif
}

static int
ixgbe_is_vf(struct rte_eth_dev *dev)
{
        struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);

        switch (hw->mac.type) {
        case ixgbe_mac_82599_vf:
        case ixgbe_mac_X540_vf: