dpdk/drivers/net/mvpp2/mrvl_ethdev.h
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   1/* SPDX-License-Identifier: BSD-3-Clause
   2 * Copyright(c) 2017 Marvell International Ltd.
   3 * Copyright(c) 2017 Semihalf.
   4 * All rights reserved.
   5 */
   6
   7#ifndef _MRVL_ETHDEV_H_
   8#define _MRVL_ETHDEV_H_
   9
  10#include <rte_spinlock.h>
  11#include <rte_flow_driver.h>
  12#include <rte_mtr_driver.h>
  13#include <rte_tm_driver.h>
  14
  15/*
  16 * container_of is defined by both DPDK and MUSDK,
  17 * we'll declare only one version.
  18 *
  19 * Note that it is not used in this PMD anyway.
  20 */
  21#ifdef container_of
  22#undef container_of
  23#endif
  24
  25#include <env/mv_autogen_comp_flags.h>
  26#include <drivers/mv_pp2.h>
  27#include <drivers/mv_pp2_bpool.h>
  28#include <drivers/mv_pp2_cls.h>
  29#include <drivers/mv_pp2_hif.h>
  30#include <drivers/mv_pp2_ppio.h>
  31#include "env/mv_common.h" /* for BIT() */
  32
  33/** Maximum number of rx queues per port */
  34#define MRVL_PP2_RXQ_MAX 32
  35
  36/** Maximum number of tx queues per port */
  37#define MRVL_PP2_TXQ_MAX 8
  38
  39/** Minimum number of descriptors in tx queue */
  40#define MRVL_PP2_TXD_MIN 16
  41
  42/** Maximum number of descriptors in tx queue */
  43#define MRVL_PP2_TXD_MAX 2048
  44
  45/** Tx queue descriptors alignment */
  46#define MRVL_PP2_TXD_ALIGN 16
  47
  48/** Minimum number of descriptors in rx queue */
  49#define MRVL_PP2_RXD_MIN 16
  50
  51/** Maximum number of descriptors in rx queue */
  52#define MRVL_PP2_RXD_MAX 2048
  53
  54/** Rx queue descriptors alignment */
  55#define MRVL_PP2_RXD_ALIGN 16
  56
  57/** Maximum number of descriptors in tx aggregated queue */
  58#define MRVL_PP2_AGGR_TXQD_MAX 2048
  59
  60/** Maximum number of Traffic Classes. */
  61#define MRVL_PP2_TC_MAX 8
  62
  63/** Packet offset inside RX buffer. */
  64#define MRVL_PKT_OFFS 64
  65
  66/** Maximum number of descriptors in shadow queue. Must be power of 2 */
  67#define MRVL_PP2_TX_SHADOWQ_SIZE MRVL_PP2_TXD_MAX
  68
  69/** Shadow queue size mask (since shadow queue size is power of 2) */
  70#define MRVL_PP2_TX_SHADOWQ_MASK (MRVL_PP2_TX_SHADOWQ_SIZE - 1)
  71
  72/** Minimum number of sent buffers to release from shadow queue to BM */
  73#define MRVL_PP2_BUF_RELEASE_BURST_SIZE 64
  74
  75#define MRVL_PP2_VLAN_TAG_LEN   4
  76#define MRVL_PP2_ETH_HDRS_LEN   (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + \
  77                                (2 * MRVL_PP2_VLAN_TAG_LEN))
  78#define MRVL_PP2_HDRS_LEN               (MV_MH_SIZE + MRVL_PP2_ETH_HDRS_LEN)
  79#define MRVL_PP2_MTU_TO_MRU(mtu)        ((mtu) + MRVL_PP2_HDRS_LEN)
  80#define MRVL_PP2_MRU_TO_MTU(mru)        ((mru) - MRVL_PP2_HDRS_LEN)
  81
  82/** Maximum length of a match string */
  83#define MRVL_MATCH_LEN 16
  84
  85#define MRVL_BURST_SIZE 64
  86
  87/** PMD-specific definition of a flow rule handle. */
  88struct mrvl_mtr;
  89struct rte_flow {
  90        LIST_ENTRY(rte_flow) next;
  91        struct mrvl_mtr *mtr;
  92
  93        struct pp2_cls_tbl_key table_key;
  94        struct pp2_cls_tbl_rule rule;
  95        struct pp2_cls_cos_desc cos;
  96        struct pp2_cls_tbl_action action;
  97        uint8_t next_udf_id;
  98};
  99
 100struct mrvl_mtr_profile {
 101        LIST_ENTRY(mrvl_mtr_profile) next;
 102        uint32_t profile_id;
 103        int refcnt;
 104        struct rte_mtr_meter_profile profile;
 105};
 106
 107struct mrvl_mtr {
 108        LIST_ENTRY(mrvl_mtr) next;
 109        uint32_t mtr_id;
 110        int refcnt;
 111        int shared;
 112        int enabled;
 113        int plcr_bit;
 114        struct mrvl_mtr_profile *profile;
 115        struct pp2_cls_plcr *plcr;
 116};
 117
 118struct mrvl_tm_shaper_profile {
 119        LIST_ENTRY(mrvl_tm_shaper_profile) next;
 120        uint32_t id;
 121        int refcnt;
 122        struct rte_tm_shaper_params params;
 123};
 124
 125enum {
 126        MRVL_NODE_PORT,
 127        MRVL_NODE_QUEUE,
 128};
 129
 130struct mrvl_tm_node {
 131        LIST_ENTRY(mrvl_tm_node) next;
 132        uint32_t id;
 133        uint32_t type;
 134        int refcnt;
 135        struct mrvl_tm_node *parent;
 136        struct mrvl_tm_shaper_profile *profile;
 137        uint8_t weight;
 138        uint64_t stats_mask;
 139};
 140
 141struct mrvl_priv {
 142        /* Hot fields, used in fast path. */
 143        struct pp2_bpool *bpool;  /**< BPool pointer */
 144        struct pp2_ppio *ppio;    /**< Port handler pointer */
 145        rte_spinlock_t lock;      /**< Spinlock for checking bpool status */
 146        uint16_t bpool_max_size;  /**< BPool maximum size */
 147        uint16_t bpool_min_size;  /**< BPool minimum size  */
 148        uint16_t bpool_init_size; /**< Configured BPool size  */
 149
 150        /** Mapping for DPDK rx queue->(TC, MRVL relative inq) */
 151        struct {
 152                uint8_t tc;  /**< Traffic Class */
 153                uint8_t inq; /**< Relative in-queue number */
 154        } rxq_map[MRVL_PP2_RXQ_MAX] __rte_cache_aligned;
 155
 156        /* Configuration data, used sporadically. */
 157        uint8_t pp_id;
 158        uint8_t ppio_id;
 159        uint8_t bpool_bit;
 160        uint8_t rss_hf_tcp;
 161        uint8_t uc_mc_flushed;
 162        uint8_t isolated;
 163        uint8_t multiseg;
 164        uint16_t max_mtu;
 165        uint8_t flow_ctrl;
 166        struct rte_eth_fc_conf fc_conf;
 167
 168        struct pp2_ppio_params ppio_params;
 169        struct pp2_cls_qos_tbl_params qos_tbl_params;
 170        struct pp2_cls_tbl *qos_tbl;
 171        uint16_t nb_rx_queues;
 172
 173        struct pp2_cls_tbl_params cls_tbl_params;
 174        struct pp2_cls_tbl *cls_tbl;
 175        LIST_HEAD(mrvl_flows, rte_flow) flows;
 176
 177        struct pp2_cls_plcr *default_policer;
 178
 179        LIST_HEAD(profiles, mrvl_mtr_profile) profiles;
 180        LIST_HEAD(mtrs, mrvl_mtr) mtrs;
 181        uint32_t used_plcrs;
 182
 183        LIST_HEAD(shaper_profiles, mrvl_tm_shaper_profile) shaper_profiles;
 184        LIST_HEAD(nodes, mrvl_tm_node) nodes;
 185        uint64_t rate_max;
 186
 187        uint8_t forward_bad_frames;
 188        uint32_t fill_bpool_buffs;
 189
 190        uint8_t configured; /** indicates if device has been configured */
 191};
 192
 193/** Flow operations forward declaration. */
 194extern const struct rte_flow_ops mrvl_flow_ops;
 195
 196/** Meter operations forward declaration. */
 197extern const struct rte_mtr_ops mrvl_mtr_ops;
 198
 199/** Traffic manager operations forward declaration. */
 200extern const struct rte_tm_ops mrvl_tm_ops;
 201
 202/** Current log type. */
 203extern int mrvl_logtype;
 204
 205#define MRVL_LOG(level, fmt, args...) \
 206        rte_log(RTE_LOG_ ## level, mrvl_logtype, "%s(): " fmt "\n", \
 207                __func__, ##args)
 208
 209extern struct pp2_bpool *dummy_pool[PP2_NUM_PKT_PROC];
 210
 211/**
 212 * Convert string to uint32_t with extra checks for result correctness.
 213 *
 214 * @param string String to convert.
 215 * @param val Conversion result.
 216 * @returns 0 in case of success, negative value otherwise.
 217 */
 218static int
 219get_val_securely(const char *string, uint32_t *val)
 220{
 221        char *endptr;
 222        size_t len = strlen(string);
 223
 224        if (len == 0)
 225                return -1;
 226
 227        errno = 0;
 228        *val = strtoul(string, &endptr, 0);
 229        if (errno != 0 || RTE_PTR_DIFF(endptr, string) != len)
 230                return -2;
 231
 232        return 0;
 233}
 234
 235static int
 236get_val_securely8(const char *string, uint32_t base, uint8_t *val)
 237{
 238        char *endptr;
 239        size_t len = strlen(string);
 240
 241        if (len == 0)
 242                return -1;
 243
 244        errno = 0;
 245        *val = (uint8_t)strtoul(string, &endptr, base);
 246        if (errno != 0 || RTE_PTR_DIFF(endptr, string) != len)
 247                return -2;
 248
 249        return 0;
 250}
 251
 252#endif /* _MRVL_ETHDEV_H_ */
 253