1/* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018-2019 NXP 3 */ 4 5#ifndef _BMU_H_ 6#define _BMU_H_ 7 8#define BMU_VERSION 0x000 9#define BMU_CTRL 0x004 10#define BMU_UCAST_CONFIG 0x008 11#define BMU_UCAST_BASE_ADDR 0x00c 12#define BMU_BUF_SIZE 0x010 13#define BMU_BUF_CNT 0x014 14#define BMU_THRES 0x018 15#define BMU_INT_SRC 0x020 16#define BMU_INT_ENABLE 0x024 17#define BMU_ALLOC_CTRL 0x030 18#define BMU_FREE_CTRL 0x034 19#define BMU_FREE_ERR_ADDR 0x038 20#define BMU_CURR_BUF_CNT 0x03c 21#define BMU_MCAST_CNT 0x040 22#define BMU_MCAST_ALLOC_CTRL 0x044 23#define BMU_REM_BUF_CNT 0x048 24#define BMU_LOW_WATERMARK 0x050 25#define BMU_HIGH_WATERMARK 0x054 26#define BMU_INT_MEM_ACCESS 0x100 27 28struct BMU_CFG { 29 unsigned long baseaddr; 30 u32 count; 31 u32 size; 32 u32 low_watermark; 33 u32 high_watermark; 34}; 35 36#define BMU1_BUF_SIZE LMEM_BUF_SIZE_LN2 37#define BMU2_BUF_SIZE DDR_BUF_SIZE_LN2 38 39#define BMU2_MCAST_ALLOC_CTRL (BMU2_BASE_ADDR + BMU_MCAST_ALLOC_CTRL) 40 41#endif /* _BMU_H_ */ 42