/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright (c) 2016 - 2018 Cavium Inc.
 * All rights reserved.
 * www.cavium.com
 */

#include "bcm_osal.h"
#include "reg_addr.h"
#include "ecore_gtt_reg_addr.h"
#include "ecore.h"
#include "ecore_chain.h"
#include "ecore_status.h"
#include "ecore_hw.h"
#include "ecore_rt_defs.h"
#include "ecore_init_ops.h"
#include "ecore_int.h"
#include "ecore_cxt.h"
#include "ecore_spq.h"
#include "ecore_init_fw_funcs.h"
#include "ecore_sp_commands.h"
#include "ecore_dev_api.h"
#include "ecore_sriov.h"
#include "ecore_vf.h"
#include "ecore_mcp.h"
#include "ecore_hw_defs.h"
#include "mcp_public.h"
#include "ecore_iro.h"
#include "nvm_cfg.h"
#include "ecore_dcbx.h"
#include "ecore_l2.h"

/* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
 * registers involved are not split and thus configuration is a race where
 * some of the PFs configuration might be lost.
 * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
 * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
 * there's more than a single compiled ecore component in system].
 */
static osal_spinlock_t qm_lock;
static u32 qm_lock_ref_cnt;

#ifndef ASIC_ONLY
static bool b_ptt_gtt_init;
#endif

/******************** Doorbell Recovery *******************/
/* The doorbell recovery mechanism consists of a list of entries which represent
 * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
 * entity needs to register with the mechanism and provide the parameters
 * describing it's doorbell, including a location where last used doorbell data
 * can be found. The doorbell execute function will traverse the list and
 * doorbell all of the registered entries.
 */
struct ecore_db_recovery_entry {
        osal_list_entry_t       list_entry;
        void OSAL_IOMEM         *db_addr;
        void                    *db_data;
        enum ecore_db_rec_width db_width;
        enum ecore_db_rec_space db_space;
        u8                      hwfn_idx;
};

/* display a single doorbell recovery entry */
void ecore_db_recovery_dp_entry(struct ecore_hwfn *p_hwfn,
                                struct ecore_db_recovery_entry *db_entry,
                                const char *action)
{
        DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
                   action, db_entry, db_entry->db_addr, db_entry->db_data,
                   db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
                   db_entry->db_space == DB_REC_USER ? "user" : "kernel",
                   db_entry->hwfn_idx);
}

/* doorbell address sanity (address within doorbell bar range) */
bool ecore_db_rec_sanity(struct ecore_dev *p_dev, void OSAL_IOMEM *db_addr,
                         void *db_data)
{
        /* make sure doorbell address  is within the doorbell bar */
        if (db_addr < p_dev->doorbells || (u8 *)db_addr >
                        (u8 *)p_dev->doorbells + p_dev->db_size) {
                OSAL_WARN(true,
                          "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
                          db_addr, p_dev->doorbells,
                          (u8 *)p_dev->doorbells + p_dev->db_size);
                return false;
        }

        /* make sure doorbell data pointer is not null */
        if (!db_data) {
                OSAL_WARN(true, "Illegal doorbell data pointer: %p", db_data);
                return false;
        }

        return true;
}

/* find hwfn according to the doorbell address */
struct ecore_hwfn *ecore_db_rec_find_hwfn(struct ecore_dev *p_dev,
                                          void OSAL_IOMEM *db_addr)
{
        struct ecore_hwfn *p_hwfn;

        /* In CMT doorbell bar is split down the middle between engine 0 and
         * enigne 1
         */
        if (ECORE_IS_CMT(p_dev))
                p_hwfn = db_addr < p_dev->hwfns[1].doorbells ?
                        &p_dev->hwfns[0] : &p_dev->hwfns[1];
        else
                p_hwfn = ECORE_LEADING_HWFN(p_dev);

        return p_hwfn;
}

/* add a new entry to the doorbell recovery mechanism */
enum _ecore_status_t ecore_db_recovery_add(struct ecore_dev *p_dev,
                                           void OSAL_IOMEM *db_addr,
                                           void *db_data,
                                           enum ecore_db_rec_width db_width,
                                           enum ecore_db_rec_space db_space)
{
        struct ecore_db_recovery_entry *db_entry;
        struct ecore_hwfn *p_hwfn;

        /* shortcircuit VFs, for now */
        if (IS_VF(p_dev)) {
                DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
                return ECORE_SUCCESS;
        }

        /* sanitize doorbell address */
        if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
                return ECORE_INVAL;

        /* obtain hwfn from doorbell address */
        p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);

        /* create entry */
        db_entry = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*db_entry));
        if (!db_entry) {
                DP_NOTICE(p_dev, false, "Failed to allocate a db recovery entry\n");
                return ECORE_NOMEM;
        }

        /* populate entry */
        db_entry->db_addr = db_addr;
        db_entry->db_data = db_data;
        db_entry->db_width = db_width;
        db_entry->db_space = db_space;
        db_entry->hwfn_idx = p_hwfn->my_id;

        /* display */
        ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");

        /* protect the list */
        OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
        OSAL_LIST_PUSH_TAIL(&db_entry->list_entry,
                            &p_hwfn->db_recovery_info.list);
        OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);

        return ECORE_SUCCESS;
}

/* remove an entry from the doorbell recovery mechanism */
enum _ecore_status_t ecore_db_recovery_del(struct ecore_dev *p_dev,
                                           void OSAL_IOMEM *db_addr,
                                           void *db_data)
{
        struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
        enum _ecore_status_t rc = ECORE_INVAL;
        struct ecore_hwfn *p_hwfn;

        /* shortcircuit VFs, for now */
        if (IS_VF(p_dev)) {
                DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
                return ECORE_SUCCESS;
        }

        /* sanitize doorbell address */
        if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
                return ECORE_INVAL;

        /* obtain hwfn from doorbell address */
        p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);

        /* protect the list */
        OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
        OSAL_LIST_FOR_EACH_ENTRY(db_entry,
                                 &p_hwfn->db_recovery_info.list,
                                 list_entry,
                                 struct ecore_db_recovery_entry) {
                /* search according to db_data addr since db_addr is not unique
                 * (roce)
                 */
                if (db_entry->db_data == db_data) {
                        ecore_db_recovery_dp_entry(p_hwfn, db_entry,
                                                   "Deleting");
                        OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
                                               &p_hwfn->db_recovery_info.list);
                        rc = ECORE_SUCCESS;
                        break;
                }
        }

        OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);

        if (rc == ECORE_INVAL)
                /*OSAL_WARN(true,*/
                DP_NOTICE(p_hwfn, false,
                          "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
                          db_data, db_addr);
        else
                OSAL_FREE(p_dev, db_entry);

        return rc;
}

/* initialize the doorbell recovery mechanism */
enum _ecore_status_t ecore_db_recovery_setup(struct ecore_hwfn *p_hwfn)
{
        DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Setting up db recovery\n");

        /* make sure db_size was set in p_dev */
        if (!p_hwfn->p_dev->db_size) {
                DP_ERR(p_hwfn->p_dev, "db_size not set\n");
                return ECORE_INVAL;
        }

        OSAL_LIST_INIT(&p_hwfn->db_recovery_info.list);
#ifdef CONFIG_ECORE_LOCK_ALLOC
        if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->db_recovery_info.lock))
                return ECORE_NOMEM;
#endif
        OSAL_SPIN_LOCK_INIT(&p_hwfn->db_recovery_info.lock);
        p_hwfn->db_recovery_info.db_recovery_counter = 0;

        return ECORE_SUCCESS;
}

/* destroy the doorbell recovery mechanism */
void ecore_db_recovery_teardown(struct ecore_hwfn *p_hwfn)
{
        struct ecore_db_recovery_entry *db_entry = OSAL_NULL;

        DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Tearing down db recovery\n");
        if (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
                DP_VERBOSE(p_hwfn, false, "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
                while (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
                        db_entry = OSAL_LIST_FIRST_ENTRY(
                                                &p_hwfn->db_recovery_info.list,
                                                struct ecore_db_recovery_entry,
                                                list_entry);
                        ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
                        OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
                                               &p_hwfn->db_recovery_info.list);
                        OSAL_FREE(p_hwfn->p_dev, db_entry);
                }
        }
#ifdef CONFIG_ECORE_LOCK_ALLOC
        OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->db_recovery_info.lock);
#endif
        p_hwfn->db_recovery_info.db_recovery_counter = 0;
}

/* print the content of the doorbell recovery mechanism */
void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn)
{
        struct ecore_db_recovery_entry *db_entry = OSAL_NULL;

        DP_NOTICE(p_hwfn, false,
                  "Dispalying doorbell recovery database. Counter was %d\n",
                  p_hwfn->db_recovery_info.db_recovery_counter);

        /* protect the list */
        OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
        OSAL_LIST_FOR_EACH_ENTRY(db_entry,
                                 &p_hwfn->db_recovery_info.list,
                                 list_entry,
                                 struct ecore_db_recovery_entry) {
                ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
        }

        OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
}

/* ring the doorbell of a single doorbell recovery entry */
void ecore_db_recovery_ring(struct ecore_hwfn *p_hwfn,
                            struct ecore_db_recovery_entry *db_entry,
                            enum ecore_db_rec_exec db_exec)
{
        /* Print according to width */
        if (db_entry->db_width == DB_REC_WIDTH_32B)
                DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %x\n",
                           db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
                           db_entry->db_addr, *(u32 *)db_entry->db_data);
        else
                DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %lx\n",
                           db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
                           db_entry->db_addr,
                           *(unsigned long *)(db_entry->db_data));

        /* Sanity */
        if (!ecore_db_rec_sanity(p_hwfn->p_dev, db_entry->db_addr,
                                 db_entry->db_data))
                return;

        /* Flush the write combined buffer. Since there are multiple doorbelling
         * entities using the same address, if we don't flush, a transaction
         * could be lost.
         */
        OSAL_WMB(p_hwfn->p_dev);

        /* Ring the doorbell */
        if (db_exec == DB_REC_REAL_DEAL || db_exec == DB_REC_ONCE) {
                if (db_entry->db_width == DB_REC_WIDTH_32B)
                        DIRECT_REG_WR(p_hwfn, db_entry->db_addr,
                                      *(u32 *)(db_entry->db_data));
                else
                        DIRECT_REG_WR64(p_hwfn, db_entry->db_addr,
                                        *(u64 *)(db_entry->db_data));
        }

        /* Flush the write combined buffer. Next doorbell may come from a
         * different entity to the same address...
         */
        OSAL_WMB(p_hwfn->p_dev);
}

/* traverse the doorbell recovery entry list and ring all the doorbells */
void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
                               enum ecore_db_rec_exec db_exec)
{
        struct ecore_db_recovery_entry *db_entry = OSAL_NULL;

        if (db_exec != DB_REC_ONCE) {
                DP_NOTICE(p_hwfn, false, "Executing doorbell recovery. Counter was %d\n",
                          p_hwfn->db_recovery_info.db_recovery_counter);

                /* track amount of times recovery was executed */
                p_hwfn->db_recovery_info.db_recovery_counter++;
        }

        /* protect the list */
        OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
        OSAL_LIST_FOR_EACH_ENTRY(db_entry,
                                 &p_hwfn->db_recovery_info.list,
                                 list_entry,
                                 struct ecore_db_recovery_entry) {
                ecore_db_recovery_ring(p_hwfn, db_entry, db_exec);
                if (db_exec == DB_REC_ONCE)
                        break;
        }

        OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
}
/******************** Doorbell Recovery end ****************/

/********************************** NIG LLH ***********************************/

enum ecore_llh_filter_type {
        ECORE_LLH_FILTER_TYPE_MAC,
        ECORE_LLH_FILTER_TYPE_PROTOCOL,
};

struct ecore_llh_mac_filter {
        u8 addr[ETH_ALEN];
};

struct ecore_llh_protocol_filter {
        enum ecore_llh_prot_filter_type_t type;
        u16 source_port_or_eth_type;
        u16 dest_port;
};

union ecore_llh_filter {
        struct ecore_llh_mac_filter mac;
        struct ecore_llh_protocol_filter protocol;
};

struct ecore_llh_filter_info {
        bool b_enabled;
        u32 ref_cnt;
        enum ecore_llh_filter_type type;
        union ecore_llh_filter filter;
};

struct ecore_llh_info {
        /* Number of LLH filters banks */
        u8 num_ppfid;

#define MAX_NUM_PPFID   8
        u8 ppfid_array[MAX_NUM_PPFID];

        /* Array of filters arrays:
         * "num_ppfid" elements of filters banks, where each is an array of
         * "NIG_REG_LLH_FUNC_FILTER_EN_SIZE" filters.
         */
        struct ecore_llh_filter_info **pp_filters;
};

static void ecore_llh_free(struct ecore_dev *p_dev)
{
        struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
        u32 i;

        if (p_llh_info != OSAL_NULL) {
                if (p_llh_info->pp_filters != OSAL_NULL) {
                        for (i = 0; i < p_llh_info->num_ppfid; i++)
                                OSAL_FREE(p_dev, p_llh_info->pp_filters[i]);
                }

                OSAL_FREE(p_dev, p_llh_info->pp_filters);
        }

        OSAL_FREE(p_dev, p_llh_info);
        p_dev->p_llh_info = OSAL_NULL;
}

static enum _ecore_status_t ecore_llh_alloc(struct ecore_dev *p_dev)
{
        struct ecore_llh_info *p_llh_info;
        u32 size;
        u8 i;

        p_llh_info = OSAL_ZALLOC(p_dev, GFP_KERNEL, sizeof(*p_llh_info));
        if (!p_llh_info)
                return ECORE_NOMEM;
        p_dev->p_llh_info = p_llh_info;

        for (i = 0; i < MAX_NUM_PPFID; i++) {
                if (!(p_dev->ppfid_bitmap & (0x1 << i)))
                        continue;

                p_llh_info->ppfid_array[p_llh_info->num_ppfid] = i;
                DP_VERBOSE(p_dev, ECORE_MSG_SP, "ppfid_array[%d] = %hhd\n",
                           p_llh_info->num_ppfid, i);
                p_llh_info->num_ppfid++;
        }

        size = p_llh_info->num_ppfid * sizeof(*p_llh_info->pp_filters);
        p_llh_info->pp_filters = OSAL_ZALLOC(p_dev, GFP_KERNEL, size);
        if (!p_llh_info->pp_filters)
                return ECORE_NOMEM;

        size = NIG_REG_LLH_FUNC_FILTER_EN_SIZE *
               sizeof(**p_llh_info->pp_filters);
        for (i = 0; i < p_llh_info->num_ppfid; i++) {
                p_llh_info->pp_filters[i] = OSAL_ZALLOC(p_dev, GFP_KERNEL,
                                                        size);
                if (!p_llh_info->pp_filters[i])
                        return ECORE_NOMEM;
        }

        return ECORE_SUCCESS;
}

static enum _ecore_status_t ecore_llh_shadow_sanity(struct ecore_dev *p_dev,
                                                    u8 ppfid, u8 filter_idx,
                                                    const char *action)
{
        struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;

        if (ppfid >= p_llh_info->num_ppfid) {
                DP_NOTICE(p_dev, false,
                          "LLH shadow [%s]: using ppfid %d while only %d ppfids are available\n",
                          action, ppfid, p_llh_info->num_ppfid);
                return ECORE_INVAL;
        }

        if (filter_idx >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
                DP_NOTICE(p_dev, false,
                          "LLH shadow [%s]: using filter_idx %d while only %d filters are available\n",
                          action, filter_idx, NIG_REG_LLH_FUNC_FILTER_EN_SIZE);
                return ECORE_INVAL;
        }

        return ECORE_SUCCESS;
}

#define ECORE_LLH_INVALID_FILTER_IDX    0xff

static enum _ecore_status_t
ecore_llh_shadow_search_filter(struct ecore_dev *p_dev, u8 ppfid,
                               union ecore_llh_filter *p_filter,
                               u8 *p_filter_idx)
{
        struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
        struct ecore_llh_filter_info *p_filters;
        enum _ecore_status_t rc;
        u8 i;

        rc = ecore_llh_shadow_sanity(p_dev, ppfid, 0, "search");
        if (rc != ECORE_SUCCESS)
                return rc;

        *p_filter_idx = ECORE_LLH_INVALID_FILTER_IDX;

        p_filters = p_llh_info->pp_filters[ppfid];
        for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
                if (!OSAL_MEMCMP(p_filter, &p_filters[i].filter,
                                 sizeof(*p_filter))) {
                        *p_filter_idx = i;
                        break;
                }
        }

        return ECORE_SUCCESS;
}

static enum _ecore_status_t
ecore_llh_shadow_get_free_idx(struct ecore_dev *p_dev, u8 ppfid,
                              u8 *p_filter_idx)
{
        struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
        struct ecore_llh_filter_info *p_filters;
        enum _ecore_status_t rc;
        u8 i;

        rc = ecore_llh_shadow_sanity(p_dev, ppfid, 0, "get_free_idx");
        if (rc != ECORE_SUCCESS)
                return rc;

        *p_filter_idx = ECORE_LLH_INVALID_FILTER_IDX;

        p_filters = p_llh_info->pp_filters[ppfid];
        for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
                if (!p_filters[i].b_enabled) {
                        *p_filter_idx = i;
                        break;
                }
        }

        return ECORE_SUCCESS;
}

static enum _ecore_status_t
__ecore_llh_shadow_add_filter(struct ecore_dev *p_dev, u8 ppfid, u8 filter_idx,
                              enum ecore_llh_filter_type type,
                              union ecore_llh_filter *p_filter, u32 *p_ref_cnt)
{
        struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
        struct ecore_llh_filter_info *p_filters;
        enum _ecore_status_t rc;

        rc = ecore_llh_shadow_sanity(p_dev, ppfid, filter_idx, "add");
        if (rc != ECORE_SUCCESS)
                return rc;

        p_filters = p_llh_info->pp_filters[ppfid];
        if (!p_filters[filter_idx].ref_cnt) {
                p_filters[filter_idx].b_enabled = true;
                p_filters[filter_idx].type = type;
                OSAL_MEMCPY(&p_filters[filter_idx].filter, p_filter,
                            sizeof(p_filters[filter_idx].filter));
        }

        *p_ref_cnt = ++p_filters[filter_idx].ref_cnt;

        return ECORE_SUCCESS;
}

static enum _ecore_status_t
ecore_llh_shadow_add_filter(struct ecore_dev *p_dev, u8 ppfid,
                            enum ecore_llh_filter_type type,
                            union ecore_llh_filter *p_filter,
                            u8 *p_filter_idx, u32 *p_ref_cnt)
{
        enum _ecore_status_t rc;

        /* Check if the same filter already exist */
        rc = ecore_llh_shadow_search_filter(p_dev, ppfid, p_filter,
                                            p_filter_idx);
        if (rc != ECORE_SUCCESS)
                return rc;

        /* Find a new entry in case of a new filter */
        if (*p_filter_idx == ECORE_LLH_INVALID_FILTER_IDX) {
                rc = ecore_llh_shadow_get_free_idx(p_dev, ppfid, p_filter_idx);
                if (rc != ECORE_SUCCESS)
                        return rc;
        }

        /* No free entry was found */
        if (*p_filter_idx == ECORE_LLH_INVALID_FILTER_IDX) {
                DP_NOTICE(p_dev, false,
                          "Failed to find an empty LLH filter to utilize [ppfid %d]\n",
                          ppfid);
                return ECORE_NORESOURCES;
        }

        return __ecore_llh_shadow_add_filter(p_dev, ppfid, *p_filter_idx, type,
                                             p_filter, p_ref_cnt);
}

static enum _ecore_status_t
__ecore_llh_shadow_remove_filter(struct ecore_dev *p_dev, u8 ppfid,
                                 u8 filter_idx, u32 *p_ref_cnt)
{
        struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
        struct ecore_llh_filter_info *p_filters;
        enum _ecore_status_t rc;

        rc = ecore_llh_shadow_sanity(p_dev, ppfid, filter_idx, "remove");
        if (rc != ECORE_SUCCESS)
                return rc;

        p_filters = p_llh_info->pp_filters[ppfid];
        if (!p_filters[filter_idx].ref_cnt) {
                DP_NOTICE(p_dev, false,
                          "LLH shadow: trying to remove a filter with ref_cnt=0\n");
                return ECORE_INVAL;
        }

        *p_ref_cnt = --p_filters[filter_idx].ref_cnt;
        if (!p_filters[filter_idx].ref_cnt)
                OSAL_MEM_ZERO(&p_filters[filter_idx],
                              sizeof(p_filters[filter_idx]));

        return ECORE_SUCCESS;
}

static enum _ecore_status_t
ecore_llh_shadow_remove_filter(struct ecore_dev *p_dev, u8 ppfid,
                               union ecore_llh_filter *p_filter,
                               u8 *p_filter_idx, u32 *p_ref_cnt)
{
        enum _ecore_status_t rc;

        rc = ecore_llh_shadow_search_filter(p_dev, ppfid, p_filter,
                                            p_filter_idx);
        if (rc != ECORE_SUCCESS)
                return rc;

        /* No matching filter was found */
        if (*p_filter_idx == ECORE_LLH_INVALID_FILTER_IDX) {
                DP_NOTICE(p_dev, false,
                          "Failed to find a filter in the LLH shadow\n");
                return ECORE_INVAL;
        }

        return __ecore_llh_shadow_remove_filter(p_dev, ppfid, *p_filter_idx,
                                                p_ref_cnt);
}

static enum _ecore_status_t
ecore_llh_shadow_remove_all_filters(struct ecore_dev *p_dev, u8 ppfid)
{
        struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
        struct ecore_llh_filter_info *p_filters;
        enum _ecore_status_t rc;

        rc = ecore_llh_shadow_sanity(p_dev, ppfid, 0, "remove_all");
        if (rc != ECORE_SUCCESS)
                return rc;

        p_filters = p_llh_info->pp_filters[ppfid];
        OSAL_MEM_ZERO(p_filters,
                      NIG_REG_LLH_FUNC_FILTER_EN_SIZE * sizeof(*p_filters));

        return ECORE_SUCCESS;
}

static enum _ecore_status_t ecore_abs_ppfid(struct ecore_dev *p_dev,
                                            u8 rel_ppfid, u8 *p_abs_ppfid)
{
        struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
        u8 ppfids = p_llh_info->num_ppfid - 1;

        if (rel_ppfid >= p_llh_info->num_ppfid) {
                DP_NOTICE(p_dev, false,
                          "rel_ppfid %d is not valid, available indices are 0..%hhd\n",
                          rel_ppfid, ppfids);
                return ECORE_INVAL;
        }

        *p_abs_ppfid = p_llh_info->ppfid_array[rel_ppfid];

        return ECORE_SUCCESS;
}

static enum _ecore_status_t
__ecore_llh_set_engine_affin(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
{
        struct ecore_dev *p_dev = p_hwfn->p_dev;
        enum ecore_eng eng;
        u8 ppfid;
        enum _ecore_status_t rc;

        rc = ecore_mcp_get_engine_config(p_hwfn, p_ptt);
        if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
                DP_NOTICE(p_hwfn, false,
                          "Failed to get the engine affinity configuration\n");
                return rc;
        }

        /* RoCE PF is bound to a single engine */
        if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
                eng = p_dev->fir_affin ? ECORE_ENG1 : ECORE_ENG0;
                rc = ecore_llh_set_roce_affinity(p_dev, eng);
                if (rc != ECORE_SUCCESS) {
                        DP_NOTICE(p_dev, false,
                                  "Failed to set the RoCE engine affinity\n");
                        return rc;
                }

                DP_VERBOSE(p_dev, ECORE_MSG_SP,
                           "LLH: Set the engine affinity of RoCE packets as %d\n",
                           eng);
        }

        /* Storage PF is bound to a single engine while L2 PF uses both */
        if (ECORE_IS_FCOE_PERSONALITY(p_hwfn) ||
            ECORE_IS_ISCSI_PERSONALITY(p_hwfn))
                eng = p_dev->fir_affin ? ECORE_ENG1 : ECORE_ENG0;
        else /* L2_PERSONALITY */
                eng = ECORE_BOTH_ENG;

        for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
                rc = ecore_llh_set_ppfid_affinity(p_dev, ppfid, eng);
                if (rc != ECORE_SUCCESS) {
                        DP_NOTICE(p_dev, false,
                                  "Failed to set the engine affinity of ppfid %d\n",
                                  ppfid);
                        return rc;
                }
        }

        DP_VERBOSE(p_dev, ECORE_MSG_SP,
                   "LLH: Set the engine affinity of non-RoCE packets as %d\n",
                   eng);

        return ECORE_SUCCESS;
}

static enum _ecore_status_t
ecore_llh_set_engine_affin(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
                           bool avoid_eng_affin)
{
        struct ecore_dev *p_dev = p_hwfn->p_dev;
        enum _ecore_status_t rc;

        /* Backwards compatible mode:
         * - RoCE packets     - Use engine 0.
         * - Non-RoCE packets - Use connection based classification for L2 PFs,
         *                      and engine 0 otherwise.
         */
        if (avoid_eng_affin) {
                enum ecore_eng eng;
                u8 ppfid;

                if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
                        eng = ECORE_ENG0;
                        rc = ecore_llh_set_roce_affinity(p_dev, eng);
                        if (rc != ECORE_SUCCESS) {
                                DP_NOTICE(p_dev, false,
                                          "Failed to set the RoCE engine affinity\n");
                                return rc;
                        }

                        DP_VERBOSE(p_dev, ECORE_MSG_SP,
                                   "LLH [backwards compatible mode]: Set the engine affinity of RoCE packets as %d\n",
                                   eng);
                }

                eng = (ECORE_IS_FCOE_PERSONALITY(p_hwfn) ||
                       ECORE_IS_ISCSI_PERSONALITY(p_hwfn)) ? ECORE_ENG0
                                                           : ECORE_BOTH_ENG;
                for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
                        rc = ecore_llh_set_ppfid_affinity(p_dev, ppfid, eng);
                        if (rc != ECORE_SUCCESS) {
                                DP_NOTICE(p_dev, false,
                                          "Failed to set the engine affinity of ppfid %d\n",
                                          ppfid);
                                return rc;
                        }
                }

                DP_VERBOSE(p_dev, ECORE_MSG_SP,
                           "LLH [backwards compatible mode]: Set the engine affinity of non-RoCE packets as %d\n",
                           eng);

                return ECORE_SUCCESS;
        }

        return __ecore_llh_set_engine_affin(p_hwfn, p_ptt);
}

static enum _ecore_status_t ecore_llh_hw_init_pf(struct ecore_hwfn *p_hwfn,
                                                 struct ecore_ptt *p_ptt,
                                                 bool avoid_eng_affin)
{
        struct ecore_dev *p_dev = p_hwfn->p_dev;
        u8 ppfid, abs_ppfid;
        enum _ecore_status_t rc;

        for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
                u32 addr;

                rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
                if (rc != ECORE_SUCCESS)
                        return rc;

                addr = NIG_REG_LLH_PPFID2PFID_TBL_0 + abs_ppfid * 0x4;
                ecore_wr(p_hwfn, p_ptt, addr, p_hwfn->rel_pf_id);
        }

        if (OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&
            !ECORE_IS_FCOE_PERSONALITY(p_hwfn)) {
                rc = ecore_llh_add_mac_filter(p_dev, 0,
                                              p_hwfn->hw_info.hw_mac_addr);
                if (rc != ECORE_SUCCESS)
                        DP_NOTICE(p_dev, false,
                                  "Failed to add an LLH filter with the primary MAC\n");
        }

        if (ECORE_IS_CMT(p_dev)) {
                rc = ecore_llh_set_engine_affin(p_hwfn, p_ptt, avoid_eng_affin);
                if (rc != ECORE_SUCCESS)
                        return rc;
        }

        return ECORE_SUCCESS;
}

u8 ecore_llh_get_num_ppfid(struct ecore_dev *p_dev)
{
        return p_dev->p_llh_info->num_ppfid;
}

enum ecore_eng ecore_llh_get_l2_affinity_hint(struct ecore_dev *p_dev)
{
        return p_dev->l2_affin_hint ? ECORE_ENG1 : ECORE_ENG0;
}

/* TBD - should be removed when these definitions are available in reg_addr.h */
#define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_MASK             0x3
#define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_SHIFT            0
#define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_MASK         0x3
#define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_SHIFT        2

enum _ecore_status_t ecore_llh_set_ppfid_affinity(struct ecore_dev *p_dev,
                                                  u8 ppfid, enum ecore_eng eng)
{
        struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
        struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
        u32 addr, val, eng_sel;
        enum _ecore_status_t rc = ECORE_SUCCESS;
        u8 abs_ppfid;

        if (p_ptt == OSAL_NULL)
                return ECORE_AGAIN;

        if (!ECORE_IS_CMT(p_dev))
                goto out;

        rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
        if (rc != ECORE_SUCCESS)
                goto out;

        switch (eng) {
        case ECORE_ENG0:
                eng_sel = 0;
                break;
        case ECORE_ENG1:
                eng_sel = 1;
                break;
        case ECORE_BOTH_ENG:
                eng_sel = 2;
                break;
        default:
                DP_NOTICE(p_dev, false,
                          "Invalid affinity value for ppfid [%d]\n", eng);
                rc = ECORE_INVAL;
                goto out;
        }

        addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
        val = ecore_rd(p_hwfn, p_ptt, addr);
        SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE, eng_sel);
        ecore_wr(p_hwfn, p_ptt, addr, val);

        /* The iWARP affinity is set as the affinity of ppfid 0 */
        if (!ppfid && ECORE_IS_IWARP_PERSONALITY(p_hwfn))
                p_dev->iwarp_affin = (eng == ECORE_ENG1) ? 1 : 0;
out:
        ecore_ptt_release(p_hwfn, p_ptt);

        return rc;
}

enum _ecore_status_t ecore_llh_set_roce_affinity(struct ecore_dev *p_dev,
                                                 enum ecore_eng eng)
{
        struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
        struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
        u32 addr, val, eng_sel;
        enum _ecore_status_t rc = ECORE_SUCCESS;
        u8 ppfid, abs_ppfid;

        if (p_ptt == OSAL_NULL)
                return ECORE_AGAIN;

        if (!ECORE_IS_CMT(p_dev))
                goto out;

        switch (eng) {
        case ECORE_ENG0:
                eng_sel = 0;
                break;
        case ECORE_ENG1:
                eng_sel = 1;
                break;
        case ECORE_BOTH_ENG:
                eng_sel = 2;
                ecore_wr(p_hwfn, p_ptt, NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL,
                         0xf /* QP bit 15 */);
                break;
        default:
                DP_NOTICE(p_dev, false,
                          "Invalid affinity value for RoCE [%d]\n", eng);
                rc = ECORE_INVAL;
                goto out;
        }

        for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
                rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
                if (rc != ECORE_SUCCESS)
                        goto out;

                addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
                val = ecore_rd(p_hwfn, p_ptt, addr);
                SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_ROCE, eng_sel);
                ecore_wr(p_hwfn, p_ptt, addr, val);
        }
out:
        ecore_ptt_release(p_hwfn, p_ptt);

        return rc;
}

struct ecore_llh_filter_details {
        u64 value;
        u32 mode;
        u32 protocol_type;
        u32 hdr_sel;
        u32 enable;
};

static enum _ecore_status_t
ecore_llh_access_filter(struct ecore_hwfn *p_hwfn,
                        struct ecore_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx,
                        struct ecore_llh_filter_details *p_details,
                        bool b_write_access)
{
        u8 pfid = ECORE_PFID_BY_PPFID(p_hwfn, abs_ppfid);
        struct dmae_params params;
        enum _ecore_status_t rc;
        u32 addr;

        /* The NIG/LLH registers that are accessed in this function have only 16
         * rows which are exposed to a PF. I.e. only the 16 filters of its
         * default ppfid
         * Accessing filters of other ppfids requires pretending to other PFs,
         * and thus the usage of the ecore_ppfid_rd/wr() functions.
         */

        /* Filter enable - should be done first when removing a filter */
        if (b_write_access && !p_details->enable) {
                addr = NIG_REG_LLH_FUNC_FILTER_EN + filter_idx * 0x4;
                ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,
                               p_details->enable);
        }

        /* Filter value */
        addr = NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * filter_idx * 0x4;
        OSAL_MEMSET(&params, 0, sizeof(params));

        if (b_write_access) {
                SET_FIELD(params.flags, DMAE_PARAMS_DST_PF_VALID, 0x1);
                params.dst_pf_id = pfid;
                rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
                                         (u64)(osal_uintptr_t)&p_details->value,
                                         addr, 2 /* size_in_dwords */, &params);
        } else {
                SET_FIELD(params.flags, DMAE_PARAMS_SRC_PF_VALID, 0x1);
                SET_FIELD(params.flags, DMAE_PARAMS_COMPLETION_DST, 0x1);
                params.src_pf_id = pfid;
                rc = ecore_dmae_grc2host(p_hwfn, p_ptt, addr,
                                         (u64)(osal_uintptr_t)&p_details->value,
                                         2 /* size_in_dwords */, &params);
        }

        if (rc != ECORE_SUCCESS)
                return rc;

        /* Filter mode */
        addr = NIG_REG_LLH_FUNC_FILTER_MODE + filter_idx * 0x4;
        if (b_write_access)
                ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr, p_details->mode);

        else
                p_details->mode = ecore_ppfid_rd(p_hwfn, p_ptt, abs_ppfid,
                                                 addr);

        /* Filter protocol type */
        addr = NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + filter_idx * 0x4;
        if (b_write_access)
                ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,
                               p_details->protocol_type);
        else
                p_details->protocol_type = ecore_ppfid_rd(p_hwfn, p_ptt,
                                                          abs_ppfid, addr);

        /* Filter header select */
        addr = NIG_REG_LLH_FUNC_FILTER_HDR_SEL + filter_idx * 0x4;
        if (b_write_access)
                ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,
                               p_details->hdr_sel);
        else
                p_details->hdr_sel = ecore_ppfid_rd(p_hwfn, p_ptt, abs_ppfid,
                                                    addr);

        /* Filter enable - should be done last when adding a filter */
        if (!b_write_access || p_details->enable) {
                addr = NIG_REG_LLH_FUNC_FILTER_EN + filter_idx * 0x4;
                if (b_write_access)
                        ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,
                                       p_details->enable);
                else
                        p_details->enable = ecore_ppfid_rd(p_hwfn, p_ptt,
                                                           abs_ppfid, addr);
        }

        return ECORE_SUCCESS;
}

static enum _ecore_status_t
ecore_llh_add_filter(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
                        u8 abs_ppfid, u8 filter_idx, u8 filter_prot_type,
                        u32 high, u32 low)
{
        struct ecore_llh_filter_details filter_details;

        filter_details.enable = 1;
        filter_details.value = ((u64)high << 32) | low;
        filter_details.hdr_sel =
                OSAL_GET_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits) ?
                1 : /* inner/encapsulated header */
                0;  /* outer/tunnel header */
        filter_details.protocol_type = filter_prot_type;
        filter_details.mode = filter_prot_type ?
                              1 : /* protocol-based classification */
                              0;  /* MAC-address based classification */

        return ecore_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
                                &filter_details,
                                true /* write access */);
}

static enum _ecore_status_t
ecore_llh_remove_filter(struct ecore_hwfn *p_hwfn,
                           struct ecore_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx)
{
        struct ecore_llh_filter_details filter_details;

        OSAL_MEMSET(&filter_details, 0, sizeof(filter_details));

        return ecore_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
                                       &filter_details,
                                       true /* write access */);
}

enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_dev *p_dev, u8 ppfid,
                                              u8 mac_addr[ETH_ALEN])
{
        struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
        struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
        union ecore_llh_filter filter;
        u8 filter_idx, abs_ppfid;
        u32 high, low, ref_cnt;
        enum _ecore_status_t rc = ECORE_SUCCESS;

        if (p_ptt == OSAL_NULL)
                return ECORE_AGAIN;

        if (!OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
                goto out;

        OSAL_MEM_ZERO(&filter, sizeof(filter));
        OSAL_MEMCPY(filter.mac.addr, mac_addr, ETH_ALEN);
        rc = ecore_llh_shadow_add_filter(p_dev, ppfid,
                                         ECORE_LLH_FILTER_TYPE_MAC,
                                         &filter, &filter_idx, &ref_cnt);
        if (rc != ECORE_SUCCESS)
                goto err;

        rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
        if (rc != ECORE_SUCCESS)
                goto err;

        /* Configure the LLH only in case of a new the filter */
        if (ref_cnt == 1) {
                high = mac_addr[1] | (mac_addr[0] << 8);
                low = mac_addr[5] | (mac_addr[4] << 8) | (mac_addr[3] << 16) |
                      (mac_addr[2] << 24);
                rc = ecore_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
                                          0, high, low);
                if (rc != ECORE_SUCCESS)
                        goto err;
        }

        DP_VERBOSE(p_dev, ECORE_MSG_SP,
                   "LLH: Added MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
                   mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
                   mac_addr[4], mac_addr[5], ppfid, abs_ppfid, filter_idx,
                   ref_cnt);

        goto out;

err:
        DP_NOTICE(p_dev, false,
                  "LLH: Failed to add MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] to ppfid %hhd\n",
                  mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
                  mac_addr[4], mac_addr[5], ppfid);
out:
        ecore_ptt_release(p_hwfn, p_ptt);

        return rc;
}

static enum _ecore_status_t
ecore_llh_protocol_filter_stringify(struct ecore_dev *p_dev,
                                    enum ecore_llh_prot_filter_type_t type,
                                    u16 source_port_or_eth_type, u16 dest_port,
                                    char *str, osal_size_t str_len)
{
        switch (type) {
        case ECORE_LLH_FILTER_ETHERTYPE:
                OSAL_SNPRINTF(str, str_len, "Ethertype 0x%04x",
                              source_port_or_eth_type);
                break;
        case ECORE_LLH_FILTER_TCP_SRC_PORT:
                OSAL_SNPRINTF(str, str_len, "TCP src port 0x%04x",
                              source_port_or_eth_type);
                break;
        case ECORE_LLH_FILTER_UDP_SRC_PORT:
                OSAL_SNPRINTF(str, str_len, "UDP src port 0x%04x",
                              source_port_or_eth_type);
                break;
        case ECORE_LLH_FILTER_TCP_DEST_PORT:
                OSAL_SNPRINTF(str, str_len, "TCP dst port 0x%04x", dest_port);
                break;
        case ECORE_LLH_FILTER_UDP_DEST_PORT:
                OSAL_SNPRINTF(str, str_len, "UDP dst port 0x%04x", dest_port);
                break;
        case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
                OSAL_SNPRINTF(str, str_len, "TCP src/dst ports 0x%04x/0x%04x",
                              source_port_or_eth_type, dest_port);
                break;
        case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
                OSAL_SNPRINTF(str, str_len, "UDP src/dst ports 0x%04x/0x%04x",
                              source_port_or_eth_type, dest_port);
                break;
        default:
                DP_NOTICE(p_dev, true,
                          "Non valid LLH protocol filter type %d\n", type);
                return ECORE_INVAL;
        }

        return ECORE_SUCCESS;
}

static enum _ecore_status_t
ecore_llh_protocol_filter_to_hilo(struct ecore_dev *p_dev,
                                  enum ecore_llh_prot_filter_type_t type,
                                  u16 source_port_or_eth_type, u16 dest_port,
                                  u32 *p_high, u32 *p_low)
{
        *p_high = 0;
        *p_low = 0;

        switch (type) {
        case ECORE_LLH_FILTER_ETHERTYPE:
                *p_high = source_port_or_eth_type;
                break;
        case ECORE_LLH_FILTER_TCP_SRC_PORT:
        case ECORE_LLH_FILTER_UDP_SRC_PORT:
                *p_low = source_port_or_eth_type << 16;
                break;
        case ECORE_LLH_FILTER_TCP_DEST_PORT:
        case ECORE_LLH_FILTER_UDP_DEST_PORT:
                *p_low = dest_port;
                break;
        case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
        case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
                *p_low = (source_port_or_eth_type << 16) | dest_port;
                break;
        default:
                DP_NOTICE(p_dev, true,
                          "Non valid LLH protocol filter type %d\n", type);
                return ECORE_INVAL;
        }

        return ECORE_SUCCESS;
}

enum _ecore_status_t
ecore_llh_add_protocol_filter(struct ecore_dev *p_dev, u8 ppfid,
                              enum ecore_llh_prot_filter_type_t type,
                              u16 source_port_or_eth_type, u16 dest_port)
{
        struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
        struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
        u8 filter_idx, abs_ppfid, type_bitmap;
        char str[32];
        union ecore_llh_filter filter;
        u32 high, low, ref_cnt;
        enum _ecore_status_t rc = ECORE_SUCCESS;

        if (p_ptt == OSAL_NULL)
                return ECORE_AGAIN;

        if (!OSAL_GET_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))
                goto out;

        rc = ecore_llh_protocol_filter_stringify(p_dev, type,
                                                 source_port_or_eth_type,
                                                 dest_port, str, sizeof(str));
        if (rc != ECORE_SUCCESS)
                goto err;

        OSAL_MEM_ZERO(&filter, sizeof(filter));
        filter.protocol.type = type;
        filter.protocol.source_port_or_eth_type = source_port_or_eth_type;
        filter.protocol.dest_port = dest_port;
        rc = ecore_llh_shadow_add_filter(p_dev, ppfid,
                                         ECORE_LLH_FILTER_TYPE_PROTOCOL,
                                         &filter, &filter_idx, &ref_cnt);
        if (rc != ECORE_SUCCESS)
                goto err;

        rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
        if (rc != ECORE_SUCCESS)
                goto err;

        /* Configure the LLH only in case of a new the filter */
        if (ref_cnt == 1) {
                rc = ecore_llh_protocol_filter_to_hilo(p_dev, type,
                                                       source_port_or_eth_type,
                                                       dest_port, &high, &low);
                if (rc != ECORE_SUCCESS)
                        goto err;

                type_bitmap = 0x1 << type;
                rc = ecore_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
                                          type_bitmap, high, low);
                if (rc != ECORE_SUCCESS)
                        goto err;
        }

        DP_VERBOSE(p_dev, ECORE_MSG_SP,
                   "LLH: Added protocol filter [%s] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
                   str, ppfid, abs_ppfid, filter_idx, ref_cnt);

        goto out;

err:
        DP_NOTICE(p_hwfn, false,
                  "LLH: Failed to add protocol filter [%s] to ppfid %hhd\n",
                  str, ppfid);
out:
        ecore_ptt_release(p_hwfn, p_ptt);

        return rc;
}

void ecore_llh_remove_mac_filter(struct ecore_dev *p_dev, u8 ppfid,
                                 u8 mac_addr[ETH_ALEN])
{
        struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
        struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
        union ecore_llh_filter filter;
        u8 filter_idx, abs_ppfid;
        enum _ecore_status_t rc = ECORE_SUCCESS;
        u32 ref_cnt;

        if (p_ptt == OSAL_NULL)
                return;

        if (!OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
                goto out;

        OSAL_MEM_ZERO(&filter, sizeof(filter));
        OSAL_MEMCPY(filter.mac.addr, mac_addr, ETH_ALEN);
        rc = ecore_llh_shadow_remove_filter(p_dev, ppfid, &filter, &filter_idx,
                                            &ref_cnt);
        if (rc != ECORE_SUCCESS)
                goto err;

        rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
        if (rc != ECORE_SUCCESS)
                goto err;

        /* Remove from the LLH in case the filter is not in use */
        if (!ref_cnt) {
                rc = ecore_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid,
                                             filter_idx);
                if (rc != ECORE_SUCCESS)
                        goto err;
        }

        DP_VERBOSE(p_dev, ECORE_MSG_SP,
                   "LLH: Removed MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
                   mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
                   mac_addr[4], mac_addr[5], ppfid, abs_ppfid, filter_idx,
                   ref_cnt);

        goto out;

err:
        DP_NOTICE(p_dev, false,
                  "LLH: Failed to remove MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] from ppfid %hhd\n",
                  mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
                  mac_addr[4], mac_addr[5], ppfid);
out:
        ecore_ptt_release(p_hwfn, p_ptt);
}

void ecore_llh_remove_protocol_filter(struct ecore_dev *p_dev, u8 ppfid,
                                      enum ecore_llh_prot_filter_type_t type,
                                      u16 source_port_or_eth_type,
                                      u16 dest_port)
{
        struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
        struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
        u8 filter_idx, abs_ppfid;
        char str[32];
        union ecore_llh_filter filter;
        enum _ecore_status_t rc = ECORE_SUCCESS;
        u32 ref_cnt;

        if (p_ptt == OSAL_NULL)
                return;

        if (!OSAL_GET_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))
                goto out;

        rc = ecore_llh_protocol_filter_stringify(p_dev, type,
                                                 source_port_or_eth_type,
                                                 dest_port, str, sizeof(str));
        if (rc != ECORE_SUCCESS)
                goto err;

        OSAL_MEM_ZERO(&filter, sizeof(filter));
        filter.protocol.type = type;
        filter.protocol.source_port_or_eth_type = source_port_or_eth_type;
        filter.protocol.dest_port = dest_port;
        rc = ecore_llh_shadow_remove_filter(p_dev, ppfid, &filter, &filter_idx,
                                            &ref_cnt);
        if (rc != ECORE_SUCCESS)
                goto err;

        rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
        if (rc != ECORE_SUCCESS)
                goto err;

        /* Remove from the LLH in case the filter is not in use */
        if (!ref_cnt) {
                rc = ecore_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid,
                                             filter_idx);
                if (rc != ECORE_SUCCESS)
                        goto err;
        }

        DP_VERBOSE(p_dev, ECORE_MSG_SP,
                   "LLH: Removed protocol filter [%s] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
                   str, ppfid, abs_ppfid, filter_idx, ref_cnt);

        goto out;

err:
        DP_NOTICE(p_dev, false,
                  "LLH: Failed to remove protocol filter [%s] from ppfid %hhd\n",
                  str, ppfid);
out:
        ecore_ptt_release(p_hwfn, p_ptt);
}

void ecore_llh_clear_ppfid_filters(struct ecore_dev *p_dev, u8 ppfid)
{
        struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
        struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
        u8 filter_idx, abs_ppfid;
        enum _ecore_status_t rc = ECORE_SUCCESS;

        if (p_ptt == OSAL_NULL)
                return;

        if (!OSAL_GET_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&
            !OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
                goto out;

        rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
        if (rc != ECORE_SUCCESS)
                goto out;

        rc = ecore_llh_shadow_remove_all_filters(p_dev, ppfid);
        if (rc != ECORE_SUCCESS)
                goto out;

        for (filter_idx = 0; filter_idx < NIG_REG_LLH_FUNC_FILTER_EN_SIZE;
             filter_idx++) {
                rc = ecore_llh_remove_filter(p_hwfn, p_ptt,
                                                abs_ppfid, filter_idx);
                if (rc != ECORE_SUCCESS)
                        goto out;
        }
out:
        ecore_ptt_release(p_hwfn, p_ptt);
}

void ecore_llh_clear_all_filters(struct ecore_dev *p_dev)
{
        u8 ppfid;

        if (!OSAL_GET_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&
            !OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
                return;

        for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++)
                ecore_llh_clear_ppfid_filters(p_dev, ppfid);
}

enum _ecore_status_t ecore_all_ppfids_wr(struct ecore_hwfn *p_hwfn,
                                         struct ecore_ptt *p_ptt, u32 addr,
                                         u32 val)
{
        struct ecore_dev *p_dev = p_hwfn->p_dev;
        u8 ppfid, abs_ppfid;
        enum _ecore_status_t rc;

        for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
                rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
                if (rc != ECORE_SUCCESS)
                        return rc;

                ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr, val);
        }

        return ECORE_SUCCESS;
}

enum _ecore_status_t
ecore_llh_dump_ppfid(struct ecore_dev *p_dev, u8 ppfid)
{
        struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
        struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
        struct ecore_llh_filter_details filter_details;
        u8 abs_ppfid, filter_idx;
        u32 addr;
        enum _ecore_status_t rc;

        if (!p_ptt)
                return ECORE_AGAIN;

        rc = ecore_abs_ppfid(p_hwfn->p_dev, ppfid, &abs_ppfid);
        if (rc != ECORE_SUCCESS)
                goto out;

        addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
        DP_NOTICE(p_hwfn, false,
                  "[rel_pf_id %hhd, ppfid={rel %hhd, abs %hhd}, engine_sel 0x%x]\n",
                  p_hwfn->rel_pf_id, ppfid, abs_ppfid,
                  ecore_rd(p_hwfn, p_ptt, addr));

        for (filter_idx = 0; filter_idx < NIG_REG_LLH_FUNC_FILTER_EN_SIZE;
             filter_idx++) {
                OSAL_MEMSET(&filter_details, 0, sizeof(filter_details));
                rc =  ecore_llh_access_filter(p_hwfn, p_ptt, abs_ppfid,
                                              filter_idx, &filter_details,
                                              false /* read access */);
                if (rc != ECORE_SUCCESS)
                        goto out;

                DP_NOTICE(p_hwfn, false,
                          "filter %2hhd: enable %d, value 0x%016lx, mode %d, protocol_type 0x%x, hdr_sel 0x%x\n",
                          filter_idx, filter_details.enable,
                          (unsigned long)filter_details.value,
                          filter_details.mode,
                          filter_details.protocol_type, filter_details.hdr_sel);
        }


out:
        ecore_ptt_release(p_hwfn, p_ptt);

        return rc;
}

enum _ecore_status_t ecore_llh_dump_all(struct ecore_dev *p_dev)
{
        u8 ppfid;
        enum _ecore_status_t rc;

        for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
                rc = ecore_llh_dump_ppfid(p_dev, ppfid);
                if (rc != ECORE_SUCCESS)
                        return rc;
        }

        return ECORE_SUCCESS;
}

/******************************* NIG LLH - End ********************************/

/* Configurable */
#define ECORE_MIN_DPIS          (4)     /* The minimal num of DPIs required to
                                         * load the driver. The number was
                                         * arbitrarily set.
                                         */

/* Derived */
#define ECORE_MIN_PWM_REGION    (ECORE_WID_SIZE * ECORE_MIN_DPIS)

static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn,
                             struct ecore_ptt *p_ptt,
                             enum BAR_ID bar_id)
{
        u32 bar_reg = (bar_id == BAR_ID_0 ?
                       PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
        u32 val;

        if (IS_VF(p_hwfn->p_dev))
                return ecore_vf_hw_bar_size(p_hwfn, bar_id);

        val = ecore_rd(p_hwfn, p_ptt, bar_reg);
        if (val)
                return 1 << (val + 15);

        /* The above registers were updated in the past only in CMT mode. Since
         * they were found to be useful MFW started updating them from 8.7.7.0.
         * In older MFW versions they are set to 0 which means disabled.
         */
        if (ECORE_IS_CMT(p_hwfn->p_dev)) {
                DP_INFO(p_hwfn,
                        "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
                val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
        } else {
                DP_INFO(p_hwfn,
                        "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
                val = 512 * 1024;
        }

        return val;
}

void ecore_init_dp(struct ecore_dev *p_dev,
                   u32 dp_module, u8 dp_level, void *dp_ctx)
{
        u32 i;

        p_dev->dp_level = dp_level;
        p_dev->dp_module = dp_module;
        p_dev->dp_ctx = dp_ctx;
        for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
                struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];

                p_hwfn->dp_level = dp_level;
                p_hwfn->dp_module = dp_module;
                p_hwfn->dp_ctx = dp_ctx;
        }
}

enum _ecore_status_t ecore_init_struct(struct ecore_dev *p_dev)
{
        u8 i;

        for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
                struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];

                p_hwfn->p_dev = p_dev;
                p_hwfn->my_id = i;
                p_hwfn->b_active = false;

#ifdef CONFIG_ECORE_LOCK_ALLOC
                if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->dmae_info.lock))
                        goto handle_err;
#endif
                OSAL_SPIN_LOCK_INIT(&p_hwfn->dmae_info.lock);
        }

        /* hwfn 0 is always active */
        p_dev->hwfns[0].b_active = true;

        /* set the default cache alignment to 128 (may be overridden later) */
        p_dev->cache_shift = 7;
        return ECORE_SUCCESS;
#ifdef CONFIG_ECORE_LOCK_ALLOC
handle_err:
        while (--i) {
                struct ecore_hwfn *p_hwfn = OSAL_NULL;

                p_hwfn = &p_dev->hwfns[i];
                OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock);
        }
        return ECORE_NOMEM;
#endif
}

static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
{
        struct ecore_qm_info *qm_info = &p_hwfn->qm_info;

        OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
        OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
        OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
        OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
}

static void ecore_dbg_user_data_free(struct ecore_hwfn *p_hwfn)
{
        OSAL_FREE(p_hwfn->p_dev, p_hwfn->dbg_user_info);
        p_hwfn->dbg_user_info = OSAL_NULL;
}

void ecore_resc_free(struct ecore_dev *p_dev)
{
        int i;

        if (IS_VF(p_dev)) {
                for_each_hwfn(p_dev, i)
                        ecore_l2_free(&p_dev->hwfns[i]);
                return;
        }

        OSAL_FREE(p_dev, p_dev->fw_data);

        OSAL_FREE(p_dev, p_dev->reset_stats);

        ecore_llh_free(p_dev);

        for_each_hwfn(p_dev, i) {
                struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];

                ecore_cxt_mngr_free(p_hwfn);
                ecore_qm_info_free(p_hwfn);
                ecore_spq_free(p_hwfn);
                ecore_eq_free(p_hwfn);
                ecore_consq_free(p_hwfn);
                ecore_int_free(p_hwfn);
                ecore_iov_free(p_hwfn);
                ecore_l2_free(p_hwfn);
                ecore_dmae_info_free(p_hwfn);
                ecore_dcbx_info_free(p_hwfn);
                ecore_dbg_user_data_free(p_hwfn);
                ecore_fw_overlay_mem_free(p_hwfn, p_hwfn->fw_overlay_mem);
                /* @@@TBD Flush work-queue ? */

                /* destroy doorbell recovery mechanism */
                ecore_db_recovery_teardown(p_hwfn);
        }
}

/******************** QM initialization *******************/

/* bitmaps for indicating active traffic classes.
 * Special case for Arrowhead 4 port
 */
/* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
#define ACTIVE_TCS_BMAP 0x9f
/* 0..3 actually used, OOO and high priority stuff all use 3 */
#define ACTIVE_TCS_BMAP_4PORT_K2 0xf

/* determines the physical queue flags for a given PF. */
static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
{
        u32 flags;

        /* common flags */
        flags = PQ_FLAGS_LB;

        /* feature flags */
        if (IS_ECORE_SRIOV(p_hwfn->p_dev))
                flags |= PQ_FLAGS_VFS;
        if (IS_ECORE_PACING(p_hwfn))
                flags |= PQ_FLAGS_RLS;

        /* protocol flags */
        switch (p_hwfn->hw_info.personality) {
        case ECORE_PCI_ETH:
                if (!IS_ECORE_PACING(p_hwfn))
                        flags |= PQ_FLAGS_MCOS;
                break;
        case ECORE_PCI_FCOE:
                flags |= PQ_FLAGS_OFLD;
                break;
        case ECORE_PCI_ISCSI:
                flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
                break;
        case ECORE_PCI_ETH_ROCE:
                flags |= PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
                if (!IS_ECORE_PACING(p_hwfn))
                        flags |= PQ_FLAGS_MCOS;
                break;
        case ECORE_PCI_ETH_IWARP:
                flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
                if (!IS_ECORE_PACING(p_hwfn))
                        flags |= PQ_FLAGS_MCOS;
                break;
        default:
                DP_ERR(p_hwfn, "unknown personality %d\n",
                       p_hwfn->hw_info.personality);
                return 0;
        }
        return flags;
}

/* Getters for resource amounts necessary for qm initialization */
u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
{
        return p_hwfn->hw_info.num_hw_tc;
}

u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
{
        return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
                        p_hwfn->p_dev->p_iov_info->total_vfs : 0;
}

#define NUM_DEFAULT_RLS 1

u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
{
        u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);

        /* num RLs can't exceed resource amount of rls or vports or the
         * dcqcn qps
         */
        num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
                                     RESC_NUM(p_hwfn, ECORE_VPORT));

        /* make sure after we reserve the default and VF rls we'll have
         * something left
         */
        if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
                DP_NOTICE(p_hwfn, false,
                          "no rate limiters left for PF rate limiting"
                          " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
                return 0;
        }

        /* subtract rls necessary for VFs and one default one for the PF */
        num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;

        return num_pf_rls;
}

u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
{
        u32 pq_flags = ecore_get_pq_flags(p_hwfn);

        /* all pqs share the same vport (hence the 1 below), except for vfs
         * and pf_rl pqs
         */
        return (!!(PQ_FLAGS_RLS & pq_flags)) *
                ecore_init_qm_get_num_pf_rls(p_hwfn) +
               (!!(PQ_FLAGS_VFS & pq_flags)) *
                ecore_init_qm_get_num_vfs(p_hwfn) + 1;
}

/* calc amount of PQs according to the requested flags */
u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
{
        u32 pq_flags = ecore_get_pq_flags(p_hwfn);

        return (!!(PQ_FLAGS_RLS & pq_flags)) *
                ecore_init_qm_get_num_pf_rls(p_hwfn) +
               (!!(PQ_FLAGS_MCOS & pq_flags)) *
                ecore_init_qm_get_num_tcs(p_hwfn) +
               (!!(PQ_FLAGS_LB & pq_flags)) +
               (!!(PQ_FLAGS_OOO & pq_flags)) +
               (!!(PQ_FLAGS_ACK & pq_flags)) +
               (!!(PQ_FLAGS_OFLD & pq_flags)) +
               (!!(PQ_FLAGS_VFS & pq_flags)) *
                ecore_init_qm_get_num_vfs(p_hwfn);
}

/* initialize the top level QM params */
static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
{
        struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
        bool four_port;

        /* pq and vport bases for this PF */
        qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
        qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);

        /* rate limiting and weighted fair queueing are always enabled */
        qm_info->vport_rl_en = 1;
        qm_info->vport_wfq_en = 1;

        /* TC config is different for AH 4 port */
        four_port = p_hwfn->p_dev->num_ports_in_engine == MAX_NUM_PORTS_K2;

        /* in AH 4 port we have fewer TCs per port */
        qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
                                                     NUM_OF_PHYS_TCS;

        /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
         * 4 otherwise
         */
        if (!qm_info->ooo_tc)
                qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
                                              DCBX_TCP_OOO_TC;
}

/* initialize qm vport params */
static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
{
        struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
        u8 i;

        /* all vports participate in weighted fair queueing */
        for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
                qm_info->qm_vport_params[i].wfq = 1;
}

/* initialize qm port params */
static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
{
        /* Initialize qm port parameters */
        u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engine;
        struct ecore_dev *p_dev = p_hwfn->p_dev;

        /* indicate how ooo and high pri traffic is dealt with */
        active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
                ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;

        for (i = 0; i < num_ports; i++) {
                struct init_qm_port_params *p_qm_port =
                        &p_hwfn->qm_info.qm_port_params[i];
                u16 pbf_max_cmd_lines;

                p_qm_port->active = 1;
                p_qm_port->active_phys_tcs = active_phys_tcs;
                pbf_max_cmd_lines = (u16)NUM_OF_PBF_CMD_LINES(p_dev);
                p_qm_port->num_pbf_cmd_lines = pbf_max_cmd_lines / num_ports;
                p_qm_port->num_btb_blocks =
                        NUM_OF_BTB_BLOCKS(p_dev) / num_ports;
        }
}

/* Reset the params which must be reset for qm init. QM init may be called as
 * a result of flows other than driver load (e.g. dcbx renegotiation). Other
 * params may be affected by the init but would simply recalculate to the same
 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
 * affected as these amounts stay the same.
 */
static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
{
        struct ecore_qm_info *qm_info = &p_hwfn->qm_info;

        qm_info->num_pqs = 0;
        qm_info->num_vports = 0;
        qm_info->num_pf_rls = 0;
        qm_info->num_vf_pqs = 0;
        qm_info->first_vf_pq = 0;
        qm_info->first_mcos_pq = 0;
        qm_info->first_rl_pq = 0;
}

static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
{
        struct ecore_qm_info *qm_info = &p_hwfn->qm_info;

        qm_info->num_vports++;

        if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
                DP_ERR(p_hwfn,
                       "vport overflow! qm_info->num_vports %d,"
                       " qm_init_get_num_vports() %d\n",
                       qm_info->num_vports,
                       ecore_init_qm_get_num_vports(p_hwfn));
}

/* initialize a single pq and manage qm_info resources accounting.
 * The pq_init_flags param determines whether the PQ is rate limited
 * (for VF or PF)
 * and whether a new vport is allocated to the pq or not (i.e. vport will be
 * shared)
 */

/* flags for pq init */
#define PQ_INIT_SHARE_VPORT     (1 << 0)
#define PQ_INIT_PF_RL           (1 << 1)
#define PQ_INIT_VF_RL           (1 << 2)

/* defines for pq init */
#define PQ_INIT_DEFAULT_WRR_GROUP       1
#define PQ_INIT_DEFAULT_TC              0
#define PQ_INIT_OFLD_TC                 (p_hwfn->hw_info.offload_tc)

static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
                             struct ecore_qm_info *qm_info,
                             u8 tc, u32 pq_init_flags)
{
        u16 pq_idx = qm_info->num_pqs, max_pq =
                                        ecore_init_qm_get_num_pqs(p_hwfn);

        if (pq_idx > max_pq)
                DP_ERR(p_hwfn,
                       "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);

        /* init pq params */
        qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
        qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
                                                 qm_info->num_vports;
        qm_info->qm_pq_params[pq_idx].tc_id = tc;
        qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
        qm_info->qm_pq_params[pq_idx].rl_valid =
                (pq_init_flags & PQ_INIT_PF_RL ||
                 pq_init_flags & PQ_INIT_VF_RL);

        /* The "rl_id" is set as the "vport_id" */
        qm_info->qm_pq_params[pq_idx].rl_id =
                qm_info->qm_pq_params[pq_idx].vport_id;

        /* qm params accounting */
        qm_info->num_pqs++;
        if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
                qm_info->num_vports++;

        if (pq_init_flags & PQ_INIT_PF_RL)
                qm_info->num_pf_rls++;

        if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
                DP_ERR(p_hwfn,
                       "vport overflow! qm_info->num_vports %d,"
                       " qm_init_get_num_vports() %d\n",
                       qm_info->num_vports,
                       ecore_init_qm_get_num_vports(p_hwfn));

        if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
                DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
                       " qm_init_get_num_pf_rls() %d\n",
                       qm_info->num_pf_rls,
                       ecore_init_qm_get_num_pf_rls(p_hwfn));
}

/* get pq index according to PQ_FLAGS */
static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
                                             u32 pq_flags)
{
        struct ecore_qm_info *qm_info = &p_hwfn->qm_info;

        /* Can't have multiple flags set here */
        if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
                                sizeof(pq_flags)) > 1)
                goto err;

        switch (pq_flags) {
        case PQ_FLAGS_RLS:
                return &qm_info->first_rl_pq;
        case PQ_FLAGS_MCOS:
                return &qm_info->first_mcos_pq;
        case PQ_FLAGS_LB:
                return &qm_info->pure_lb_pq;
        case PQ_FLAGS_OOO:
                return &qm_info->ooo_pq;
        case PQ_FLAGS_ACK:
                return &qm_info->pure_ack_pq;
        case PQ_FLAGS_OFLD:
                return &qm_info->offload_pq;
        case PQ_FLAGS_VFS:
                return &qm_info->first_vf_pq;
        default:
                goto err;
        }

err:
        DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
        return OSAL_NULL;
}

/* save pq index in qm info */
static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
                                  u32 pq_flags, u16 pq_val)
{
        u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);

        *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
}

/* get tx pq index, with the PQ TX base already set (ready for context init) */
u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
{
        u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);

        return *base_pq_idx + CM_TX_PQ_BASE;
}

u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
{
        u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);

        if (tc > max_tc)
                DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);

        return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + (tc % max_tc);
}

u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
{
        u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);

        if (vf > max_vf)
                DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);

        return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + (vf % max_vf);
}

u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl)
{
        u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);

        /* for rate limiters, it is okay to use the modulo behavior - no
         * DP_ERR
         */
        return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + (rl % max_rl);
}

u16 ecore_get_qm_vport_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl)
{
        u16 start_pq, pq, qm_pq_idx;

        pq = ecore_get_cm_pq_idx_rl(p_hwfn, rl);
        start_pq = p_hwfn->qm_info.start_pq;
        qm_pq_idx = pq - start_pq - CM_TX_PQ_BASE;

        if (qm_pq_idx > p_hwfn->qm_info.num_pqs) {
                DP_ERR(p_hwfn,
                       "qm_pq_idx %d must be smaller than %d\n",
                        qm_pq_idx, p_hwfn->qm_info.num_pqs);
        }

        return p_hwfn->qm_info.qm_pq_params[qm_pq_idx].vport_id;
}

/* Functions for creating specific types of pqs */
static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
{
        struct ecore_qm_info *qm_info = &p_hwfn->qm_info;

        if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
                return;

        ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
        ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
}

static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
{
        struct ecore_qm_info *qm_info = &p_hwfn->qm_info;

        if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
                return;

        ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
        ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
}

static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
{
        struct ecore_qm_info *qm_info = &p_hwfn->qm_info;

        if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
                return;

        ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
        ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
}

static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
{
        struct ecore_qm_info *qm_info = &p_hwfn->qm_info;

        if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
                return;

        ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
        ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
}

static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
{
        struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
        u8 tc_idx;

        if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
                return;

        ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
        for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
                ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
}

static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
{
        struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
        u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);

        if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
                return;

        ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);

        qm_info->num_vf_pqs = num_vfs;
        for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
                ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
                                 PQ_INIT_VF_RL);
}

static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
{
        u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
        struct ecore_qm_info *qm_info = &p_hwfn->qm_info;

        if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
                return;

        ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
        for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
                ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
                                 PQ_INIT_PF_RL);
}

static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
{
        /* rate limited pqs, must come first (FW assumption) */
        ecore_init_qm_rl_pqs(p_hwfn);

        /* pqs for multi cos */
        ecore_init_qm_mcos_pqs(p_hwfn);

        /* pure loopback pq */
        ecore_init_qm_lb_pq(p_hwfn);

        /* out of order pq */
        ecore_init_qm_ooo_pq(p_hwfn);

        /* pure ack pq */
        ecore_init_qm_pure_ack_pq(p_hwfn);

        /* pq for offloaded protocol */
        ecore_init_qm_offload_pq(p_hwfn);

        /* done sharing vports */
        ecore_init_qm_advance_vport(p_hwfn);

        /* pqs for vfs */
        ecore_init_qm_vf_pqs(p_hwfn);
}

/* compare values of getters against resources amounts */
static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
{
        if (ecore_init_qm_get_num_vports(p_hwfn) >
            RESC_NUM(p_hwfn, ECORE_VPORT)) {
                DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
                return ECORE_INVAL;
        }

        if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
                DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
                return ECORE_INVAL;
        }

        return ECORE_SUCCESS;
}

/*
 * Function for verbose printing of the qm initialization results
 */
static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
{
        struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
        struct init_qm_vport_params *vport;
        struct init_qm_port_params *port;
        struct init_qm_pq_params *pq;
        int i, tc;

        /* top level params */
        DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
                   "qm init top level params: start_pq %d, start_vport %d,"
                   " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
                   qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
                   qm_info->offload_pq, qm_info->pure_ack_pq);
        DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
                   "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
                   " num_vports %d, max_phys_tcs_per_port %d\n",
                   qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
                   qm_info->num_vf_pqs, qm_info->num_vports,
                   qm_info->max_phys_tcs_per_port);
        DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
                   "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
                   " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
                   qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
                   qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
                   qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));

        /* port table */
        for (i = 0; i < p_hwfn->p_dev->num_ports_in_engine; i++) {
                port = &qm_info->qm_port_params[i];
                DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
                           "port idx %d, active %d, active_phys_tcs %d,"
                           " num_pbf_cmd_lines %d, num_btb_blocks %d,"
                           " reserved %d\n",
                           i, port->active, port->active_phys_tcs,
                           port->num_pbf_cmd_lines, port->num_btb_blocks,
                           port->reserved);
        }

        /* vport table */
        for (i = 0; i < qm_info->num_vports; i++) {
                vport = &qm_info->qm_vport_params[i];
                DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "vport idx %d, wfq %d, first_tx_pq_id [ ",
                           qm_info->start_vport + i, vport->wfq);
                for (tc = 0; tc < NUM_OF_TCS; tc++)
                        DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
                                   vport->first_tx_pq_id[tc]);
                DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
        }

        /* pq table */
        for (i = 0; i < qm_info->num_pqs; i++) {
                pq = &qm_info->qm_pq_params[i];
                DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
                           "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d, rl_id %d\n",
                           qm_info->start_pq + i, pq->port_id, pq->vport_id,
                           pq->tc_id, pq->wrr_group, pq->rl_valid, pq->rl_id);
        }
}

static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
{
        /* reset params required for init run */
        ecore_init_qm_reset_params(p_hwfn);

        /* init QM top level params */
        ecore_init_qm_params(p_hwfn);

        /* init QM port params */
        ecore_init_qm_port_params(p_hwfn);

        /* init QM vport params */
        ecore_init_qm_vport_params(p_hwfn);

        /* init QM physical queue params */
        ecore_init_qm_pq_params(p_hwfn);

        /* display all that init */
        ecore_dp_init_qm_params(p_hwfn);
}

/* This function reconfigures the QM pf on the fly.
 * For this purpose we:
 * 1. reconfigure the QM database
 * 2. set new values to runtime array
 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 * 4. activate init tool in QM_PF stage
 * 5. send an sdm_qm_cmd through rbc interface to release the QM
 */
enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
                                     struct ecore_ptt *p_ptt)
{
        struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
        bool b_rc;
        enum _ecore_status_t rc = ECORE_SUCCESS;

        /* multiple flows can issue qm reconf. Need to lock */
        OSAL_SPIN_LOCK(&qm_lock);

        /* initialize ecore's qm data structure */
        ecore_init_qm_info(p_hwfn);

        /* stop PF's qm queues */
        b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
                                      qm_info->start_pq, qm_info->num_pqs);
        if (!b_rc) {
                rc = ECORE_INVAL;
                goto unlock;
        }

        /* clear the QM_PF runtime phase leftovers from previous init */
        ecore_init_clear_rt_data(p_hwfn);

        /* prepare QM portion of runtime array */
        ecore_qm_init_pf(p_hwfn, p_ptt, false);

        /* activate init tool on runtime array */
        rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
                            p_hwfn->hw_info.hw_mode);

        /* start PF's qm queues */
        b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
                                      qm_info->start_pq, qm_info->num_pqs);
        if (!b_rc)
                rc = ECORE_INVAL;

unlock:
        OSAL_SPIN_UNLOCK(&qm_lock);

        return rc;
}

static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
{
        struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
        enum _ecore_status_t rc;

        rc = ecore_init_qm_sanity(p_hwfn);
        if (rc != ECORE_SUCCESS)
                goto alloc_err;

        qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
                                            sizeof(struct init_qm_pq_params) *
                                            ecore_init_qm_get_num_pqs(p_hwfn));
        if (!qm_info->qm_pq_params)
                goto alloc_err;

        qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
                                       sizeof(struct init_qm_vport_params) *
                                       ecore_init_qm_get_num_vports(p_hwfn));
        if (!qm_info->qm_vport_params)
                goto alloc_err;

        qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
                                      sizeof(struct init_qm_port_params) *
                                      p_hwfn->p_dev->num_ports_in_engine);
        if (!qm_info->qm_port_params)
                goto alloc_err;

        qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
                                        sizeof(struct ecore_wfq_data) *
                                        ecore_init_qm_get_num_vports(p_hwfn));
        if (!qm_info->wfq_data)
                goto alloc_err;

        return ECORE_SUCCESS;

alloc_err:
        DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
        ecore_qm_info_free(p_hwfn);
        return ECORE_NOMEM;
}
/******************** End QM initialization ***************/

enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
{
        enum _ecore_status_t rc = ECORE_SUCCESS;
        enum dbg_status debug_status = DBG_STATUS_OK;
        int i;

        if (IS_VF(p_dev)) {
                for_each_hwfn(p_dev, i) {
                        rc = ecore_l2_alloc(&p_dev->hwfns[i]);
                        if (rc != ECORE_SUCCESS)
                                return rc;
                }
                return rc;
        }

        p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
                                     sizeof(*p_dev->fw_data));
        if (!p_dev->fw_data)
                return ECORE_NOMEM;

        for_each_hwfn(p_dev, i) {
                struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
                u32 n_eqes, num_cons;

                /* initialize the doorbell recovery mechanism */
                rc = ecore_db_recovery_setup(p_hwfn);
                if (rc)
                        goto alloc_err;

                /* First allocate the context manager structure */
                rc = ecore_cxt_mngr_alloc(p_hwfn);
                if (rc)
                        goto alloc_err;

                /* Set the HW cid/tid numbers (in the context manager)
                 * Must be done prior to any further computations.
                 */
                rc = ecore_cxt_set_pf_params(p_hwfn);
                if (rc)
                        goto alloc_err;

                rc = ecore_alloc_qm_data(p_hwfn);
                if (rc)
                        goto alloc_err;

                /* init qm info */
                ecore_init_qm_info(p_hwfn);

                /* Compute the ILT client partition */
                rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
                if (rc)
                        goto alloc_err;

                /* CID map / ILT shadow table / T2
                 * The talbes sizes are determined by the computations above
                 */
                rc = ecore_cxt_tables_alloc(p_hwfn);
                if (rc)
                        goto alloc_err;

                /* SPQ, must follow ILT because initializes SPQ context */
                rc = ecore_spq_alloc(p_hwfn);
                if (rc)
                        goto alloc_err;

                /* SP status block allocation */
                p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
                                                           RESERVED_PTT_DPC);

                rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
                if (rc)
                        goto alloc_err;

                rc = ecore_iov_alloc(p_hwfn);
                if (rc)
                        goto alloc_err;

                /* EQ */
                n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
                if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
                        /* Calculate the EQ size
                         * ---------------------
                         * Each ICID may generate up to one event at a time i.e.
                         * the event must be handled/cleared before a new one
                         * can be generated. We calculate the sum of events per
                         * protocol and create an EQ deep enough to handle the
                         * worst case:
                         * - Core - according to SPQ.
                         * - RoCE - per QP there are a couple of ICIDs, one
                         *        responder and one requester, each can
                         *        generate an EQE => n_eqes_qp = 2 * n_qp.
                         *        Each CQ can generate an EQE. There are 2 CQs
                         *        per QP => n_eqes_cq = 2 * n_qp.
                         *        Hence the RoCE total is 4 * n_qp or
                         *        2 * num_cons.
                         * - ENet - There can be up to two events per VF. One
                         *        for VF-PF channel and another for VF FLR
                         *        initial cleanup. The number of VFs is
                         *        bounded by MAX_NUM_VFS_BB, and is much
                         *        smaller than RoCE's so we avoid exact
                         *        calculation.
                         */
                        if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
                                num_cons =
                                    ecore_cxt_get_proto_cid_count(
                                                p_hwfn,
                                                PROTOCOLID_ROCE,
                                                OSAL_NULL);
                                num_cons *= 2;
                        } else {
                                num_cons = ecore_cxt_get_proto_cid_count(
                                                p_hwfn,
                                                PROTOCOLID_IWARP,
                                                OSAL_NULL);
                        }
                        n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
                } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
                        num_cons =
                            ecore_cxt_get_proto_cid_count(p_hwfn,
                                                          PROTOCOLID_ISCSI,
                                                          OSAL_NULL);
                        n_eqes += 2 * num_cons;
                }

                if (n_eqes > 0xFFFF) {
                        DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
                                       "The maximum of a u16 chain is 0x%x\n",
                               n_eqes, 0xFFFF);
                        goto alloc_no_mem;
                }

                rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
                if (rc)
                        goto alloc_err;

                rc = ecore_consq_alloc(p_hwfn);
                if (rc)
                        goto alloc_err;

                rc = ecore_l2_alloc(p_hwfn);
                if (rc != ECORE_SUCCESS)
                        goto alloc_err;

                /* DMA info initialization */
                rc = ecore_dmae_info_alloc(p_hwfn);
                if (rc) {
                        DP_NOTICE(p_hwfn, false, "Failed to allocate memory for dmae_info structure\n");
                        goto alloc_err;
                }

                /* DCBX initialization */
                rc = ecore_dcbx_info_alloc(p_hwfn);
                if (rc) {
                        DP_NOTICE(p_hwfn, false,
                                  "Failed to allocate memory for dcbx structure\n");
                        goto alloc_err;
                }

                debug_status = OSAL_DBG_ALLOC_USER_DATA(p_hwfn,
                                                        &p_hwfn->dbg_user_info);
                if (debug_status) {
                        DP_NOTICE(p_hwfn, false,
                                  "Failed to allocate dbg user info structure\n");
                        rc = (enum _ecore_status_t)debug_status;
                        goto alloc_err;
                }

                debug_status = OSAL_DBG_ALLOC_USER_DATA(p_hwfn,
                                                        &p_hwfn->dbg_user_info);
                if (debug_status) {
                        DP_NOTICE(p_hwfn, false,
                                  "Failed to allocate dbg user info structure\n");
                        rc = (enum _ecore_status_t)debug_status;
                        goto alloc_err;
                }
        } /* hwfn loop */

        rc = ecore_llh_alloc(p_dev);
        if (rc != ECORE_SUCCESS) {
                DP_NOTICE(p_dev, true,
                          "Failed to allocate memory for the llh_info structure\n");
                goto alloc_err;
        }

        p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
                                         sizeof(*p_dev->reset_stats));
        if (!p_dev->reset_stats) {
                DP_NOTICE(p_dev, false, "Failed to allocate reset statistics\n");
                goto alloc_no_mem;
        }

        return ECORE_SUCCESS;

alloc_no_mem:
        rc = ECORE_NOMEM;
alloc_err:
        ecore_resc_free(p_dev);
        return rc;
}

void ecore_resc_setup(struct ecore_dev *p_dev)
{
        int i;

        if (IS_VF(p_dev)) {
                for_each_hwfn(p_dev, i)
                        ecore_l2_setup(&p_dev->hwfns[i]);
                return;
        }

        for_each_hwfn(p_dev, i) {
                struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];

                ecore_cxt_mngr_setup(p_hwfn);
                ecore_spq_setup(p_hwfn);
                ecore_eq_setup(p_hwfn);
                ecore_consq_setup(p_hwfn);

                /* Read shadow of current MFW mailbox */
                ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
                OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
                            p_hwfn->mcp_info->mfw_mb_cur,
                            p_hwfn->mcp_info->mfw_mb_length);

                ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);

                ecore_l2_setup(p_hwfn);
                ecore_iov_setup(p_hwfn);
        }
}

#define FINAL_CLEANUP_POLL_CNT  (100)
#define FINAL_CLEANUP_POLL_TIME (10)
enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
                                         struct ecore_ptt *p_ptt,
                                         u16 id, bool is_vf)
{
        u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
        enum _ecore_status_t rc = ECORE_TIMEOUT;

#ifndef ASIC_ONLY
        if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
            CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
                DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
                return ECORE_SUCCESS;
        }
#endif

        addr = GTT_BAR0_MAP_REG_USDM_RAM +
            USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);

        if (is_vf)
                id += 0x10;

        command |= X_FINAL_CLEANUP_AGG_INT <<
            SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
        command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
        command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
        command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;

/* Make sure notification is not set before initiating final cleanup */

        if (REG_RD(p_hwfn, addr)) {
                DP_NOTICE(p_hwfn, false,
                          "Unexpected; Found final cleanup notification");
                DP_NOTICE(p_hwfn, false,
                          " before initiating final cleanup\n");
                REG_WR(p_hwfn, addr, 0);
        }

        DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
                   "Sending final cleanup for PFVF[%d] [Command %08x]\n",
                   id, command);

        ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);

        /* Poll until completion */
        while (!REG_RD(p_hwfn, addr) && count--)
                OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);

        if (REG_RD(p_hwfn, addr))
                rc = ECORE_SUCCESS;
        else
                DP_NOTICE(p_hwfn, true,
                          "Failed to receive FW final cleanup notification\n");

        /* Cleanup afterwards */
        REG_WR(p_hwfn, addr, 0);

        return rc;
}

static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
{
        int hw_mode = 0;

        if (ECORE_IS_BB(p_hwfn->p_dev)) {
                hw_mode |= 1 << MODE_BB;
        } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
                hw_mode |= 1 << MODE_K2;
        } else {
                DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
                          p_hwfn->p_dev->type);
                return ECORE_INVAL;
        }

        /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
        switch (p_hwfn->p_dev->num_ports_in_engine) {
        case 1:
                hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
                break;
        case 2:
                hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
                break;
        case 4:
                hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
                break;
        default:
                DP_NOTICE(p_hwfn, true,
                          "num_ports_in_engine = %d not supported\n",
                          p_hwfn->p_dev->num_ports_in_engine);
                return ECORE_INVAL;
        }

        if (OSAL_GET_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits))
                hw_mode |= 1 << MODE_MF_SD;
        else
                hw_mode |= 1 << MODE_MF_SI;

#ifndef ASIC_ONLY
        if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
                if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
                        hw_mode |= 1 << MODE_FPGA;
                } else {
                        if (p_hwfn->p_dev->b_is_emul_full)
                                hw_mode |= 1 << MODE_EMUL_FULL;
                        else
                                hw_mode |= 1 << MODE_EMUL_REDUCED;
                }
        } else
#endif
                hw_mode |= 1 << MODE_ASIC;

        if (ECORE_IS_CMT(p_hwfn->p_dev))
                hw_mode |= 1 << MODE_100G;

        p_hwfn->hw_info.hw_mode = hw_mode;

        DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
                   "Configuring function for hw_mode: 0x%08x\n",
                   p_hwfn->hw_info.hw_mode);

        return ECORE_SUCCESS;
}

#ifndef ASIC_ONLY
/* MFW-replacement initializations for emulation */
static enum _ecore_status_t ecore_hw_init_chip(struct ecore_dev *p_dev,
                                               struct ecore_ptt *p_ptt)
{
        struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
        u32 pl_hv, wr_mbs;
        int i, pos;
        u16 ctrl = 0;

        if (!CHIP_REV_IS_EMUL(p_dev)) {
                DP_NOTICE(p_dev, false,
                          "ecore_hw_init_chip() shouldn't be called in a non-emulation environment\n");
                return ECORE_INVAL;
        }

        pl_hv = ECORE_IS_BB(p_dev) ? 0x1 : 0x401;
        ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);

        if (ECORE_IS_AH(p_dev))
                ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2, 0x3ffffff);

        /* Initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
        if (ECORE_IS_BB(p_dev))
                ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);

        if (ECORE_IS_AH(p_dev)) {
                /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
                ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
                         p_dev->num_ports_in_engine >> 1);

                ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
                         p_dev->num_ports_in_engine == 4 ? 0 : 3);
        }

        /* Signal the PSWRQ block to start initializing internal memories */
        ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
        for (i = 0; i < 100; i++) {
                OSAL_UDELAY(50);
                if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
                        break;
        }
        if (i == 100) {
                DP_NOTICE(p_hwfn, true,
                          "RBC done failed to complete in PSWRQ2\n");
                return ECORE_TIMEOUT;
        }

        /* Indicate PSWRQ to initialize steering tag table with zeros */
        ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RESET_STT, 1);
        for (i = 0; i < 100; i++) {
                OSAL_UDELAY(50);
                if (!ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_RESET_STT))
                        break;
        }
        if (i == 100) {
                DP_NOTICE(p_hwfn, true,
                          "Steering tag table initialization failed to complete in PSWRQ2\n");
                return ECORE_TIMEOUT;
        }

        /* Clear a possible PSWRQ2 STT parity which might have been generated by
         * a previous MSI-X read.
         */
        ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_PRTY_STS_WR_H_0, 0x8);

        /* Configure PSWRQ2_REG_WR_MBS0 according to the MaxPayloadSize field in
         * the PCI configuration space. The value is common for all PFs, so it
         * is okay to do it according to the first loading PF.
         */
        pos = OSAL_PCI_FIND_CAPABILITY(p_dev, PCI_CAP_ID_EXP);
        if (!pos) {
                DP_NOTICE(p_dev, true,
                          "Failed to find the PCI Express Capability structure in the PCI config space\n");
                return ECORE_IO;
        }

        OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + RTE_PCI_EXP_DEVCTL, &ctrl);
        wr_mbs = (ctrl & PCI_EXP_DEVCTL_PAYLOAD) >> 5;
        ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0, wr_mbs);

        /* Configure the PGLUE_B to discard mode */
        ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_DISCARD_NBLOCK, 0x3f);

        return ECORE_SUCCESS;
}
#endif

/* Init run time data for all PFs and their VFs on an engine.
 * TBD - for VFs - Once we have parent PF info for each VF in
 * shmem available as CAU requires knowledge of parent PF for each VF.
 */
static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
{
        u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
        u32 igu_sb_id;
        int i;

        for_each_hwfn(p_dev, i) {
                struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
                struct ecore_igu_info *p_igu_info;
                struct ecore_igu_block *p_block;
                struct cau_sb_entry sb_entry;

                p_igu_info = p_hwfn->hw_info.p_igu_info;

                for (igu_sb_id = 0;
                     igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
                     igu_sb_id++) {
                        p_block = &p_igu_info->entry[igu_sb_id];

                        if (!p_block->is_pf)
                                continue;

                        ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
                                                p_block->function_id, 0, 0);
                        STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
                                         sb_entry);
                }
        }
}

static void ecore_init_cache_line_size(struct ecore_hwfn *p_hwfn,
                                       struct ecore_ptt *p_ptt)
{
        u32 val, wr_mbs, cache_line_size;

        val = ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
        switch (val) {
        case 0:
                wr_mbs = 128;
                break;
        case 1:
                wr_mbs = 256;
                break;
        case 2:
                wr_mbs = 512;
                break;
        default:
                DP_INFO(p_hwfn,
                        "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
                        val);
                return;
        }

        cache_line_size = OSAL_MIN_T(u32, OSAL_CACHE_LINE_SIZE, wr_mbs);
        switch (cache_line_size) {
        case 32:
                val = 0;
                break;
        case 64:
                val = 1;
                break;
        case 128:
                val = 2;
                break;
        case 256:
                val = 3;
                break;
        default:
                DP_INFO(p_hwfn,
                        "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
                        cache_line_size);
        }

        if (wr_mbs < OSAL_CACHE_LINE_SIZE)
                DP_INFO(p_hwfn,
                        "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
                        OSAL_CACHE_LINE_SIZE, wr_mbs);

        STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
        if (val > 0) {
                STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
                STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
        }
}

static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
                                                 struct ecore_ptt *p_ptt,
                                                 int hw_mode)
{
        struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
        struct ecore_dev *p_dev = p_hwfn->p_dev;
        u8 vf_id, max_num_vfs;
        u16 num_pfs, pf_id;
        u32 concrete_fid;
        enum _ecore_status_t rc = ECORE_SUCCESS;

        ecore_init_cau_rt_data(p_dev);

        /* Program GTT windows */
        ecore_gtt_init(p_hwfn);

#ifndef ASIC_ONLY
        if (CHIP_REV_IS_EMUL(p_dev) && IS_LEAD_HWFN(p_hwfn)) {
                rc = ecore_hw_init_chip(p_dev, p_ptt);
                if (rc != ECORE_SUCCESS)
                        return rc;
        }
#endif

        if (p_hwfn->mcp_info) {
                if (p_hwfn->mcp_info->func_info.bandwidth_max)
                        qm_info->pf_rl_en = 1;
                if (p_hwfn->mcp_info->func_info.bandwidth_min)
                        qm_info->pf_wfq_en = 1;
        }

        ecore_qm_common_rt_init(p_hwfn,
                                p_dev->num_ports_in_engine,
                                qm_info->max_phys_tcs_per_port,
                                qm_info->pf_rl_en, qm_info->pf_wfq_en,
                                qm_info->vport_rl_en, qm_info->vport_wfq_en,
                                qm_info->qm_port_params,
                                OSAL_NULL /* global RLs are not configured */);

        ecore_cxt_hw_init_common(p_hwfn);

        ecore_init_cache_line_size(p_hwfn, p_ptt);

        rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ECORE_PATH_ID(p_hwfn),
                            hw_mode);
        if (rc != ECORE_SUCCESS)
                return rc;

        /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
         * need to decide with which value, maybe runtime
         */
        ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
        ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);

        if (ECORE_IS_BB(p_dev)) {
                /* Workaround clears ROCE search for all functions to prevent
                 * involving non initialized function in processing ROCE packet.
                 */
                num_pfs = (u16)NUM_OF_ENG_PFS(p_dev);
                for (pf_id = 0; pf_id < num_pfs; pf_id++) {
                        ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
                        ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
                        ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
                }
                /* pretend to original PF */
                ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
        }

        /* Workaround for avoiding CCFC execution error when getting packets
         * with CRC errors, and allowing instead the invoking of the FW error
         * handler.
         * This is not done inside the init tool since it currently can't
         * perform a pretending to VFs.
         */
        max_num_vfs = (u8)NUM_OF_VFS(p_dev);
        for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
                concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
                ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
                ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
                ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
                ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
                ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
        }
        /* pretend to original PF */
        ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);

        return rc;
}

#ifndef ASIC_ONLY
#define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
#define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)

#define PMEG_IF_BYTE_COUNT      8

static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
                             struct ecore_ptt *p_ptt,
                             u32 addr, u64 data, u8 reg_type, u8 port)
{
        DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
                   "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
                   ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
                   (8 << PMEG_IF_BYTE_COUNT),
                   (reg_type << 25) | (addr << 8) | port,
                   (u32)((data >> 32) & 0xffffffff),
                   (u32)(data & 0xffffffff));

        ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
                 (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
                  0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
        ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,