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7#include "qede_ethdev.h"
8#include <rte_string_fns.h>
9#include <rte_alarm.h>
10#include <rte_kvargs.h>
11
12static const struct qed_eth_ops *qed_ops;
13static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev);
14static int qede_eth_dev_init(struct rte_eth_dev *eth_dev);
15
16#define QEDE_SP_TIMER_PERIOD 10000
17
18struct rte_qede_xstats_name_off {
19 char name[RTE_ETH_XSTATS_NAME_SIZE];
20 uint64_t offset;
21};
22
23static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
24 {"rx_unicast_bytes",
25 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
26 {"rx_multicast_bytes",
27 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
28 {"rx_broadcast_bytes",
29 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
30 {"rx_unicast_packets",
31 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
32 {"rx_multicast_packets",
33 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
34 {"rx_broadcast_packets",
35 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
36
37 {"tx_unicast_bytes",
38 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
39 {"tx_multicast_bytes",
40 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
41 {"tx_broadcast_bytes",
42 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
43 {"tx_unicast_packets",
44 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
45 {"tx_multicast_packets",
46 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
47 {"tx_broadcast_packets",
48 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
49
50 {"rx_64_byte_packets",
51 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
52 {"rx_65_to_127_byte_packets",
53 offsetof(struct ecore_eth_stats_common,
54 rx_65_to_127_byte_packets)},
55 {"rx_128_to_255_byte_packets",
56 offsetof(struct ecore_eth_stats_common,
57 rx_128_to_255_byte_packets)},
58 {"rx_256_to_511_byte_packets",
59 offsetof(struct ecore_eth_stats_common,
60 rx_256_to_511_byte_packets)},
61 {"rx_512_to_1023_byte_packets",
62 offsetof(struct ecore_eth_stats_common,
63 rx_512_to_1023_byte_packets)},
64 {"rx_1024_to_1518_byte_packets",
65 offsetof(struct ecore_eth_stats_common,
66 rx_1024_to_1518_byte_packets)},
67 {"tx_64_byte_packets",
68 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
69 {"tx_65_to_127_byte_packets",
70 offsetof(struct ecore_eth_stats_common,
71 tx_65_to_127_byte_packets)},
72 {"tx_128_to_255_byte_packets",
73 offsetof(struct ecore_eth_stats_common,
74 tx_128_to_255_byte_packets)},
75 {"tx_256_to_511_byte_packets",
76 offsetof(struct ecore_eth_stats_common,
77 tx_256_to_511_byte_packets)},
78 {"tx_512_to_1023_byte_packets",
79 offsetof(struct ecore_eth_stats_common,
80 tx_512_to_1023_byte_packets)},
81 {"tx_1024_to_1518_byte_packets",
82 offsetof(struct ecore_eth_stats_common,
83 tx_1024_to_1518_byte_packets)},
84
85 {"rx_mac_crtl_frames",
86 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
87 {"tx_mac_control_frames",
88 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
89 {"rx_pause_frames",
90 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
91 {"tx_pause_frames",
92 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
93 {"rx_priority_flow_control_frames",
94 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
95 {"tx_priority_flow_control_frames",
96 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
97
98 {"rx_crc_errors",
99 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
100 {"rx_align_errors",
101 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
102 {"rx_carrier_errors",
103 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
104 {"rx_oversize_packet_errors",
105 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
106 {"rx_jabber_errors",
107 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
108 {"rx_undersize_packet_errors",
109 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
110 {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
111 {"rx_host_buffer_not_available",
112 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
113
114 {"rx_packet_too_big_discards",
115 offsetof(struct ecore_eth_stats_common,
116 packet_too_big_discard)},
117 {"rx_ttl_zero_discards",
118 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
119 {"rx_multi_function_tag_filter_discards",
120 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
121 {"rx_mac_filter_discards",
122 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
123 {"rx_gft_filter_drop",
124 offsetof(struct ecore_eth_stats_common, gft_filter_drop)},
125 {"rx_hw_buffer_truncates",
126 offsetof(struct ecore_eth_stats_common, brb_truncates)},
127 {"rx_hw_buffer_discards",
128 offsetof(struct ecore_eth_stats_common, brb_discards)},
129 {"tx_error_drop_packets",
130 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
131
132 {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
133 {"rx_mac_unicast_packets",
134 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
135 {"rx_mac_multicast_packets",
136 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
137 {"rx_mac_broadcast_packets",
138 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
139 {"rx_mac_frames_ok",
140 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
141 {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
142 {"tx_mac_unicast_packets",
143 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
144 {"tx_mac_multicast_packets",
145 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
146 {"tx_mac_broadcast_packets",
147 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
148
149 {"lro_coalesced_packets",
150 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
151 {"lro_coalesced_events",
152 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
153 {"lro_aborts_num",
154 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
155 {"lro_not_coalesced_packets",
156 offsetof(struct ecore_eth_stats_common,
157 tpa_not_coalesced_pkts)},
158 {"lro_coalesced_bytes",
159 offsetof(struct ecore_eth_stats_common,
160 tpa_coalesced_bytes)},
161};
162
163static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
164 {"rx_1519_to_1522_byte_packets",
165 offsetof(struct ecore_eth_stats, bb) +
166 offsetof(struct ecore_eth_stats_bb,
167 rx_1519_to_1522_byte_packets)},
168 {"rx_1519_to_2047_byte_packets",
169 offsetof(struct ecore_eth_stats, bb) +
170 offsetof(struct ecore_eth_stats_bb,
171 rx_1519_to_2047_byte_packets)},
172 {"rx_2048_to_4095_byte_packets",
173 offsetof(struct ecore_eth_stats, bb) +
174 offsetof(struct ecore_eth_stats_bb,
175 rx_2048_to_4095_byte_packets)},
176 {"rx_4096_to_9216_byte_packets",
177 offsetof(struct ecore_eth_stats, bb) +
178 offsetof(struct ecore_eth_stats_bb,
179 rx_4096_to_9216_byte_packets)},
180 {"rx_9217_to_16383_byte_packets",
181 offsetof(struct ecore_eth_stats, bb) +
182 offsetof(struct ecore_eth_stats_bb,
183 rx_9217_to_16383_byte_packets)},
184
185 {"tx_1519_to_2047_byte_packets",
186 offsetof(struct ecore_eth_stats, bb) +
187 offsetof(struct ecore_eth_stats_bb,
188 tx_1519_to_2047_byte_packets)},
189 {"tx_2048_to_4095_byte_packets",
190 offsetof(struct ecore_eth_stats, bb) +
191 offsetof(struct ecore_eth_stats_bb,
192 tx_2048_to_4095_byte_packets)},
193 {"tx_4096_to_9216_byte_packets",
194 offsetof(struct ecore_eth_stats, bb) +
195 offsetof(struct ecore_eth_stats_bb,
196 tx_4096_to_9216_byte_packets)},
197 {"tx_9217_to_16383_byte_packets",
198 offsetof(struct ecore_eth_stats, bb) +
199 offsetof(struct ecore_eth_stats_bb,
200 tx_9217_to_16383_byte_packets)},
201
202 {"tx_lpi_entry_count",
203 offsetof(struct ecore_eth_stats, bb) +
204 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
205 {"tx_total_collisions",
206 offsetof(struct ecore_eth_stats, bb) +
207 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
208};
209
210static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
211 {"rx_1519_to_max_byte_packets",
212 offsetof(struct ecore_eth_stats, ah) +
213 offsetof(struct ecore_eth_stats_ah,
214 rx_1519_to_max_byte_packets)},
215 {"tx_1519_to_max_byte_packets",
216 offsetof(struct ecore_eth_stats, ah) +
217 offsetof(struct ecore_eth_stats_ah,
218 tx_1519_to_max_byte_packets)},
219};
220
221static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
222 {"rx_q_segments",
223 offsetof(struct qede_rx_queue, rx_segs)},
224 {"rx_q_hw_errors",
225 offsetof(struct qede_rx_queue, rx_hw_errors)},
226 {"rx_q_allocation_errors",
227 offsetof(struct qede_rx_queue, rx_alloc_errors)}
228};
229
230
231static int
232qede_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size)
233{
234 struct qede_dev *qdev = dev->data->dev_private;
235 struct ecore_dev *edev = &qdev->edev;
236 struct qed_dev_info *info = &qdev->dev_info.common;
237 static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
238 size_t size;
239
240 if (IS_PF(edev))
241 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
242 QEDE_PMD_FW_VERSION);
243 else
244 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
245 info->fw_major, info->fw_minor,
246 info->fw_rev, info->fw_eng);
247 size = strlen(ver_str);
248 if (size + 1 <= fw_size)
249 strlcpy(fw_ver, ver_str, fw_size);
250 else
251 return (size + 1);
252
253 snprintf(ver_str + size, (QEDE_PMD_DRV_VER_STR_SIZE - size),
254 " MFW: %d.%d.%d.%d",
255 GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_3),
256 GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_2),
257 GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_1),
258 GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_0));
259 size = strlen(ver_str);
260 if (size + 1 <= fw_size)
261 strlcpy(fw_ver, ver_str, fw_size);
262
263 if (fw_size <= 32)
264 goto out;
265
266 snprintf(ver_str + size, (QEDE_PMD_DRV_VER_STR_SIZE - size),
267 " MBI: %d.%d.%d",
268 GET_MFW_FIELD(info->mbi_version, QED_MBI_VERSION_2),
269 GET_MFW_FIELD(info->mbi_version, QED_MBI_VERSION_1),
270 GET_MFW_FIELD(info->mbi_version, QED_MBI_VERSION_0));
271 size = strlen(ver_str);
272 if (size + 1 <= fw_size)
273 strlcpy(fw_ver, ver_str, fw_size);
274
275out:
276 return 0;
277}
278
279static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
280{
281 OSAL_SPIN_LOCK(&p_hwfn->spq_lock);
282 ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
283 OSAL_SPIN_UNLOCK(&p_hwfn->spq_lock);
284}
285
286static void
287qede_interrupt_handler_intx(void *param)
288{
289 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
290 struct qede_dev *qdev = eth_dev->data->dev_private;
291 struct ecore_dev *edev = &qdev->edev;
292 u64 status;
293
294
295 status = ecore_int_igu_read_sisr_reg(ECORE_LEADING_HWFN(edev));
296 if (status & 0x1) {
297 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
298
299 if (rte_intr_ack(eth_dev->intr_handle))
300 DP_ERR(edev, "rte_intr_ack failed\n");
301 }
302}
303
304static void
305qede_interrupt_handler(void *param)
306{
307 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
308 struct qede_dev *qdev = eth_dev->data->dev_private;
309 struct ecore_dev *edev = &qdev->edev;
310
311 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
312 if (rte_intr_ack(eth_dev->intr_handle))
313 DP_ERR(edev, "rte_intr_ack failed\n");
314}
315
316static void
317qede_assign_rxtx_handlers(struct rte_eth_dev *dev, bool is_dummy)
318{
319 uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
320 struct qede_dev *qdev = dev->data->dev_private;
321 struct ecore_dev *edev = &qdev->edev;
322 bool use_tx_offload = false;
323
324 if (is_dummy) {
325 dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
326 dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
327 return;
328 }
329
330 if (ECORE_IS_CMT(edev)) {
331 dev->rx_pkt_burst = qede_recv_pkts_cmt;
332 dev->tx_pkt_burst = qede_xmit_pkts_cmt;
333 return;
334 }
335
336 if (dev->data->lro || dev->data->scattered_rx) {
337 DP_INFO(edev, "Assigning qede_recv_pkts\n");
338 dev->rx_pkt_burst = qede_recv_pkts;
339 } else {
340 DP_INFO(edev, "Assigning qede_recv_pkts_regular\n");
341 dev->rx_pkt_burst = qede_recv_pkts_regular;
342 }
343
344 use_tx_offload = !!(tx_offloads &
345 (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
346 DEV_TX_OFFLOAD_TCP_TSO |
347 DEV_TX_OFFLOAD_VLAN_INSERT));
348
349 if (use_tx_offload) {
350 DP_INFO(edev, "Assigning qede_xmit_pkts\n");
351 dev->tx_pkt_burst = qede_xmit_pkts;
352 } else {
353 DP_INFO(edev, "Assigning qede_xmit_pkts_regular\n");
354 dev->tx_pkt_burst = qede_xmit_pkts_regular;
355 }
356}
357
358static void
359qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
360{
361 rte_memcpy(&qdev->dev_info, info, sizeof(*info));
362 qdev->ops = qed_ops;
363}
364
365static void qede_print_adapter_info(struct rte_eth_dev *dev)
366{
367 struct qede_dev *qdev = dev->data->dev_private;
368 struct ecore_dev *edev = &qdev->edev;
369 static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
370
371 DP_INFO(edev, "**************************************************\n");
372 DP_INFO(edev, " %-20s: %s\n", "DPDK version", rte_version());
373 DP_INFO(edev, " %-20s: %s %c%d\n", "Chip details",
374 ECORE_IS_BB(edev) ? "BB" : "AH",
375 'A' + edev->chip_rev,
376 (int)edev->chip_metal);
377 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
378 QEDE_PMD_DRV_VERSION);
379 DP_INFO(edev, " %-20s: %s\n", "Driver version", ver_str);
380 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
381 QEDE_PMD_BASE_VERSION);
382 DP_INFO(edev, " %-20s: %s\n", "Base version", ver_str);
383 qede_fw_version_get(dev, ver_str, sizeof(ver_str));
384 DP_INFO(edev, " %-20s: %s\n", "Firmware version", ver_str);
385 DP_INFO(edev, " %-20s: %s\n", "Firmware file", qede_fw_file);
386 DP_INFO(edev, "**************************************************\n");
387}
388
389static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats)
390{
391 struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
392 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
393 unsigned int i = 0, j = 0, qid;
394 unsigned int rxq_stat_cntrs, txq_stat_cntrs;
395 struct qede_tx_queue *txq;
396
397 DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n");
398
399 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(dev),
400 RTE_ETHDEV_QUEUE_STAT_CNTRS);
401 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(dev),
402 RTE_ETHDEV_QUEUE_STAT_CNTRS);
403
404 for (qid = 0; qid < qdev->num_rx_queues; qid++) {
405 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
406 offsetof(struct qede_rx_queue, rcv_pkts), 0,
407 sizeof(uint64_t));
408 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
409 offsetof(struct qede_rx_queue, rx_hw_errors), 0,
410 sizeof(uint64_t));
411 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
412 offsetof(struct qede_rx_queue, rx_alloc_errors), 0,
413 sizeof(uint64_t));
414
415 if (xstats)
416 for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++)
417 OSAL_MEMSET((((char *)
418 (qdev->fp_array[qid].rxq)) +
419 qede_rxq_xstats_strings[j].offset),
420 0,
421 sizeof(uint64_t));
422
423 i++;
424 if (i == rxq_stat_cntrs)
425 break;
426 }
427
428 i = 0;
429
430 for (qid = 0; qid < qdev->num_tx_queues; qid++) {
431 txq = qdev->fp_array[qid].txq;
432
433 OSAL_MEMSET((uint64_t *)(uintptr_t)
434 (((uint64_t)(uintptr_t)(txq)) +
435 offsetof(struct qede_tx_queue, xmit_pkts)), 0,
436 sizeof(uint64_t));
437
438 i++;
439 if (i == txq_stat_cntrs)
440 break;
441 }
442}
443
444static int
445qede_stop_vport(struct ecore_dev *edev)
446{
447 struct ecore_hwfn *p_hwfn;
448 uint8_t vport_id;
449 int rc;
450 int i;
451
452 vport_id = 0;
453 for_each_hwfn(edev, i) {
454 p_hwfn = &edev->hwfns[i];
455 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
456 vport_id);
457 if (rc != ECORE_SUCCESS) {
458 DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
459 return rc;
460 }
461 }
462
463 DP_INFO(edev, "vport stopped\n");
464
465 return 0;
466}
467
468static int
469qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
470{
471 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
472 struct ecore_sp_vport_start_params params;
473 struct ecore_hwfn *p_hwfn;
474 int rc;
475 int i;
476
477 if (qdev->vport_started)
478 qede_stop_vport(edev);
479
480 memset(¶ms, 0, sizeof(params));
481 params.vport_id = 0;
482 params.mtu = mtu;
483
484 params.zero_placement_offset = 1;
485 for_each_hwfn(edev, i) {
486 p_hwfn = &edev->hwfns[i];
487 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
488 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
489 rc = ecore_sp_vport_start(p_hwfn, ¶ms);
490 if (rc != ECORE_SUCCESS) {
491 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
492 return rc;
493 }
494 }
495 ecore_reset_vport_stats(edev);
496 qdev->vport_started = true;
497 DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
498
499 return 0;
500}
501
502#define QEDE_NPAR_TX_SWITCHING "npar_tx_switching"
503#define QEDE_VF_TX_SWITCHING "vf_tx_switching"
504
505
506int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
507{
508 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
509 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
510 struct ecore_sp_vport_update_params params;
511 struct ecore_hwfn *p_hwfn;
512 uint8_t i;
513 int rc = -1;
514
515 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
516 params.vport_id = 0;
517 params.update_vport_active_rx_flg = 1;
518 params.update_vport_active_tx_flg = 1;
519 params.vport_active_rx_flg = flg;
520 params.vport_active_tx_flg = flg;
521 if ((qdev->enable_tx_switching == false) && (flg == true)) {
522 params.update_tx_switching_flg = 1;
523 params.tx_switching_flg = !flg;
524 }
525 for_each_hwfn(edev, i) {
526 p_hwfn = &edev->hwfns[i];
527 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
528 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
529 ECORE_SPQ_MODE_EBLOCK, NULL);
530 if (rc != ECORE_SUCCESS) {
531 DP_ERR(edev, "Failed to update vport\n");
532 break;
533 }
534 }
535 DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated");
536
537 return rc;
538}
539
540static void
541qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
542 uint16_t mtu, bool enable)
543{
544
545 sge_tpa_params->tpa_ipv4_en_flg = enable;
546 sge_tpa_params->tpa_ipv6_en_flg = enable;
547 sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
548 sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
549
550 sge_tpa_params->update_tpa_en_flg = 1;
551
552 sge_tpa_params->update_tpa_param_flg = enable;
553
554 sge_tpa_params->max_buffers_per_cqe = 20;
555
556
557
558 sge_tpa_params->tpa_pkt_split_flg = 1;
559 sge_tpa_params->tpa_hdr_data_split_flg = 0;
560 sge_tpa_params->tpa_gro_consistent_flg = 0;
561 sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
562 sge_tpa_params->tpa_max_size = 0x7FFF;
563 sge_tpa_params->tpa_min_size_to_start = mtu / 2;
564 sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
565}
566
567
568int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
569{
570 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
571 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
572 struct ecore_sp_vport_update_params params;
573 struct ecore_sge_tpa_params tpa_params;
574 struct ecore_hwfn *p_hwfn;
575 int rc;
576 int i;
577
578 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
579 memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
580 qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
581 params.vport_id = 0;
582 params.sge_tpa_params = &tpa_params;
583 for_each_hwfn(edev, i) {
584 p_hwfn = &edev->hwfns[i];
585 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
586 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
587 ECORE_SPQ_MODE_EBLOCK, NULL);
588 if (rc != ECORE_SUCCESS) {
589 DP_ERR(edev, "Failed to update LRO\n");
590 return -1;
591 }
592 }
593 qdev->enable_lro = flg;
594 eth_dev->data->lro = flg;
595
596 DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
597
598 return 0;
599}
600
601static int
602qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
603 enum qed_filter_rx_mode_type type)
604{
605 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
606 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
607 struct ecore_filter_accept_flags flags;
608
609 memset(&flags, 0, sizeof(flags));
610
611 flags.update_rx_mode_config = 1;
612 flags.update_tx_mode_config = 1;
613 flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
614 ECORE_ACCEPT_MCAST_MATCHED |
615 ECORE_ACCEPT_BCAST;
616
617 flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
618 ECORE_ACCEPT_MCAST_MATCHED |
619 ECORE_ACCEPT_BCAST;
620
621 if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
622 flags.rx_accept_filter |= (ECORE_ACCEPT_UCAST_UNMATCHED |
623 ECORE_ACCEPT_MCAST_UNMATCHED);
624 if (IS_VF(edev)) {
625 flags.tx_accept_filter |=
626 (ECORE_ACCEPT_UCAST_UNMATCHED |
627 ECORE_ACCEPT_MCAST_UNMATCHED);
628 DP_INFO(edev, "Enabling Tx unmatched flags for VF\n");
629 }
630 } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
631 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
632 }
633
634 return ecore_filter_accept_cmd(edev, 0, flags, false, false,
635 ECORE_SPQ_MODE_CB, NULL);
636}
637
638int
639qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
640 bool add)
641{
642 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
643 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
644 struct qede_ucast_entry *tmp = NULL;
645 struct qede_ucast_entry *u;
646 struct rte_ether_addr *mac_addr;
647
648 mac_addr = (struct rte_ether_addr *)ucast->mac;
649 if (add) {
650 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
651 if ((memcmp(mac_addr, &tmp->mac,
652 RTE_ETHER_ADDR_LEN) == 0) &&
653 ucast->vni == tmp->vni &&
654 ucast->vlan == tmp->vlan) {
655 DP_INFO(edev, "Unicast MAC is already added"
656 " with vlan = %u, vni = %u\n",
657 ucast->vlan, ucast->vni);
658 return 0;
659 }
660 }
661 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
662 RTE_CACHE_LINE_SIZE);
663 if (!u) {
664 DP_ERR(edev, "Did not allocate memory for ucast\n");
665 return -ENOMEM;
666 }
667 rte_ether_addr_copy(mac_addr, &u->mac);
668 u->vlan = ucast->vlan;
669 u->vni = ucast->vni;
670 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
671 qdev->num_uc_addr++;
672 } else {
673 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
674 if ((memcmp(mac_addr, &tmp->mac,
675 RTE_ETHER_ADDR_LEN) == 0) &&
676 ucast->vlan == tmp->vlan &&
677 ucast->vni == tmp->vni)
678 break;
679 }
680 if (tmp == NULL) {
681 DP_INFO(edev, "Unicast MAC is not found\n");
682 return -EINVAL;
683 }
684 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
685 qdev->num_uc_addr--;
686 }
687
688 return 0;
689}
690
691static int
692qede_add_mcast_filters(struct rte_eth_dev *eth_dev,
693 struct rte_ether_addr *mc_addrs,
694 uint32_t mc_addrs_num)
695{
696 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
697 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
698 struct ecore_filter_mcast mcast;
699 struct qede_mcast_entry *m = NULL;
700 uint8_t i;
701 int rc;
702
703 for (i = 0; i < mc_addrs_num; i++) {
704 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
705 RTE_CACHE_LINE_SIZE);
706 if (!m) {
707 DP_ERR(edev, "Did not allocate memory for mcast\n");
708 return -ENOMEM;
709 }
710 rte_ether_addr_copy(&mc_addrs[i], &m->mac);
711 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
712 }
713 memset(&mcast, 0, sizeof(mcast));
714 mcast.num_mc_addrs = mc_addrs_num;
715 mcast.opcode = ECORE_FILTER_ADD;
716 for (i = 0; i < mc_addrs_num; i++)
717 rte_ether_addr_copy(&mc_addrs[i], (struct rte_ether_addr *)
718 &mcast.mac[i]);
719 rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
720 if (rc != ECORE_SUCCESS) {
721 DP_ERR(edev, "Failed to add multicast filter (rc = %d\n)", rc);
722 return -1;
723 }
724
725 return 0;
726}
727
728static int qede_del_mcast_filters(struct rte_eth_dev *eth_dev)
729{
730 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
731 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
732 struct qede_mcast_entry *tmp = NULL;
733 struct ecore_filter_mcast mcast;
734 int j;
735 int rc;
736
737 memset(&mcast, 0, sizeof(mcast));
738 mcast.num_mc_addrs = qdev->num_mc_addr;
739 mcast.opcode = ECORE_FILTER_REMOVE;
740 j = 0;
741 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
742 rte_ether_addr_copy(&tmp->mac,
743 (struct rte_ether_addr *)&mcast.mac[j]);
744 j++;
745 }
746 rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
747 if (rc != ECORE_SUCCESS) {
748 DP_ERR(edev, "Failed to delete multicast filter\n");
749 return -1;
750 }
751
752 while (!SLIST_EMPTY(&qdev->mc_list_head)) {
753 tmp = SLIST_FIRST(&qdev->mc_list_head);
754 SLIST_REMOVE_HEAD(&qdev->mc_list_head, list);
755 }
756 SLIST_INIT(&qdev->mc_list_head);
757
758 return 0;
759}
760
761enum _ecore_status_t
762qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
763 bool add)
764{
765 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
766 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
767 enum _ecore_status_t rc = ECORE_INVAL;
768
769 if (add && (qdev->num_uc_addr >= qdev->dev_info.num_mac_filters)) {
770 DP_ERR(edev, "Ucast filter table limit exceeded,"
771 " Please enable promisc mode\n");
772 return ECORE_INVAL;
773 }
774
775 rc = qede_ucast_filter(eth_dev, ucast, add);
776 if (rc == 0)
777 rc = ecore_filter_ucast_cmd(edev, ucast,
778 ECORE_SPQ_MODE_CB, NULL);
779
780
781
782 if ((rc != ECORE_SUCCESS) && add)
783 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
784 rc, add);
785
786 return rc;
787}
788
789static int
790qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr,
791 __rte_unused uint32_t index, __rte_unused uint32_t pool)
792{
793 struct ecore_filter_ucast ucast;
794 int re;
795
796 if (!rte_is_valid_assigned_ether_addr(mac_addr))
797 return -EINVAL;
798
799 qede_set_ucast_cmn_params(&ucast);
800 ucast.opcode = ECORE_FILTER_ADD;
801 ucast.type = ECORE_FILTER_MAC;
802 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)&ucast.mac);
803 re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
804 return re;
805}
806
807static void
808qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
809{
810 struct qede_dev *qdev = eth_dev->data->dev_private;
811 struct ecore_dev *edev = &qdev->edev;
812 struct ecore_filter_ucast ucast;
813
814 PMD_INIT_FUNC_TRACE(edev);
815
816 if (index >= qdev->dev_info.num_mac_filters) {
817 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
818 index, qdev->dev_info.num_mac_filters);
819 return;
820 }
821
822 if (!rte_is_valid_assigned_ether_addr(ð_dev->data->mac_addrs[index]))
823 return;
824
825 qede_set_ucast_cmn_params(&ucast);
826 ucast.opcode = ECORE_FILTER_REMOVE;
827 ucast.type = ECORE_FILTER_MAC;
828
829
830 rte_ether_addr_copy(ð_dev->data->mac_addrs[index],
831 (struct rte_ether_addr *)&ucast.mac);
832
833 qede_mac_int_ops(eth_dev, &ucast, false);
834}
835
836static int
837qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr)
838{
839 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
840 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
841
842 if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
843 mac_addr->addr_bytes)) {
844 DP_ERR(edev, "Setting MAC address is not allowed\n");
845 return -EPERM;
846 }
847
848 qede_mac_addr_remove(eth_dev, 0);
849
850 return qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
851}
852
853void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
854{
855 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
856 struct ecore_sp_vport_update_params params;
857 struct ecore_hwfn *p_hwfn;
858 uint8_t i;
859 int rc;
860
861 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
862 params.vport_id = 0;
863 params.update_accept_any_vlan_flg = 1;
864 params.accept_any_vlan = flg;
865 for_each_hwfn(edev, i) {
866 p_hwfn = &edev->hwfns[i];
867 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
868 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
869 ECORE_SPQ_MODE_EBLOCK, NULL);
870 if (rc != ECORE_SUCCESS) {
871 DP_ERR(edev, "Failed to configure accept-any-vlan\n");
872 return;
873 }
874 }
875
876 DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
877}
878
879static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
880{
881 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
882 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
883 struct ecore_sp_vport_update_params params;
884 struct ecore_hwfn *p_hwfn;
885 uint8_t i;
886 int rc;
887
888 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
889 params.vport_id = 0;
890 params.update_inner_vlan_removal_flg = 1;
891 params.inner_vlan_removal_flg = flg;
892 for_each_hwfn(edev, i) {
893 p_hwfn = &edev->hwfns[i];
894 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
895 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
896 ECORE_SPQ_MODE_EBLOCK, NULL);
897 if (rc != ECORE_SUCCESS) {
898 DP_ERR(edev, "Failed to update vport\n");
899 return -1;
900 }
901 }
902
903 qdev->vlan_strip_flg = flg;
904
905 DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
906 return 0;
907}
908
909static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
910 uint16_t vlan_id, int on)
911{
912 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
913 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
914 struct qed_dev_eth_info *dev_info = &qdev->dev_info;
915 struct qede_vlan_entry *tmp = NULL;
916 struct qede_vlan_entry *vlan;
917 struct ecore_filter_ucast ucast;
918 int rc;
919
920 if (on) {
921 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
922 DP_ERR(edev, "Reached max VLAN filter limit"
923 " enabling accept_any_vlan\n");
924 qede_config_accept_any_vlan(qdev, true);
925 return 0;
926 }
927
928 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
929 if (tmp->vid == vlan_id) {
930 DP_INFO(edev, "VLAN %u already configured\n",
931 vlan_id);
932 return 0;
933 }
934 }
935
936 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
937 RTE_CACHE_LINE_SIZE);
938
939 if (!vlan) {
940 DP_ERR(edev, "Did not allocate memory for VLAN\n");
941 return -ENOMEM;
942 }
943
944 qede_set_ucast_cmn_params(&ucast);
945 ucast.opcode = ECORE_FILTER_ADD;
946 ucast.type = ECORE_FILTER_VLAN;
947 ucast.vlan = vlan_id;
948 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
949 NULL);
950 if (rc != 0) {
951 DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
952 rc);
953 rte_free(vlan);
954 } else {
955 vlan->vid = vlan_id;
956 SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
957 qdev->configured_vlans++;
958 DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
959 vlan_id, qdev->configured_vlans);
960 }
961 } else {
962 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
963 if (tmp->vid == vlan_id)
964 break;
965 }
966
967 if (!tmp) {
968 if (qdev->configured_vlans == 0) {
969 DP_INFO(edev,
970 "No VLAN filters configured yet\n");
971 return 0;
972 }
973
974 DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
975 return -EINVAL;
976 }
977
978 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
979
980 qede_set_ucast_cmn_params(&ucast);
981 ucast.opcode = ECORE_FILTER_REMOVE;
982 ucast.type = ECORE_FILTER_VLAN;
983 ucast.vlan = vlan_id;
984 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
985 NULL);
986 if (rc != 0) {
987 DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
988 vlan_id, rc);
989 } else {
990 qdev->configured_vlans--;
991 DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
992 vlan_id, qdev->configured_vlans);
993 }
994 }
995
996 return rc;
997}
998
999static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
1000{
1001 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1002 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1003 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1004
1005 if (mask & ETH_VLAN_STRIP_MASK) {
1006 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1007 (void)qede_vlan_stripping(eth_dev, 1);
1008 else
1009 (void)qede_vlan_stripping(eth_dev, 0);
1010 }
1011
1012 if (mask & ETH_VLAN_FILTER_MASK) {
1013
1014 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
1015 qede_vlan_filter_set(eth_dev, 0, 1);
1016 } else {
1017 if (qdev->configured_vlans > 1) {
1018 DP_ERR(edev,
1019 " Please remove existing VLAN filters"
1020 " before disabling VLAN filtering\n");
1021
1022
1023
1024 eth_dev->data->dev_conf.rxmode.offloads |=
1025 DEV_RX_OFFLOAD_VLAN_FILTER;
1026 } else {
1027 qede_vlan_filter_set(eth_dev, 0, 0);
1028 }
1029 }
1030 }
1031
1032 qdev->vlan_offload_mask = mask;
1033
1034 DP_INFO(edev, "VLAN offload mask %d\n", mask);
1035
1036 return 0;
1037}
1038
1039static void qede_prandom_bytes(uint32_t *buff)
1040{
1041 uint8_t i;
1042
1043 srand((unsigned int)time(NULL));
1044 for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1045 buff[i] = rand();
1046}
1047
1048int qede_config_rss(struct rte_eth_dev *eth_dev)
1049{
1050 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1051 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1052 uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1053 struct rte_eth_rss_reta_entry64 reta_conf[2];
1054 struct rte_eth_rss_conf rss_conf;
1055 uint32_t i, id, pos, q;
1056
1057 rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1058 if (!rss_conf.rss_key) {
1059 DP_INFO(edev, "Applying driver default key\n");
1060 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1061 qede_prandom_bytes(&def_rss_key[0]);
1062 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1063 }
1064
1065
1066 if (qede_rss_hash_update(eth_dev, &rss_conf))
1067 return -EINVAL;
1068
1069
1070 memset(reta_conf, 0, sizeof(reta_conf));
1071 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1072 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1073
1074 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1075 id = i / RTE_RETA_GROUP_SIZE;
1076 pos = i % RTE_RETA_GROUP_SIZE;
1077 q = i % QEDE_RSS_COUNT(eth_dev);
1078 reta_conf[id].reta[pos] = q;
1079 }
1080 if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1081 ECORE_RSS_IND_TABLE_SIZE))
1082 return -EINVAL;
1083
1084 return 0;
1085}
1086
1087static void qede_fastpath_start(struct ecore_dev *edev)
1088{
1089 struct ecore_hwfn *p_hwfn;
1090 int i;
1091
1092 for_each_hwfn(edev, i) {
1093 p_hwfn = &edev->hwfns[i];
1094 ecore_hw_start_fastpath(p_hwfn);
1095 }
1096}
1097
1098static int qede_dev_start(struct rte_eth_dev *eth_dev)
1099{
1100 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1101 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1102 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
1103
1104 PMD_INIT_FUNC_TRACE(edev);
1105
1106
1107 if (qdev->new_mtu && qdev->new_mtu != qdev->mtu) {
1108 if (qede_update_mtu(eth_dev, qdev->new_mtu))
1109 goto err;
1110 qdev->mtu = qdev->new_mtu;
1111 qdev->new_mtu = 0;
1112 }
1113
1114
1115 if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) {
1116 if (qede_enable_tpa(eth_dev, true))
1117 return -EINVAL;
1118
1119 if (!eth_dev->data->scattered_rx)
1120 rxmode->offloads |= DEV_RX_OFFLOAD_SCATTER;
1121 }
1122
1123
1124 if (qede_start_queues(eth_dev))
1125 goto err;
1126
1127 if (IS_PF(edev))
1128 qede_reset_queue_stats(qdev, true);
1129
1130
1131
1132
1133
1134
1135 if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1136 if (qede_config_rss(eth_dev))
1137 goto err;
1138
1139
1140 if (qede_activate_vport(eth_dev, true))
1141 goto err;
1142
1143
1144 qede_dev_set_link_state(eth_dev, true);
1145
1146
1147 qede_link_update(eth_dev, 0);
1148
1149
1150 qede_fastpath_start(edev);
1151
1152
1153 qede_assign_rxtx_handlers(eth_dev, false);
1154
1155 DP_INFO(edev, "Device started\n");
1156
1157 return 0;
1158err:
1159 DP_ERR(edev, "Device start fails\n");
1160 return -1;
1161}
1162
1163static int qede_dev_stop(struct rte_eth_dev *eth_dev)
1164{
1165 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1166 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1167
1168 PMD_INIT_FUNC_TRACE(edev);
1169 eth_dev->data->dev_started = 0;
1170
1171
1172 qede_dev_set_link_state(eth_dev, false);
1173
1174
1175 qede_link_update(eth_dev, 0);
1176
1177
1178
1179
1180 qede_assign_rxtx_handlers(eth_dev, true);
1181
1182
1183 if (qede_activate_vport(eth_dev, false))
1184 return 0;
1185
1186 if (qdev->enable_lro)
1187 qede_enable_tpa(eth_dev, false);
1188
1189
1190 qede_stop_queues(eth_dev);
1191
1192
1193 ecore_hw_stop_fastpath(edev);
1194
1195 DP_INFO(edev, "Device is stopped\n");
1196
1197 return 0;
1198}
1199
1200static const char * const valid_args[] = {
1201 QEDE_NPAR_TX_SWITCHING,
1202 QEDE_VF_TX_SWITCHING,
1203 NULL,
1204};
1205
1206static int qede_args_check(const char *key, const char *val, void *opaque)
1207{
1208 unsigned long tmp;
1209 int ret = 0;
1210 struct rte_eth_dev *eth_dev = opaque;
1211 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1212 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1213
1214 errno = 0;
1215 tmp = strtoul(val, NULL, 0);
1216 if (errno) {
1217 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val);
1218 return errno;
1219 }
1220
1221 if ((strcmp(QEDE_NPAR_TX_SWITCHING, key) == 0) ||
1222 ((strcmp(QEDE_VF_TX_SWITCHING, key) == 0) && IS_VF(edev))) {
1223 qdev->enable_tx_switching = !!tmp;
1224 DP_INFO(edev, "Disabling %s tx-switching\n",
1225 strcmp(QEDE_NPAR_TX_SWITCHING, key) ?
1226 "VF" : "NPAR");
1227 }
1228
1229 return ret;
1230}
1231
1232static int qede_args(struct rte_eth_dev *eth_dev)
1233{
1234 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1235 struct rte_kvargs *kvlist;
1236 struct rte_devargs *devargs;
1237 int ret;
1238 int i;
1239
1240 devargs = pci_dev->device.devargs;
1241 if (!devargs)
1242 return 0;
1243
1244 kvlist = rte_kvargs_parse(devargs->args, valid_args);
1245 if (kvlist == NULL)
1246 return -EINVAL;
1247
1248
1249 for (i = 0; (valid_args[i] != NULL); ++i) {
1250 if (rte_kvargs_count(kvlist, valid_args[i])) {
1251 ret = rte_kvargs_process(kvlist, valid_args[i],
1252 qede_args_check, eth_dev);
1253 if (ret != ECORE_SUCCESS) {
1254 rte_kvargs_free(kvlist);
1255 return ret;
1256 }
1257 }
1258 }
1259 rte_kvargs_free(kvlist);
1260
1261 return 0;
1262}
1263
1264static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1265{
1266 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1267 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1268 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
1269 uint8_t num_rxqs;
1270 uint8_t num_txqs;
1271 int ret;
1272
1273 PMD_INIT_FUNC_TRACE(edev);
1274
1275 if (rxmode->mq_mode & ETH_MQ_RX_RSS_FLAG)
1276 rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1277
1278
1279
1280
1281 if (eth_dev->data->nb_rx_queues == 0) {
1282 DP_ERR(edev, "Minimum one RX queue is required\n");
1283 return -EINVAL;
1284 }
1285
1286
1287 qdev->enable_tx_switching = 1;
1288
1289
1290 if (qede_args(eth_dev))
1291 DP_NOTICE(edev, false,
1292 "Invalid devargs supplied, requested change will not take effect\n");
1293
1294 if (!(rxmode->mq_mode == ETH_MQ_RX_NONE ||
1295 rxmode->mq_mode == ETH_MQ_RX_RSS)) {
1296 DP_ERR(edev, "Unsupported multi-queue mode\n");
1297 return -ENOTSUP;
1298 }
1299
1300 if (qede_check_fdir_support(eth_dev))
1301 return -ENOTSUP;
1302
1303
1304 num_txqs = eth_dev->data->nb_tx_queues * edev->num_hwfns;
1305 num_rxqs = eth_dev->data->nb_rx_queues * edev->num_hwfns;
1306 if (qdev->num_tx_queues != num_txqs ||
1307 qdev->num_rx_queues != num_rxqs) {
1308 qede_dealloc_fp_resc(eth_dev);
1309 qdev->num_tx_queues = num_txqs;
1310 qdev->num_rx_queues = num_rxqs;
1311 if (qede_alloc_fp_resc(qdev))
1312 return -ENOMEM;
1313 }
1314
1315
1316 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
1317 eth_dev->data->mtu =
1318 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1319 RTE_ETHER_HDR_LEN - QEDE_ETH_OVERHEAD;
1320
1321 if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER)
1322 eth_dev->data->scattered_rx = 1;
1323
1324 if (qede_start_vport(qdev, eth_dev->data->mtu))
1325 return -1;
1326
1327 qdev->mtu = eth_dev->data->mtu;
1328
1329
1330 ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK |
1331 ETH_VLAN_FILTER_MASK);
1332 if (ret)
1333 return ret;
1334
1335 DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1336 QEDE_RSS_COUNT(eth_dev), QEDE_TSS_COUNT(eth_dev));
1337
1338 if (ECORE_IS_CMT(edev))
1339 DP_INFO(edev, "Actual HW queues for CMT mode - RX = %d TX = %d\n",
1340 qdev->num_rx_queues, qdev->num_tx_queues);
1341
1342
1343 return 0;
1344}
1345
1346
1347static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1348 .nb_max = 0x8000,
1349 .nb_min = 128,
1350 .nb_align = 128
1351};
1352
1353static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1354 .nb_max = 0x8000,
1355 .nb_min = 256,
1356 .nb_align = 256,
1357 .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1358 .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1359};
1360
1361static int
1362qede_dev_info_get(struct rte_eth_dev *eth_dev,
1363 struct rte_eth_dev_info *dev_info)
1364{
1365 struct qede_dev *qdev = eth_dev->data->dev_private;
1366 struct ecore_dev *edev = &qdev->edev;
1367 struct qed_link_output link;
1368 uint32_t speed_cap = 0;
1369
1370 PMD_INIT_FUNC_TRACE(edev);
1371
1372 dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1373 dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1374 dev_info->rx_desc_lim = qede_rx_desc_lim;
1375 dev_info->tx_desc_lim = qede_tx_desc_lim;
1376
1377 if (IS_PF(edev))
1378 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1379 QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1380 else
1381 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1382 QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1383
1384 if (ECORE_IS_CMT(edev))
1385 dev_info->max_rx_queues = dev_info->max_rx_queues / 2;
1386
1387 dev_info->max_tx_queues = dev_info->max_rx_queues;
1388
1389 dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1390 dev_info->max_vfs = 0;
1391 dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1392 dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1393 dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1394 dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
1395 DEV_RX_OFFLOAD_UDP_CKSUM |
1396 DEV_RX_OFFLOAD_TCP_CKSUM |
1397 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1398 DEV_RX_OFFLOAD_TCP_LRO |
1399 DEV_RX_OFFLOAD_KEEP_CRC |
1400 DEV_RX_OFFLOAD_SCATTER |
1401 DEV_RX_OFFLOAD_JUMBO_FRAME |
1402 DEV_RX_OFFLOAD_VLAN_FILTER |
1403 DEV_RX_OFFLOAD_VLAN_STRIP |
1404 DEV_RX_OFFLOAD_RSS_HASH);
1405 dev_info->rx_queue_offload_capa = 0;
1406
1407
1408
1409
1410 dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1411 DEV_TX_OFFLOAD_IPV4_CKSUM |
1412 DEV_TX_OFFLOAD_UDP_CKSUM |
1413 DEV_TX_OFFLOAD_TCP_CKSUM |
1414 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1415 DEV_TX_OFFLOAD_MULTI_SEGS |
1416 DEV_TX_OFFLOAD_TCP_TSO |
1417 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
1418 DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
1419 dev_info->tx_queue_offload_capa = dev_info->tx_offload_capa;
1420
1421 dev_info->default_txconf = (struct rte_eth_txconf) {
1422 .offloads = DEV_TX_OFFLOAD_MULTI_SEGS,
1423 };
1424
1425 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1426
1427 .rx_drop_en = 1,
1428 .offloads = 0,
1429 };
1430
1431 memset(&link, 0, sizeof(struct qed_link_output));
1432 qdev->ops->common->get_link(edev, &link);
1433 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1434 speed_cap |= ETH_LINK_SPEED_1G;
1435 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1436 speed_cap |= ETH_LINK_SPEED_10G;
1437 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1438 speed_cap |= ETH_LINK_SPEED_25G;
1439 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1440 speed_cap |= ETH_LINK_SPEED_40G;
1441 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1442 speed_cap |= ETH_LINK_SPEED_50G;
1443 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1444 speed_cap |= ETH_LINK_SPEED_100G;
1445 dev_info->speed_capa = speed_cap;
1446
1447 return 0;
1448}
1449
1450
1451int
1452qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1453{
1454 struct qede_dev *qdev = eth_dev->data->dev_private;
1455 struct ecore_dev *edev = &qdev->edev;
1456 struct qed_link_output q_link;
1457 struct rte_eth_link link;
1458 uint16_t link_duplex;
1459
1460 memset(&q_link, 0, sizeof(q_link));
1461 memset(&link, 0, sizeof(link));
1462
1463 qdev->ops->common->get_link(edev, &q_link);
1464
1465
1466 link.link_speed = q_link.speed;
1467
1468
1469 switch (q_link.duplex) {
1470 case QEDE_DUPLEX_HALF:
1471 link_duplex = ETH_LINK_HALF_DUPLEX;
1472 break;
1473 case QEDE_DUPLEX_FULL:
1474 link_duplex = ETH_LINK_FULL_DUPLEX;
1475 break;
1476 case QEDE_DUPLEX_UNKNOWN:
1477 default:
1478 link_duplex = -1;
1479 }
1480 link.link_duplex = link_duplex;
1481
1482
1483 link.link_status = q_link.link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
1484
1485
1486 link.link_autoneg = (q_link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1487 ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1488
1489 DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1490 link.link_speed, link.link_duplex,
1491 link.link_autoneg, link.link_status);
1492
1493 return rte_eth_linkstatus_set(eth_dev, &link);
1494}
1495
1496static int qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1497{
1498 enum _ecore_status_t ecore_status;
1499 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1500 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1501 enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1502
1503 PMD_INIT_FUNC_TRACE(edev);
1504
1505 ecore_status = qed_configure_filter_rx_mode(eth_dev, type);
1506
1507 return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1508}
1509
1510static int qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1511{
1512 struct qede_dev *qdev = eth_dev->data->dev_private;
1513 struct ecore_dev *edev = &qdev->edev;
1514 enum _ecore_status_t ecore_status;
1515
1516 PMD_INIT_FUNC_TRACE(edev);
1517
1518 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1519 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1520 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1521 else
1522 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1523 QED_FILTER_RX_MODE_TYPE_REGULAR);
1524
1525 return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1526}
1527
1528static void qede_poll_sp_sb_cb(void *param)
1529{
1530 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1531 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1532 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1533 int rc;
1534
1535 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1536 qede_interrupt_action(&edev->hwfns[1]);
1537
1538 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
1539 qede_poll_sp_sb_cb,
1540 (void *)eth_dev);
1541 if (rc != 0) {
1542 DP_ERR(edev, "Unable to start periodic"
1543 " timer rc %d\n", rc);
1544 }
1545}
1546
1547static int qede_dev_close(struct rte_eth_dev *eth_dev)
1548{
1549 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1550 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1551 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1552 int ret = 0;
1553
1554 PMD_INIT_FUNC_TRACE(edev);
1555
1556
1557 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1558 return 0;
1559
1560
1561
1562
1563
1564
1565 if (eth_dev->data->dev_started)
1566 ret = qede_dev_stop(eth_dev);
1567
1568 if (qdev->vport_started)
1569 qede_stop_vport(edev);
1570 qdev->vport_started = false;
1571 qede_fdir_dealloc_resc(eth_dev);
1572 qede_dealloc_fp_resc(eth_dev);
1573
1574 eth_dev->data->nb_rx_queues = 0;
1575 eth_dev->data->nb_tx_queues = 0;
1576
1577 qdev->ops->common->slowpath_stop(edev);
1578 qdev->ops->common->remove(edev);
1579 rte_intr_disable(&pci_dev->intr_handle);
1580
1581 switch (pci_dev->intr_handle.type) {
1582 case RTE_INTR_HANDLE_UIO_INTX:
1583 case RTE_INTR_HANDLE_VFIO_LEGACY:
1584 rte_intr_callback_unregister(&pci_dev->intr_handle,
1585 qede_interrupt_handler_intx,
1586 (void *)eth_dev);
1587 break;
1588 default:
1589 rte_intr_callback_unregister(&pci_dev->intr_handle,
1590 qede_interrupt_handler,
1591 (void *)eth_dev);
1592 }
1593
1594 if (ECORE_IS_CMT(edev))
1595 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1596
1597 return ret;
1598}
1599
1600static int
1601qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1602{
1603 struct qede_dev *qdev = eth_dev->data->dev_private;
1604 struct ecore_dev *edev = &qdev->edev;
1605 struct ecore_eth_stats stats;
1606 unsigned int i = 0, j = 0, qid, idx, hw_fn;
1607 unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1608 struct qede_tx_queue *txq;
1609
1610 ecore_get_vport_stats(edev, &stats);
1611
1612
1613 eth_stats->ipackets = stats.common.rx_ucast_pkts +
1614 stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1615
1616 eth_stats->ibytes = stats.common.rx_ucast_bytes +
1617 stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1618
1619 eth_stats->ierrors = stats.common.rx_crc_errors +
1620 stats.common.rx_align_errors +
1621 stats.common.rx_carrier_errors +
1622 stats.common.rx_oversize_packets +
1623 stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1624
1625 eth_stats->rx_nombuf = stats.common.no_buff_discards;
1626
1627 eth_stats->imissed = stats.common.mftag_filter_discards +
1628 stats.common.mac_filter_discards +
1629 stats.common.no_buff_discards +
1630 stats.common.brb_truncates + stats.common.brb_discards;
1631
1632
1633 eth_stats->opackets = stats.common.tx_ucast_pkts +
1634 stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1635
1636 eth_stats->obytes = stats.common.tx_ucast_bytes +
1637 stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1638
1639 eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1640
1641
1642 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(eth_dev),
1643 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1644 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(eth_dev),
1645 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1646 if (rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(eth_dev) ||
1647 txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(eth_dev))
1648 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1649 "Not all the queue stats will be displayed. Set"
1650 " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1651 " appropriately and retry.\n");
1652
1653 for (qid = 0; qid < eth_dev->data->nb_rx_queues; qid++) {
1654 eth_stats->q_ipackets[i] = 0;
1655 eth_stats->q_errors[i] = 0;
1656
1657 for_each_hwfn(edev, hw_fn) {
1658 idx = qid * edev->num_hwfns + hw_fn;
1659
1660 eth_stats->q_ipackets[i] +=
1661 *(uint64_t *)
1662 (((char *)(qdev->fp_array[idx].rxq)) +
1663 offsetof(struct qede_rx_queue,
1664 rcv_pkts));
1665 eth_stats->q_errors[i] +=
1666 *(uint64_t *)
1667 (((char *)(qdev->fp_array[idx].rxq)) +
1668 offsetof(struct qede_rx_queue,
1669 rx_hw_errors)) +
1670 *(uint64_t *)
1671 (((char *)(qdev->fp_array[idx].rxq)) +
1672 offsetof(struct qede_rx_queue,
1673 rx_alloc_errors));
1674 }
1675
1676 i++;
1677 if (i == rxq_stat_cntrs)
1678 break;
1679 }
1680
1681 for (qid = 0; qid < eth_dev->data->nb_tx_queues; qid++) {
1682 eth_stats->q_opackets[j] = 0;
1683
1684 for_each_hwfn(edev, hw_fn) {
1685 idx = qid * edev->num_hwfns + hw_fn;
1686
1687 txq = qdev->fp_array[idx].txq;
1688 eth_stats->q_opackets[j] +=
1689 *((uint64_t *)(uintptr_t)
1690 (((uint64_t)(uintptr_t)(txq)) +
1691 offsetof(struct qede_tx_queue,
1692 xmit_pkts)));
1693 }
1694
1695 j++;
1696 if (j == txq_stat_cntrs)
1697 break;
1698 }
1699
1700 return 0;
1701}
1702
1703static unsigned
1704qede_get_xstats_count(struct qede_dev *qdev) {
1705 struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
1706
1707 if (ECORE_IS_BB(&qdev->edev))
1708 return RTE_DIM(qede_xstats_strings) +
1709 RTE_DIM(qede_bb_xstats_strings) +
1710 (RTE_DIM(qede_rxq_xstats_strings) *
1711 QEDE_RSS_COUNT(dev) * qdev->edev.num_hwfns);
1712 else
1713 return RTE_DIM(qede_xstats_strings) +
1714 RTE_DIM(qede_ah_xstats_strings) +
1715 (RTE_DIM(qede_rxq_xstats_strings) *
1716 QEDE_RSS_COUNT(dev));
1717}
1718
1719static int
1720qede_get_xstats_names(struct rte_eth_dev *dev,
1721 struct rte_eth_xstat_name *xstats_names,
1722 __rte_unused unsigned int limit)
1723{
1724 struct qede_dev *qdev = dev->data->dev_private;
1725 struct ecore_dev *edev = &qdev->edev;
1726 const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1727 unsigned int i, qid, hw_fn, stat_idx = 0;
1728
1729 if (xstats_names == NULL)
1730 return stat_cnt;
1731
1732 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1733 strlcpy(xstats_names[stat_idx].name,
1734 qede_xstats_strings[i].name,
1735 sizeof(xstats_names[stat_idx].name));
1736 stat_idx++;
1737 }
1738
1739 if (ECORE_IS_BB(edev)) {
1740 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1741 strlcpy(xstats_names[stat_idx].name,
1742 qede_bb_xstats_strings[i].name,
1743 sizeof(xstats_names[stat_idx].name));
1744 stat_idx++;
1745 }
1746 } else {
1747 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1748 strlcpy(xstats_names[stat_idx].name,
1749 qede_ah_xstats_strings[i].name,
1750 sizeof(xstats_names[stat_idx].name));
1751 stat_idx++;
1752 }
1753 }
1754
1755 for (qid = 0; qid < QEDE_RSS_COUNT(dev); qid++) {
1756 for_each_hwfn(edev, hw_fn) {
1757 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1758 snprintf(xstats_names[stat_idx].name,
1759 RTE_ETH_XSTATS_NAME_SIZE,
1760 "%.4s%d.%d%s",
1761 qede_rxq_xstats_strings[i].name,
1762 hw_fn, qid,
1763 qede_rxq_xstats_strings[i].name + 4);
1764 stat_idx++;
1765 }
1766 }
1767 }
1768
1769 return stat_cnt;
1770}
1771
1772static int
1773qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1774 unsigned int n)
1775{
1776 struct qede_dev *qdev = dev->data->dev_private;
1777 struct ecore_dev *edev = &qdev->edev;
1778 struct ecore_eth_stats stats;
1779 const unsigned int num = qede_get_xstats_count(qdev);
1780 unsigned int i, qid, hw_fn, fpidx, stat_idx = 0;
1781
1782 if (n < num)
1783 return num;
1784
1785 ecore_get_vport_stats(edev, &stats);
1786
1787 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1788 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1789 qede_xstats_strings[i].offset);
1790 xstats[stat_idx].id = stat_idx;
1791 stat_idx++;
1792 }
1793
1794 if (ECORE_IS_BB(edev)) {
1795 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1796 xstats[stat_idx].value =
1797 *(uint64_t *)(((char *)&stats) +
1798 qede_bb_xstats_strings[i].offset);
1799 xstats[stat_idx].id = stat_idx;
1800 stat_idx++;
1801 }
1802 } else {
1803 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1804 xstats[stat_idx].value =
1805 *(uint64_t *)(((char *)&stats) +
1806 qede_ah_xstats_strings[i].offset);
1807 xstats[stat_idx].id = stat_idx;
1808 stat_idx++;
1809 }
1810 }
1811
1812 for (qid = 0; qid < dev->data->nb_rx_queues; qid++) {
1813 for_each_hwfn(edev, hw_fn) {
1814 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1815 fpidx = qid * edev->num_hwfns + hw_fn;
1816 xstats[stat_idx].value = *(uint64_t *)
1817 (((char *)(qdev->fp_array[fpidx].rxq)) +
1818 qede_rxq_xstats_strings[i].offset);
1819 xstats[stat_idx].id = stat_idx;
1820 stat_idx++;
1821 }
1822
1823 }
1824 }
1825
1826 return stat_idx;
1827}
1828
1829static int
1830qede_reset_xstats(struct rte_eth_dev *dev)
1831{
1832 struct qede_dev *qdev = dev->data->dev_private;
1833 struct ecore_dev *edev = &qdev->edev;
1834
1835 ecore_reset_vport_stats(edev);
1836 qede_reset_queue_stats(qdev, true);
1837
1838 return 0;
1839}
1840
1841int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1842{
1843 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1844 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1845 struct qed_link_params link_params;
1846 int rc;
1847
1848 DP_INFO(edev, "setting link state %d\n", link_up);
1849 memset(&link_params, 0, sizeof(link_params));
1850 link_params.link_up = link_up;
1851 rc = qdev->ops->common->set_link(edev, &link_params);
1852 if (rc != ECORE_SUCCESS)
1853 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1854
1855 return rc;
1856}
1857
1858static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1859{
1860 return qede_dev_set_link_state(eth_dev, true);
1861}
1862
1863static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1864{
1865 return qede_dev_set_link_state(eth_dev, false);
1866}
1867
1868static int qede_reset_stats(struct rte_eth_dev *eth_dev)
1869{
1870 struct qede_dev *qdev = eth_dev->data->dev_private;
1871 struct ecore_dev *edev = &qdev->edev;
1872
1873 ecore_reset_vport_stats(edev);
1874 qede_reset_queue_stats(qdev, false);
1875
1876 return 0;
1877}
1878
1879static int qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1880{
1881 enum qed_filter_rx_mode_type type =
1882 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1883 enum _ecore_status_t ecore_status;
1884
1885 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1886 type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1887 ecore_status = qed_configure_filter_rx_mode(eth_dev, type);
1888
1889 return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1890}
1891
1892static int qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1893{
1894 enum _ecore_status_t ecore_status;
1895
1896 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1897 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1898 QED_FILTER_RX_MODE_TYPE_PROMISC);
1899 else
1900 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1901 QED_FILTER_RX_MODE_TYPE_REGULAR);
1902
1903 return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1904}
1905
1906static int
1907qede_set_mc_addr_list(struct rte_eth_dev *eth_dev,
1908 struct rte_ether_addr *mc_addrs,
1909 uint32_t mc_addrs_num)
1910{
1911 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1912 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1913 uint8_t i;
1914
1915 if (mc_addrs_num > ECORE_MAX_MC_ADDRS) {
1916 DP_ERR(edev, "Reached max multicast filters limit,"
1917 "Please enable multicast promisc mode\n");
1918 return -ENOSPC;
1919 }
1920
1921 for (i = 0; i < mc_addrs_num; i++) {
1922 if (!rte_is_multicast_ether_addr(&mc_addrs[i])) {
1923 DP_ERR(edev, "Not a valid multicast MAC\n");
1924 return -EINVAL;
1925 }
1926 }
1927
1928
1929 if (qede_del_mcast_filters(eth_dev))
1930 return -1;
1931
1932
1933 return qede_add_mcast_filters(eth_dev, mc_addrs, mc_addrs_num);
1934}
1935
1936
1937
1938
1939int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
1940{
1941 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1942 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1943 struct ecore_hwfn *p_hwfn;
1944 int rc;
1945 int i;
1946
1947 if (IS_PF(edev)) {
1948 struct ecore_sp_vport_update_params params;
1949
1950 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
1951 params.vport_id = 0;
1952 params.mtu = mtu;
1953 params.vport_id = 0;
1954 for_each_hwfn(edev, i) {
1955 p_hwfn = &edev->hwfns[i];
1956 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1957 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
1958 ECORE_SPQ_MODE_EBLOCK, NULL);
1959 if (rc != ECORE_SUCCESS)
1960 goto err;
1961 }
1962 } else {
1963 for_each_hwfn(edev, i) {
1964 p_hwfn = &edev->hwfns[i];
1965 rc = ecore_vf_pf_update_mtu(p_hwfn, mtu);
1966 if (rc == ECORE_INVAL) {
1967 DP_INFO(edev, "VF MTU Update TLV not supported\n");
1968
1969 rc = qede_start_vport(qdev, mtu);
1970 if (rc != ECORE_SUCCESS)
1971 goto err;
1972
1973
1974 if (eth_dev->data->promiscuous)
1975 qede_promiscuous_enable(eth_dev);
1976 else
1977 qede_promiscuous_disable(eth_dev);
1978
1979 if (eth_dev->data->all_multicast)
1980 qede_allmulticast_enable(eth_dev);
1981 else
1982 qede_allmulticast_disable(eth_dev);
1983
1984 qede_vlan_offload_set(eth_dev,
1985 qdev->vlan_offload_mask);
1986 } else if (rc != ECORE_SUCCESS) {
1987 goto err;
1988 }
1989 }
1990 }
1991 DP_INFO(edev, "%s MTU updated to %u\n", IS_PF(edev) ? "PF" : "VF", mtu);
1992
1993 return 0;
1994
1995err:
1996 DP_ERR(edev, "Failed to update MTU\n");
1997 return -1;
1998}
1999
2000static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
2001 struct rte_eth_fc_conf *fc_conf)
2002{
2003 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2004 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2005 struct qed_link_output current_link;
2006 struct qed_link_params params;
2007
2008 memset(¤t_link, 0, sizeof(current_link));
2009 qdev->ops->common->get_link(edev, ¤t_link);
2010
2011 memset(¶ms, 0, sizeof(params));
2012 params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
2013 if (fc_conf->autoneg) {
2014 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
2015 DP_ERR(edev, "Autoneg not supported\n");
2016 return -EINVAL;
2017 }
2018 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
2019 }
2020
2021
2022 if (fc_conf->mode == RTE_FC_FULL)
2023 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
2024 QED_LINK_PAUSE_RX_ENABLE);
2025 if (fc_conf->mode == RTE_FC_TX_PAUSE)
2026 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
2027 if (fc_conf->mode == RTE_FC_RX_PAUSE)
2028 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
2029
2030 params.link_up = true;
2031 (void)qdev->ops->common->set_link(edev, ¶ms);
2032
2033 return 0;
2034}
2035
2036static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
2037 struct rte_eth_fc_conf *fc_conf)
2038{
2039 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2040 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2041 struct qed_link_output current_link;
2042
2043 memset(¤t_link, 0, sizeof(current_link));
2044 qdev->ops->common->get_link(edev, ¤t_link);
2045
2046 if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
2047 fc_conf->autoneg = true;
2048
2049 if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
2050 QED_LINK_PAUSE_TX_ENABLE))
2051 fc_conf->mode = RTE_FC_FULL;
2052 else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
2053 fc_conf->mode = RTE_FC_RX_PAUSE;
2054 else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
2055 fc_conf->mode = RTE_FC_TX_PAUSE;
2056 else
2057 fc_conf->mode = RTE_FC_NONE;
2058
2059 return 0;
2060}
2061
2062static const uint32_t *
2063qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
2064{
2065 static const uint32_t ptypes[] = {
2066 RTE_PTYPE_L2_ETHER,
2067 RTE_PTYPE_L2_ETHER_VLAN,
2068 RTE_PTYPE_L3_IPV4,
2069 RTE_PTYPE_L3_IPV6,
2070 RTE_PTYPE_L4_TCP,
2071 RTE_PTYPE_L4_UDP,
2072 RTE_PTYPE_TUNNEL_VXLAN,
2073 RTE_PTYPE_L4_FRAG,
2074 RTE_PTYPE_TUNNEL_GENEVE,
2075 RTE_PTYPE_TUNNEL_GRE,
2076
2077 RTE_PTYPE_INNER_L2_ETHER,
2078 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2079 RTE_PTYPE_INNER_L3_IPV4,
2080 RTE_PTYPE_INNER_L3_IPV6,
2081 RTE_PTYPE_INNER_L4_TCP,
2082 RTE_PTYPE_INNER_L4_UDP,
2083 RTE_PTYPE_INNER_L4_FRAG,
2084 RTE_PTYPE_UNKNOWN
2085 };
2086
2087 if (eth_dev->rx_pkt_burst == qede_recv_pkts ||
2088 eth_dev->rx_pkt_burst == qede_recv_pkts_regular ||
2089 eth_dev->rx_pkt_burst == qede_recv_pkts_cmt)
2090 return ptypes;
2091
2092 return NULL;
2093}
2094
2095static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
2096{
2097 *rss_caps = 0;
2098 *rss_caps |= (hf & ETH_RSS_IPV4) ? ECORE_RSS_IPV4 : 0;
2099 *rss_caps |= (hf & ETH_RSS_IPV6) ? ECORE_RSS_IPV6 : 0;
2100 *rss_caps |= (hf & ETH_RSS_IPV6_EX) ? ECORE_RSS_IPV6 : 0;
2101 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? ECORE_RSS_IPV4_TCP : 0;
2102 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? ECORE_RSS_IPV6_TCP : 0;
2103 *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX) ? ECORE_RSS_IPV6_TCP : 0;
2104 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? ECORE_RSS_IPV4_UDP : 0;
2105 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? ECORE_RSS_IPV6_UDP : 0;
2106}
2107
2108int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
2109 struct rte_eth_rss_conf *rss_conf)
2110{
2111 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2112 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2113 struct ecore_sp_vport_update_params vport_update_params;
2114 struct ecore_rss_params rss_params;
2115 struct ecore_hwfn *p_hwfn;
2116 uint32_t *key = (uint32_t *)rss_conf->rss_key;
2117 uint64_t hf = rss_conf->rss_hf;
2118 uint8_t len = rss_conf->rss_key_len;
2119 uint8_t idx, i, j, fpidx;
2120 int rc;
2121
2122 memset(&vport_update_params, 0, sizeof(vport_update_params));
2123 memset(&rss_params, 0, sizeof(rss_params));
2124
2125 DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
2126 (unsigned long)hf, len, key);
2127
2128 if (hf != 0) {
2129
2130 DP_INFO(edev, "Enabling rss\n");
2131
2132
2133 qede_init_rss_caps(&rss_params.rss_caps, hf);
2134 rss_params.update_rss_capabilities = 1;
2135
2136
2137 if (key) {
2138 if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
2139 len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
2140 DP_NOTICE(edev, false,
2141 "RSS key length too big, trimmed to %d\n",
2142 len);
2143 }
2144 DP_INFO(edev, "Applying user supplied hash key\n");
2145 rss_params.update_rss_key = 1;
2146 memcpy(&rss_params.rss_key, key, len);
2147 }
2148 rss_params.rss_enable = 1;
2149 }
2150
2151 rss_params.update_rss_config = 1;
2152
2153 rss_params.rss_table_size_log = 7;
2154 vport_update_params.vport_id = 0;
2155
2156 for_each_hwfn(edev, i) {
2157
2158 for (j = 0 ; j < ECORE_RSS_IND_TABLE_SIZE ; j++) {
2159 idx = j % QEDE_RSS_COUNT(eth_dev);
2160 fpidx = idx * edev->num_hwfns + i;
2161 rss_params.rss_ind_table[j] =
2162 qdev->fp_array[fpidx].rxq->handle;
2163 }
2164
2165 vport_update_params.rss_params = &rss_params;
2166
2167 p_hwfn = &edev->hwfns[i];
2168 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2169 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2170 ECORE_SPQ_MODE_EBLOCK, NULL);
2171 if (rc) {
2172 DP_ERR(edev, "vport-update for RSS failed\n");
2173 return rc;
2174 }
2175 }
2176 qdev->rss_enable = rss_params.rss_enable;
2177
2178
2179 qdev->rss_conf.rss_hf = hf;
2180 qdev->rss_conf.rss_key_len = len;
2181 if (qdev->rss_enable) {
2182 if (qdev->rss_conf.rss_key == NULL) {
2183 qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
2184 if (qdev->rss_conf.rss_key == NULL) {
2185 DP_ERR(edev, "No memory to store RSS key\n");
2186 return -ENOMEM;
2187 }
2188 }
2189 if (key && len) {
2190 DP_INFO(edev, "Storing RSS key\n");
2191 memcpy(qdev->rss_conf.rss_key, key, len);
2192 }
2193 } else if (!qdev->rss_enable && len == 0) {
2194 if (qdev->rss_conf.rss_key) {
2195 free(qdev->rss_conf.rss_key);
2196 qdev->rss_conf.rss_key = NULL;
2197 DP_INFO(edev, "Free RSS key\n");
2198 }
2199 }
2200
2201 return 0;
2202}
2203
2204static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
2205 struct rte_eth_rss_conf *rss_conf)
2206{
2207 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2208
2209 rss_conf->rss_hf = qdev->rss_conf.rss_hf;
2210 rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
2211
2212 if (rss_conf->rss_key && qdev->rss_conf.rss_key)
2213 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
2214 rss_conf->rss_key_len);
2215 return 0;
2216}
2217
2218int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2219 struct rte_eth_rss_reta_entry64 *reta_conf,
2220 uint16_t reta_size)
2221{
2222 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2223 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2224 struct ecore_sp_vport_update_params vport_update_params;
2225 struct ecore_rss_params *params;
2226 uint16_t i, j, idx, fid, shift;
2227 struct ecore_hwfn *p_hwfn;
2228 uint8_t entry;
2229 int rc = 0;
2230
2231 if (reta_size > ETH_RSS_RETA_SIZE_128) {
2232 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2233 reta_size);
2234 return -EINVAL;
2235 }
2236
2237 memset(&vport_update_params, 0, sizeof(vport_update_params));
2238 params = rte_zmalloc("qede_rss", sizeof(*params), RTE_CACHE_LINE_SIZE);
2239 if (params == NULL) {
2240 DP_ERR(edev, "failed to allocate memory\n");
2241 return -ENOMEM;
2242 }
2243
2244 params->update_rss_ind_table = 1;
2245 params->rss_table_size_log = 7;
2246 params->update_rss_config = 1;
2247
2248 vport_update_params.vport_id = 0;
2249
2250 params->rss_enable = qdev->rss_enable;
2251 vport_update_params.rss_params = params;
2252
2253 for_each_hwfn(edev, i) {
2254 for (j = 0; j < reta_size; j++) {
2255 idx = j / RTE_RETA_GROUP_SIZE;
2256 shift = j % RTE_RETA_GROUP_SIZE;
2257 if (reta_conf[idx].mask & (1ULL << shift)) {
2258 entry = reta_conf[idx].reta[shift];
2259 fid = entry * edev->num_hwfns + i;
2260
2261 params->rss_ind_table[j] =
2262 qdev->fp_array[fid].rxq->handle;
2263
2264 qdev->rss_ind_table[j] = entry;
2265 }
2266 }
2267
2268 p_hwfn = &edev->hwfns[i];
2269 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2270 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2271 ECORE_SPQ_MODE_EBLOCK, NULL);
2272 if (rc) {
2273 DP_ERR(edev, "vport-update for RSS failed\n");
2274 goto out;
2275 }
2276 }
2277
2278out:
2279 rte_free(params);
2280 return rc;
2281}
2282
2283static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2284 struct rte_eth_rss_reta_entry64 *reta_conf,
2285 uint16_t reta_size)
2286{
2287 struct qede_dev *qdev = eth_dev->data->dev_private;
2288 struct ecore_dev *edev = &qdev->edev;
2289 uint16_t i, idx, shift;
2290 uint8_t entry;
2291
2292 if (reta_size > ETH_RSS_RETA_SIZE_128) {
2293 DP_ERR(edev, "reta_size %d is not supported\n",
2294 reta_size);
2295 return -EINVAL;
2296 }
2297
2298 for (i = 0; i < reta_size; i++) {
2299 idx = i / RTE_RETA_GROUP_SIZE;
2300 shift = i % RTE_RETA_GROUP_SIZE;
2301 if (reta_conf[idx].mask & (1ULL << shift)) {
2302 entry = qdev->rss_ind_table[i];
2303 reta_conf[idx].reta[shift] = entry;
2304 }
2305 }
2306
2307 return 0;
2308}
2309
2310
2311
2312static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2313{
2314 struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2315 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2316 struct rte_eth_dev_info dev_info = {0};
2317 struct qede_fastpath *fp;
2318 uint32_t max_rx_pkt_len;
2319 uint32_t frame_size;
2320 uint16_t bufsz;
2321 bool restart = false;
2322 int i, rc;
2323
2324 PMD_INIT_FUNC_TRACE(edev);
2325 rc = qede_dev_info_get(dev, &dev_info);
2326 if (rc != 0) {
2327 DP_ERR(edev, "Error during getting ethernet device info\n");
2328 return rc;
2329 }
2330 max_rx_pkt_len = mtu + QEDE_MAX_ETHER_HDR_LEN;
2331 frame_size = max_rx_pkt_len;
2332 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen) {
2333 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
2334 mtu, dev_info.max_rx_pktlen - RTE_ETHER_HDR_LEN -
2335 QEDE_ETH_OVERHEAD);
2336 return -EINVAL;
2337 }
2338 if (!dev->data->scattered_rx &&
2339 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2340 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2341 dev->data->min_rx_buf_size);
2342 return -EINVAL;
2343 }
2344 if (dev->data->dev_started) {
2345 dev->data->dev_started = 0;
2346 rc = qede_dev_stop(dev);
2347 if (rc != 0)
2348 return rc;
2349 restart = true;
2350 }
2351 rte_delay_ms(1000);
2352 qdev->new_mtu = mtu;
2353
2354
2355 for (i = 0; i < qdev->num_rx_queues; i++) {
2356 fp = &qdev->fp_array[i];
2357 if (fp->rxq != NULL) {
2358 bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2359 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2360
2361
2362
2363 bufsz = QEDE_FLOOR_TO_CACHE_LINE_SIZE(bufsz);
2364 rc = qede_calc_rx_buf_size(dev, bufsz, frame_size);
2365 if (rc < 0)
2366 return rc;
2367
2368 fp->rxq->rx_buf_size = rc;
2369 }
2370 }
2371 if (frame_size > QEDE_ETH_MAX_LEN)
2372 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2373 else
2374 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2375
2376 if (!dev->data->dev_started && restart) {
2377 qede_dev_start(dev);
2378 dev->data->dev_started = 1;
2379 }
2380
2381
2382 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;
2383
2384 return 0;
2385}
2386
2387static int
2388qede_dev_reset(struct rte_eth_dev *dev)
2389{
2390 int ret;
2391
2392 ret = qede_eth_dev_uninit(dev);
2393 if (ret)
2394 return ret;
2395
2396 return qede_eth_dev_init(dev);
2397}
2398
2399static const struct eth_dev_ops qede_eth_dev_ops = {
2400 .dev_configure = qede_dev_configure,
2401 .dev_infos_get = qede_dev_info_get,
2402 .rx_queue_setup = qede_rx_queue_setup,
2403 .rx_queue_release = qede_rx_queue_release,
2404 .tx_queue_setup = qede_tx_queue_setup,
2405 .tx_queue_release = qede_tx_queue_release,
2406 .dev_start = qede_dev_start,
2407 .dev_reset = qede_dev_reset,
2408 .dev_set_link_up = qede_dev_set_link_up,
2409 .dev_set_link_down = qede_dev_set_link_down,
2410 .link_update = qede_link_update,
2411 .promiscuous_enable = qede_promiscuous_enable,
2412 .promiscuous_disable = qede_promiscuous_disable,
2413 .allmulticast_enable = qede_allmulticast_enable,
2414 .allmulticast_disable = qede_allmulticast_disable,
2415 .set_mc_addr_list = qede_set_mc_addr_list,
2416 .dev_stop = qede_dev_stop,
2417 .dev_close = qede_dev_close,
2418 .stats_get = qede_get_stats,
2419 .stats_reset = qede_reset_stats,
2420 .xstats_get = qede_get_xstats,
2421 .xstats_reset = qede_reset_xstats,
2422 .xstats_get_names = qede_get_xstats_names,
2423 .mac_addr_add = qede_mac_addr_add,
2424 .mac_addr_remove = qede_mac_addr_remove,
2425 .mac_addr_set = qede_mac_addr_set,
2426 .vlan_offload_set = qede_vlan_offload_set,
2427 .vlan_filter_set = qede_vlan_filter_set,
2428 .flow_ctrl_set = qede_flow_ctrl_set,
2429 .flow_ctrl_get = qede_flow_ctrl_get,
2430 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2431 .rss_hash_update = qede_rss_hash_update,
2432 .rss_hash_conf_get = qede_rss_hash_conf_get,
2433 .reta_update = qede_rss_reta_update,
2434 .reta_query = qede_rss_reta_query,
2435 .mtu_set = qede_set_mtu,
2436 .flow_ops_get = qede_dev_flow_ops_get,
2437 .udp_tunnel_port_add = qede_udp_dst_port_add,
2438 .udp_tunnel_port_del = qede_udp_dst_port_del,
2439 .fw_version_get = qede_fw_version_get,
2440 .get_reg = qede_get_regs,
2441};
2442
2443static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2444 .dev_configure = qede_dev_configure,
2445 .dev_infos_get = qede_dev_info_get,
2446 .rx_queue_setup = qede_rx_queue_setup,
2447 .rx_queue_release = qede_rx_queue_release,
2448 .tx_queue_setup = qede_tx_queue_setup,
2449 .tx_queue_release = qede_tx_queue_release,
2450 .dev_start = qede_dev_start,
2451 .dev_reset = qede_dev_reset,
2452 .dev_set_link_up = qede_dev_set_link_up,
2453 .dev_set_link_down = qede_dev_set_link_down,
2454 .link_update = qede_link_update,
2455 .promiscuous_enable = qede_promiscuous_enable,
2456 .promiscuous_disable = qede_promiscuous_disable,
2457 .allmulticast_enable = qede_allmulticast_enable,
2458 .allmulticast_disable = qede_allmulticast_disable,
2459 .set_mc_addr_list = qede_set_mc_addr_list,
2460 .dev_stop = qede_dev_stop,
2461 .dev_close = qede_dev_close,
2462 .stats_get = qede_get_stats,
2463 .stats_reset = qede_reset_stats,
2464 .xstats_get = qede_get_xstats,
2465 .xstats_reset = qede_reset_xstats,
2466 .xstats_get_names = qede_get_xstats_names,
2467 .vlan_offload_set = qede_vlan_offload_set,
2468 .vlan_filter_set = qede_vlan_filter_set,
2469 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2470 .rss_hash_update = qede_rss_hash_update,
2471 .rss_hash_conf_get = qede_rss_hash_conf_get,
2472 .reta_update = qede_rss_reta_update,
2473 .reta_query = qede_rss_reta_query,
2474 .mtu_set = qede_set_mtu,
2475 .udp_tunnel_port_add = qede_udp_dst_port_add,
2476 .udp_tunnel_port_del = qede_udp_dst_port_del,
2477 .mac_addr_add = qede_mac_addr_add,
2478 .mac_addr_remove = qede_mac_addr_remove,
2479 .mac_addr_set = qede_mac_addr_set,
2480 .fw_version_get = qede_fw_version_get,
2481};
2482
2483static void qede_update_pf_params(struct ecore_dev *edev)
2484{
2485 struct ecore_pf_params pf_params;
2486
2487 memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2488 pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2489 pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2490 qed_ops->common->update_pf_params(edev, &pf_params);
2491}
2492
2493static void qede_generate_random_mac_addr(struct rte_ether_addr *mac_addr)
2494{
2495 uint64_t random;
2496
2497
2498 mac_addr->addr_bytes[0] = 0x00;
2499 mac_addr->addr_bytes[1] = 0x09;
2500 mac_addr->addr_bytes[2] = 0xC0;
2501
2502
2503 mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
2504
2505
2506 random = rte_rand();
2507
2508 memcpy(&mac_addr->addr_bytes[3], &random, 3);
2509}
2510
2511static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2512{
2513 struct rte_pci_device *pci_dev;
2514 struct rte_pci_addr pci_addr;
2515 struct qede_dev *adapter;
2516 struct ecore_dev *edev;
2517 struct qed_dev_eth_info dev_info;
2518 struct qed_slowpath_params params;
2519 static bool do_once = true;
2520 uint8_t bulletin_change;
2521 uint8_t vf_mac[RTE_ETHER_ADDR_LEN];
2522 uint8_t is_mac_forced;
2523 bool is_mac_exist = false;
2524
2525 uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2526 uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2527 uint32_t int_mode;
2528 int rc;
2529
2530
2531 adapter = eth_dev->data->dev_private;
2532 adapter->ethdev = eth_dev;
2533 edev = &adapter->edev;
2534 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2535 pci_addr = pci_dev->addr;
2536
2537 PMD_INIT_FUNC_TRACE(edev);
2538
2539 snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2540 pci_addr.bus, pci_addr.devid, pci_addr.function,
2541 eth_dev->data->port_id);
2542
2543 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2544 DP_ERR(edev, "Skipping device init from secondary process\n");
2545 return 0;
2546 }
2547
2548 rte_eth_copy_pci_info(eth_dev, pci_dev);
2549 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2550
2551
2552 edev->vendor_id = pci_dev->id.vendor_id;
2553 edev->device_id = pci_dev->id.device_id;
2554
2555 qed_ops = qed_get_eth_ops();
2556 if (!qed_ops) {
2557 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2558 rc = -EINVAL;
2559 goto err;
2560 }
2561
2562 DP_INFO(edev, "Starting qede probe\n");
2563 rc = qed_ops->common->probe(edev, pci_dev, dp_module,
2564 dp_level, is_vf);
2565 if (rc != 0) {
2566 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2567 rc = -ENODEV;
2568 goto err;
2569 }
2570 qede_update_pf_params(edev);
2571
2572 switch (pci_dev->intr_handle.type) {
2573 case RTE_INTR_HANDLE_UIO_INTX:
2574 case RTE_INTR_HANDLE_VFIO_LEGACY:
2575 int_mode = ECORE_INT_MODE_INTA;
2576 rte_intr_callback_register(&pci_dev->intr_handle,
2577 qede_interrupt_handler_intx,
2578 (void *)eth_dev);
2579 break;
2580 default:
2581 int_mode = ECORE_INT_MODE_MSIX;
2582 rte_intr_callback_register(&pci_dev->intr_handle,
2583 qede_interrupt_handler,
2584 (void *)eth_dev);
2585 }
2586
2587 if (rte_intr_enable(&pci_dev->intr_handle)) {
2588 DP_ERR(edev, "rte_intr_enable() failed\n");
2589 rc = -ENODEV;
2590 goto err;
2591 }
2592
2593
2594 memset(¶ms, 0, sizeof(struct qed_slowpath_params));
2595
2596 params.int_mode = int_mode;
2597 params.drv_major = QEDE_PMD_VERSION_MAJOR;
2598 params.drv_minor = QEDE_PMD_VERSION_MINOR;
2599 params.drv_rev = QEDE_PMD_VERSION_REVISION;
2600 params.drv_eng = QEDE_PMD_VERSION_PATCH;
2601 strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2602 QEDE_PMD_DRV_VER_STR_SIZE);
2603
2604 qede_assign_rxtx_handlers(eth_dev, true);
2605 eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2606
2607
2608
2609
2610
2611 if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
2612 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
2613 qede_poll_sp_sb_cb,
2614 (void *)eth_dev);
2615 if (rc != 0) {
2616 DP_ERR(edev, "Unable to start periodic"
2617 " timer rc %d\n", rc);
2618 rc = -EINVAL;
2619 goto err;
2620 }
2621 }
2622
2623 rc = qed_ops->common->slowpath_start(edev, ¶ms);
2624 if (rc) {
2625 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2626 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2627 (void *)eth_dev);
2628 rc = -ENODEV;
2629 goto err;
2630 }
2631
2632 rc = qed_ops->fill_dev_info(edev, &dev_info);
2633 if (rc) {
2634 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2635 qed_ops->common->slowpath_stop(edev);
2636 qed_ops->common->remove(edev);
2637 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2638 (void *)eth_dev);
2639 rc = -ENODEV;
2640 goto err;
2641 }
2642
2643 qede_alloc_etherdev(adapter, &dev_info);
2644
2645 if (do_once) {
2646 qede_print_adapter_info(eth_dev);
2647 do_once = false;
2648 }
2649
2650 adapter->ops->common->set_name(edev, edev->name);
2651
2652 if (!is_vf)
2653 adapter->dev_info.num_mac_filters =
2654 (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2655 ECORE_MAC);
2656 else
2657 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2658 (uint32_t *)&adapter->dev_info.num_mac_filters);
2659
2660
2661 eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2662 (RTE_ETHER_ADDR_LEN *
2663 adapter->dev_info.num_mac_filters),
2664 RTE_CACHE_LINE_SIZE);
2665
2666 if (eth_dev->data->mac_addrs == NULL) {
2667 DP_ERR(edev, "Failed to allocate MAC address\n");
2668 qed_ops->common->slowpath_stop(edev);
2669 qed_ops->common->remove(edev);
2670 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2671 (void *)eth_dev);
2672 return -ENOMEM;
2673 }
2674
2675 if (!is_vf) {
2676 rte_ether_addr_copy((struct rte_ether_addr *)edev->hwfns[0].
2677 hw_info.hw_mac_addr,
2678 ð_dev->data->mac_addrs[0]);
2679 rte_ether_addr_copy(ð_dev->data->mac_addrs[0],
2680 &adapter->primary_mac);
2681 } else {
2682 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2683 &bulletin_change);
2684 if (bulletin_change) {
2685 is_mac_exist =
2686 ecore_vf_bulletin_get_forced_mac(
2687 ECORE_LEADING_HWFN(edev),
2688 vf_mac,
2689 &is_mac_forced);
2690 if (is_mac_exist) {
2691 DP_INFO(edev, "VF macaddr received from PF\n");
2692 rte_ether_addr_copy(
2693 (struct rte_ether_addr *)&vf_mac,
2694 ð_dev->data->mac_addrs[0]);
2695 rte_ether_addr_copy(
2696 ð_dev->data->mac_addrs[0],
2697 &adapter->primary_mac);
2698 } else {
2699 DP_ERR(edev, "No VF macaddr assigned\n");
2700 }
2701 }
2702
2703
2704 if (!is_mac_exist) {
2705 struct rte_ether_addr *mac_addr;
2706
2707 mac_addr = (struct rte_ether_addr *)&vf_mac;
2708 qede_generate_random_mac_addr(mac_addr);
2709
2710 rte_ether_addr_copy(mac_addr,
2711 ð_dev->data->mac_addrs[0]);
2712
2713 rte_ether_addr_copy(ð_dev->data->mac_addrs[0],
2714 &adapter->primary_mac);
2715 }
2716 }
2717
2718 eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2719 eth_dev->rx_descriptor_status = qede_rx_descriptor_status;
2720
2721 adapter->num_tx_queues = 0;
2722 adapter->num_rx_queues = 0;
2723 SLIST_INIT(&adapter->arfs_info.arfs_list_head);
2724 SLIST_INIT(&adapter->vlan_list_head);
2725 SLIST_INIT(&adapter->uc_list_head);
2726 SLIST_INIT(&adapter->mc_list_head);
2727 adapter->mtu = RTE_ETHER_MTU;
2728 adapter->vport_started = false;
2729
2730
2731 adapter->vxlan.num_filters = 0;
2732 adapter->geneve.num_filters = 0;
2733 adapter->ipgre.num_filters = 0;
2734 if (is_vf) {
2735 adapter->vxlan.enable = true;
2736 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
2737 ETH_TUNNEL_FILTER_IVLAN;
2738 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT;
2739 adapter->geneve.enable = true;
2740 adapter->geneve.filter_type = ETH_TUNNEL_FILTER_IMAC |
2741 ETH_TUNNEL_FILTER_IVLAN;
2742 adapter->geneve.udp_port = QEDE_GENEVE_DEF_PORT;
2743 adapter->ipgre.enable = true;
2744 adapter->ipgre.filter_type = ETH_TUNNEL_FILTER_IMAC |
2745 ETH_TUNNEL_FILTER_IVLAN;
2746 } else {
2747 adapter->vxlan.enable = false;
2748 adapter->geneve.enable = false;
2749 adapter->ipgre.enable = false;
2750 qed_ops->sriov_configure(edev, pci_dev->max_vfs);
2751 }
2752
2753 DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2754 adapter->primary_mac.addr_bytes[0],
2755 adapter->primary_mac.addr_bytes[1],
2756 adapter->primary_mac.addr_bytes[2],
2757 adapter->primary_mac.addr_bytes[3],
2758 adapter->primary_mac.addr_bytes[4],
2759 adapter->primary_mac.addr_bytes[5]);
2760
2761 DP_INFO(edev, "Device initialized\n");
2762
2763 return 0;
2764
2765err:
2766 if (do_once) {
2767 qede_print_adapter_info(eth_dev);
2768 do_once = false;
2769 }
2770 return rc;
2771}
2772
2773static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2774{
2775 return qede_common_dev_init(eth_dev, 1);
2776}
2777
2778static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2779{
2780 return qede_common_dev_init(eth_dev, 0);
2781}
2782
2783static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2784{
2785 struct qede_dev *qdev = eth_dev->data->dev_private;
2786 struct ecore_dev *edev = &qdev->edev;
2787 PMD_INIT_FUNC_TRACE(edev);
2788 qede_dev_close(eth_dev);
2789 return 0;
2790}
2791
2792static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2793{
2794 return qede_dev_common_uninit(eth_dev);
2795}
2796
2797static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2798{
2799 return qede_dev_common_uninit(eth_dev);
2800}
2801
2802static const struct rte_pci_id pci_id_qedevf_map[] = {
2803#define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2804 {
2805 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
2806 },
2807 {
2808 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
2809 },
2810 {
2811 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
2812 },
2813 {.vendor_id = 0,}
2814};
2815
2816static const struct rte_pci_id pci_id_qede_map[] = {
2817#define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2818 {
2819 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
2820 },
2821 {
2822 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
2823 },
2824 {
2825 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
2826 },
2827 {
2828 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
2829 },
2830 {
2831 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
2832 },
2833 {
2834 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
2835 },
2836 {
2837 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
2838 },
2839 {
2840 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
2841 },
2842 {
2843 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
2844 },
2845 {
2846 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
2847 },
2848 {.vendor_id = 0,}
2849};
2850
2851static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2852 struct rte_pci_device *pci_dev)
2853{
2854 return rte_eth_dev_pci_generic_probe(pci_dev,
2855 sizeof(struct qede_dev), qedevf_eth_dev_init);
2856}
2857
2858static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2859{
2860 return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
2861}
2862
2863static struct rte_pci_driver rte_qedevf_pmd = {
2864 .id_table = pci_id_qedevf_map,
2865 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2866 .probe = qedevf_eth_dev_pci_probe,
2867 .remove = qedevf_eth_dev_pci_remove,
2868};
2869
2870static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2871 struct rte_pci_device *pci_dev)
2872{
2873 return rte_eth_dev_pci_generic_probe(pci_dev,
2874 sizeof(struct qede_dev), qede_eth_dev_init);
2875}
2876
2877static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2878{
2879 return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
2880}
2881
2882static struct rte_pci_driver rte_qede_pmd = {
2883 .id_table = pci_id_qede_map,
2884 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2885 .probe = qede_eth_dev_pci_probe,
2886 .remove = qede_eth_dev_pci_remove,
2887};
2888
2889RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
2890RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2891RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
2892RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
2893RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2894RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");
2895RTE_LOG_REGISTER_SUFFIX(qede_logtype_init, init, NOTICE);
2896RTE_LOG_REGISTER_SUFFIX(qede_logtype_driver, driver, NOTICE);
2897
