1
2
3
4
5
6
7#include <limits.h>
8
9#include <rte_alarm.h>
10#include <rte_string_fns.h>
11
12#include "eal_firmware.h"
13
14#include "qede_ethdev.h"
15
16#include "qede_debug.h"
17
18
19#define QEDE_ALARM_TIMEOUT_US 100000
20
21
22char qede_fw_file[PATH_MAX];
23
24static const char * const QEDE_DEFAULT_FIRMWARE =
25 "/lib/firmware/qed/qed_init_values-8.40.33.0.bin";
26
27static void
28qed_update_pf_params(struct ecore_dev *edev, struct ecore_pf_params *params)
29{
30 int i;
31
32 for (i = 0; i < edev->num_hwfns; i++) {
33 struct ecore_hwfn *p_hwfn = &edev->hwfns[i];
34 p_hwfn->pf_params = *params;
35 }
36}
37
38static void qed_init_pci(struct ecore_dev *edev, struct rte_pci_device *pci_dev)
39{
40 edev->regview = pci_dev->mem_resource[0].addr;
41 edev->doorbells = pci_dev->mem_resource[2].addr;
42 edev->db_size = pci_dev->mem_resource[2].len;
43 edev->pci_dev = pci_dev;
44}
45
46static int
47qed_probe(struct ecore_dev *edev, struct rte_pci_device *pci_dev,
48 uint32_t dp_module, uint8_t dp_level, bool is_vf)
49{
50 struct ecore_hw_prepare_params hw_prepare_params;
51 int rc;
52
53 ecore_init_struct(edev);
54 edev->drv_type = DRV_ID_DRV_TYPE_LINUX;
55
56
57 if (is_vf)
58 edev->b_is_vf = true;
59
60 ecore_init_dp(edev, dp_module, dp_level, NULL);
61 qed_init_pci(edev, pci_dev);
62
63 memset(&hw_prepare_params, 0, sizeof(hw_prepare_params));
64
65 if (is_vf)
66 hw_prepare_params.acquire_retry_cnt = ECORE_VF_ACQUIRE_THRESH;
67
68 hw_prepare_params.personality = ECORE_PCI_ETH;
69 hw_prepare_params.drv_resc_alloc = false;
70 hw_prepare_params.chk_reg_fifo = false;
71 hw_prepare_params.initiate_pf_flr = true;
72 hw_prepare_params.allow_mdump = false;
73 hw_prepare_params.b_en_pacing = false;
74 hw_prepare_params.epoch = OSAL_GET_EPOCH(ECORE_LEADING_HWFN(edev));
75 rc = ecore_hw_prepare(edev, &hw_prepare_params);
76 if (rc) {
77 DP_ERR(edev, "hw prepare failed\n");
78 return rc;
79 }
80
81 return rc;
82}
83
84static int qed_nic_setup(struct ecore_dev *edev)
85{
86 int rc;
87
88 rc = ecore_resc_alloc(edev);
89 if (rc)
90 return rc;
91
92 DP_INFO(edev, "Allocated qed resources\n");
93 ecore_resc_setup(edev);
94
95 return rc;
96}
97
98#ifdef CONFIG_ECORE_ZIPPED_FW
99static int qed_alloc_stream_mem(struct ecore_dev *edev)
100{
101 int i;
102
103 for_each_hwfn(edev, i) {
104 struct ecore_hwfn *p_hwfn = &edev->hwfns[i];
105
106 p_hwfn->stream = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
107 sizeof(*p_hwfn->stream));
108 if (!p_hwfn->stream)
109 return -ENOMEM;
110 }
111
112 return 0;
113}
114
115static void qed_free_stream_mem(struct ecore_dev *edev)
116{
117 int i;
118
119 for_each_hwfn(edev, i) {
120 struct ecore_hwfn *p_hwfn = &edev->hwfns[i];
121
122 if (!p_hwfn->stream)
123 return;
124
125 OSAL_FREE(p_hwfn->p_dev, p_hwfn->stream);
126 }
127}
128#endif
129
130#ifdef CONFIG_ECORE_BINARY_FW
131static int qed_load_firmware_data(struct ecore_dev *edev)
132{
133 const char *fw = RTE_LIBRTE_QEDE_FW;
134 void *buf;
135 size_t bufsz;
136 int ret;
137
138 if (strcmp(fw, "") == 0)
139 strcpy(qede_fw_file, QEDE_DEFAULT_FIRMWARE);
140 else
141 strcpy(qede_fw_file, fw);
142
143 if (rte_firmware_read(qede_fw_file, &buf, &bufsz) < 0) {
144 DP_ERR(edev, "Can't read firmware data: %s\n", qede_fw_file);
145 return -1;
146 }
147
148 edev->firmware = rte_zmalloc("qede_fw", bufsz, RTE_CACHE_LINE_SIZE);
149 if (!edev->firmware) {
150 DP_ERR(edev, "Can't allocate memory for firmware\n");
151 ret = -ENOMEM;
152 goto out;
153 }
154
155 memcpy(edev->firmware, buf, bufsz);
156 edev->fw_len = bufsz;
157 if (edev->fw_len < 104) {
158 DP_ERR(edev, "Invalid fw size: %" PRIu64 "\n",
159 edev->fw_len);
160 ret = -EINVAL;
161 goto out;
162 }
163 ret = 0;
164out:
165 free(buf);
166 return ret;
167}
168#endif
169
170static void qed_handle_bulletin_change(struct ecore_hwfn *hwfn)
171{
172 uint8_t mac[ETH_ALEN], is_mac_exist, is_mac_forced;
173
174 is_mac_exist = ecore_vf_bulletin_get_forced_mac(hwfn, mac,
175 &is_mac_forced);
176 if (is_mac_exist && is_mac_forced)
177 rte_memcpy(hwfn->hw_info.hw_mac_addr, mac, ETH_ALEN);
178
179
180 qed_link_update(hwfn);
181}
182
183static void qede_vf_task(void *arg)
184{
185 struct ecore_hwfn *p_hwfn = arg;
186 uint8_t change = 0;
187
188
189 ecore_vf_read_bulletin(p_hwfn, &change);
190 if (change)
191 qed_handle_bulletin_change(p_hwfn);
192
193 rte_eal_alarm_set(QEDE_ALARM_TIMEOUT_US, qede_vf_task, p_hwfn);
194}
195
196static void qed_start_iov_task(struct ecore_dev *edev)
197{
198 struct ecore_hwfn *p_hwfn;
199 int i;
200
201 for_each_hwfn(edev, i) {
202 p_hwfn = &edev->hwfns[i];
203 if (!IS_PF(edev))
204 rte_eal_alarm_set(QEDE_ALARM_TIMEOUT_US, qede_vf_task,
205 p_hwfn);
206 }
207}
208
209static void qed_stop_iov_task(struct ecore_dev *edev)
210{
211 struct ecore_hwfn *p_hwfn;
212 int i;
213
214 for_each_hwfn(edev, i) {
215 p_hwfn = &edev->hwfns[i];
216 if (IS_PF(edev))
217 rte_eal_alarm_cancel(qed_iov_pf_task, p_hwfn);
218 else
219 rte_eal_alarm_cancel(qede_vf_task, p_hwfn);
220 }
221}
222static int qed_slowpath_start(struct ecore_dev *edev,
223 struct qed_slowpath_params *params)
224{
225 struct ecore_drv_load_params drv_load_params;
226 struct ecore_hw_init_params hw_init_params;
227 struct ecore_mcp_drv_version drv_version;
228 const uint8_t *data = NULL;
229 struct ecore_hwfn *hwfn;
230 struct ecore_ptt *p_ptt;
231 int rc;
232
233 if (IS_PF(edev)) {
234#ifdef CONFIG_ECORE_BINARY_FW
235 rc = qed_load_firmware_data(edev);
236 if (rc) {
237 DP_ERR(edev, "Failed to find fw file %s\n",
238 qede_fw_file);
239 goto err;
240 }
241#endif
242 hwfn = ECORE_LEADING_HWFN(edev);
243 if (edev->num_hwfns == 1) {
244 p_ptt = ecore_ptt_acquire(hwfn);
245 if (p_ptt) {
246 ECORE_LEADING_HWFN(edev)->p_arfs_ptt = p_ptt;
247 } else {
248 DP_ERR(edev, "Failed to acquire PTT for flowdir\n");
249 rc = -ENOMEM;
250 goto err;
251 }
252 }
253 }
254
255 rc = qed_nic_setup(edev);
256 if (rc)
257 goto err;
258
259
260 edev->int_coalescing_mode = ECORE_COAL_MODE_ENABLE;
261
262#ifdef CONFIG_ECORE_ZIPPED_FW
263 if (IS_PF(edev)) {
264
265 rc = qed_alloc_stream_mem(edev);
266 if (rc) {
267 DP_ERR(edev, "Failed to allocate stream memory\n");
268 goto err1;
269 }
270 }
271#endif
272
273 qed_start_iov_task(edev);
274
275#ifdef CONFIG_ECORE_BINARY_FW
276 if (IS_PF(edev)) {
277 data = (const uint8_t *)edev->firmware + sizeof(u32);
278
279
280 qed_dbg_pf_init(edev);
281 }
282#endif
283
284
285
286 memset(&hw_init_params, 0, sizeof(hw_init_params));
287 hw_init_params.b_hw_start = true;
288 hw_init_params.int_mode = params->int_mode;
289 hw_init_params.allow_npar_tx_switch = true;
290 hw_init_params.bin_fw_data = data;
291
292 memset(&drv_load_params, 0, sizeof(drv_load_params));
293 drv_load_params.mfw_timeout_val = ECORE_LOAD_REQ_LOCK_TO_DEFAULT;
294 drv_load_params.avoid_eng_reset = false;
295 drv_load_params.override_force_load = ECORE_OVERRIDE_FORCE_LOAD_ALWAYS;
296 hw_init_params.avoid_eng_affin = false;
297 hw_init_params.p_drv_load_params = &drv_load_params;
298
299 rc = ecore_hw_init(edev, &hw_init_params);
300 if (rc) {
301 DP_ERR(edev, "ecore_hw_init failed\n");
302 goto err2;
303 }
304
305 DP_INFO(edev, "HW inited and function started\n");
306
307 if (IS_PF(edev)) {
308 hwfn = ECORE_LEADING_HWFN(edev);
309 drv_version.version = (params->drv_major << 24) |
310 (params->drv_minor << 16) |
311 (params->drv_rev << 8) | (params->drv_eng);
312 strlcpy((char *)drv_version.name, (const char *)params->name,
313 sizeof(drv_version.name));
314 rc = ecore_mcp_send_drv_version(hwfn, hwfn->p_main_ptt,
315 &drv_version);
316 if (rc) {
317 DP_ERR(edev, "Failed sending drv version command\n");
318 goto err3;
319 }
320 }
321
322 ecore_reset_vport_stats(edev);
323
324 return 0;
325
326err3:
327 ecore_hw_stop(edev);
328err2:
329 qed_stop_iov_task(edev);
330#ifdef CONFIG_ECORE_ZIPPED_FW
331 qed_free_stream_mem(edev);
332err1:
333#endif
334 ecore_resc_free(edev);
335err:
336#ifdef CONFIG_ECORE_BINARY_FW
337 if (IS_PF(edev)) {
338 if (edev->firmware)
339 rte_free(edev->firmware);
340 edev->firmware = NULL;
341 }
342#endif
343 qed_stop_iov_task(edev);
344
345 return rc;
346}
347
348static int
349qed_fill_dev_info(struct ecore_dev *edev, struct qed_dev_info *dev_info)
350{
351 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(edev);
352 struct ecore_ptt *ptt = NULL;
353 struct ecore_tunnel_info *tun = &edev->tunnel;
354
355 memset(dev_info, 0, sizeof(struct qed_dev_info));
356
357 if (tun->vxlan.tun_cls == ECORE_TUNN_CLSS_MAC_VLAN &&
358 tun->vxlan.b_mode_enabled)
359 dev_info->vxlan_enable = true;
360
361 if (tun->l2_gre.b_mode_enabled && tun->ip_gre.b_mode_enabled &&
362 tun->l2_gre.tun_cls == ECORE_TUNN_CLSS_MAC_VLAN &&
363 tun->ip_gre.tun_cls == ECORE_TUNN_CLSS_MAC_VLAN)
364 dev_info->gre_enable = true;
365
366 if (tun->l2_geneve.b_mode_enabled && tun->ip_geneve.b_mode_enabled &&
367 tun->l2_geneve.tun_cls == ECORE_TUNN_CLSS_MAC_VLAN &&
368 tun->ip_geneve.tun_cls == ECORE_TUNN_CLSS_MAC_VLAN)
369 dev_info->geneve_enable = true;
370
371 dev_info->num_hwfns = edev->num_hwfns;
372 dev_info->is_mf_default = IS_MF_DEFAULT(&edev->hwfns[0]);
373 dev_info->mtu = ECORE_LEADING_HWFN(edev)->hw_info.mtu;
374 dev_info->dev_type = edev->type;
375
376 rte_memcpy(&dev_info->hw_mac, &edev->hwfns[0].hw_info.hw_mac_addr,
377 RTE_ETHER_ADDR_LEN);
378
379 dev_info->fw_major = FW_MAJOR_VERSION;
380 dev_info->fw_minor = FW_MINOR_VERSION;
381 dev_info->fw_rev = FW_REVISION_VERSION;
382 dev_info->fw_eng = FW_ENGINEERING_VERSION;
383
384 if (IS_PF(edev)) {
385 dev_info->b_inter_pf_switch =
386 OSAL_GET_BIT(ECORE_MF_INTER_PF_SWITCH, &edev->mf_bits);
387 if (!OSAL_GET_BIT(ECORE_MF_DISABLE_ARFS, &edev->mf_bits))
388 dev_info->b_arfs_capable = true;
389 dev_info->tx_switching = false;
390
391 dev_info->smart_an = ecore_mcp_is_smart_an_supported(p_hwfn);
392
393 ptt = ecore_ptt_acquire(ECORE_LEADING_HWFN(edev));
394 if (ptt) {
395 ecore_mcp_get_mfw_ver(ECORE_LEADING_HWFN(edev), ptt,
396 &dev_info->mfw_rev, NULL);
397
398 ecore_mcp_get_mbi_ver(ECORE_LEADING_HWFN(edev), ptt,
399 &dev_info->mbi_version);
400
401 ecore_mcp_get_flash_size(ECORE_LEADING_HWFN(edev), ptt,
402 &dev_info->flash_size);
403
404
405
406
407 if (ECORE_IS_BB_B0(edev))
408 dev_info->flash_size = 0xffffffff;
409
410 ecore_ptt_release(ECORE_LEADING_HWFN(edev), ptt);
411 }
412 } else {
413 ecore_mcp_get_mfw_ver(ECORE_LEADING_HWFN(edev), ptt,
414 &dev_info->mfw_rev, NULL);
415 }
416
417 return 0;
418}
419
420int
421qed_fill_eth_dev_info(struct ecore_dev *edev, struct qed_dev_eth_info *info)
422{
423 uint8_t queues = 0;
424 int i;
425
426 memset(info, 0, sizeof(*info));
427
428 info->num_tc = 1 ;
429
430 if (IS_PF(edev)) {
431 int max_vf_vlan_filters = 0;
432
433 info->num_queues = 0;
434 for_each_hwfn(edev, i)
435 info->num_queues +=
436 FEAT_NUM(&edev->hwfns[i], ECORE_PF_L2_QUE);
437
438 if (IS_ECORE_SRIOV(edev))
439 max_vf_vlan_filters = edev->p_iov_info->total_vfs *
440 ECORE_ETH_VF_NUM_VLAN_FILTERS;
441 info->num_vlan_filters = RESC_NUM(&edev->hwfns[0], ECORE_VLAN) -
442 max_vf_vlan_filters;
443
444 rte_memcpy(&info->port_mac, &edev->hwfns[0].hw_info.hw_mac_addr,
445 RTE_ETHER_ADDR_LEN);
446 } else {
447 ecore_vf_get_num_rxqs(ECORE_LEADING_HWFN(edev),
448 &info->num_queues);
449 if (ECORE_IS_CMT(edev)) {
450 ecore_vf_get_num_rxqs(&edev->hwfns[1], &queues);
451 info->num_queues += queues;
452 }
453
454 ecore_vf_get_num_vlan_filters(&edev->hwfns[0],
455 (u8 *)&info->num_vlan_filters);
456
457 ecore_vf_get_port_mac(&edev->hwfns[0],
458 (uint8_t *)&info->port_mac);
459
460 info->is_legacy = ecore_vf_get_pre_fp_hsi(&edev->hwfns[0]);
461 }
462
463 qed_fill_dev_info(edev, &info->common);
464
465 if (IS_VF(edev))
466 memset(&info->common.hw_mac, 0, RTE_ETHER_ADDR_LEN);
467
468 return 0;
469}
470
471static void qed_set_name(struct ecore_dev *edev, char name[NAME_SIZE])
472{
473 int i;
474
475 rte_memcpy(edev->name, name, NAME_SIZE);
476 for_each_hwfn(edev, i) {
477 snprintf(edev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i);
478 }
479}
480
481static uint32_t
482qed_sb_init(struct ecore_dev *edev, struct ecore_sb_info *sb_info,
483 void *sb_virt_addr, dma_addr_t sb_phy_addr, uint16_t sb_id)
484{
485 struct ecore_hwfn *p_hwfn;
486 int hwfn_index;
487 uint16_t rel_sb_id;
488 uint8_t n_hwfns = edev->num_hwfns;
489 uint32_t rc;
490
491 hwfn_index = sb_id % n_hwfns;
492 p_hwfn = &edev->hwfns[hwfn_index];
493 rel_sb_id = sb_id / n_hwfns;
494
495 DP_INFO(edev, "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
496 hwfn_index, rel_sb_id, sb_id);
497
498 rc = ecore_int_sb_init(p_hwfn, p_hwfn->p_main_ptt, sb_info,
499 sb_virt_addr, sb_phy_addr, rel_sb_id);
500
501 return rc;
502}
503
504static void qed_fill_link(struct ecore_hwfn *hwfn,
505 __rte_unused struct ecore_ptt *ptt,
506 struct qed_link_output *if_link)
507{
508 struct ecore_mcp_link_params params;
509 struct ecore_mcp_link_state link;
510 struct ecore_mcp_link_capabilities link_caps;
511 uint8_t change = 0;
512
513 memset(if_link, 0, sizeof(*if_link));
514
515
516 if (IS_PF(hwfn->p_dev)) {
517 rte_memcpy(¶ms, ecore_mcp_get_link_params(hwfn),
518 sizeof(params));
519 rte_memcpy(&link, ecore_mcp_get_link_state(hwfn), sizeof(link));
520 rte_memcpy(&link_caps, ecore_mcp_get_link_capabilities(hwfn),
521 sizeof(link_caps));
522 } else {
523 ecore_vf_read_bulletin(hwfn, &change);
524 ecore_vf_get_link_params(hwfn, ¶ms);
525 ecore_vf_get_link_state(hwfn, &link);
526 ecore_vf_get_link_caps(hwfn, &link_caps);
527 }
528
529
530 if (link.link_up)
531 if_link->link_up = true;
532
533 if (link.link_up)
534 if_link->speed = link.speed;
535
536 if_link->duplex = QEDE_DUPLEX_FULL;
537
538
539 if_link->adv_speed = params.speed.advertised_speeds;
540
541 if (params.speed.autoneg)
542 if_link->supported_caps |= QEDE_SUPPORTED_AUTONEG;
543
544 if (params.pause.autoneg || params.pause.forced_rx ||
545 params.pause.forced_tx)
546 if_link->supported_caps |= QEDE_SUPPORTED_PAUSE;
547
548 if (params.pause.autoneg)
549 if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
550
551 if (params.pause.forced_rx)
552 if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE;
553
554 if (params.pause.forced_tx)
555 if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE;
556
557 if (link_caps.default_eee == ECORE_MCP_EEE_UNSUPPORTED) {
558 if_link->eee_supported = false;
559 } else {
560 if_link->eee_supported = true;
561 if_link->eee_active = link.eee_active;
562 if_link->sup_caps = link_caps.eee_speed_caps;
563
564 if_link->eee.adv_caps = link.eee_adv_caps ? link.eee_adv_caps :
565 params.eee.adv_caps;
566 if_link->eee.lp_adv_caps = link.eee_lp_adv_caps;
567 if_link->eee.enable = params.eee.enable;
568 if_link->eee.tx_lpi_enable = params.eee.tx_lpi_enable;
569 if_link->eee.tx_lpi_timer = params.eee.tx_lpi_timer;
570 }
571}
572
573static void
574qed_get_current_link(struct ecore_dev *edev, struct qed_link_output *if_link)
575{
576 struct ecore_hwfn *hwfn;
577 struct ecore_ptt *ptt;
578
579 hwfn = &edev->hwfns[0];
580 if (IS_PF(edev)) {
581 ptt = ecore_ptt_acquire(hwfn);
582 if (ptt) {
583 qed_fill_link(hwfn, ptt, if_link);
584 ecore_ptt_release(hwfn, ptt);
585 } else {
586 DP_NOTICE(hwfn, true, "Failed to fill link; No PTT\n");
587 }
588 } else {
589 qed_fill_link(hwfn, NULL, if_link);
590 }
591}
592
593static int qed_set_link(struct ecore_dev *edev, struct qed_link_params *params)
594{
595 struct ecore_hwfn *hwfn;
596 struct ecore_ptt *ptt;
597 struct ecore_mcp_link_params *link_params;
598 int rc;
599
600 if (IS_VF(edev))
601 return 0;
602
603
604 hwfn = &edev->hwfns[0];
605
606 ptt = ecore_ptt_acquire(hwfn);
607 if (!ptt)
608 return -EBUSY;
609
610 link_params = ecore_mcp_get_link_params(hwfn);
611 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG)
612 link_params->speed.autoneg = params->autoneg;
613
614 if (params->override_flags & QED_LINK_OVERRIDE_PAUSE_CONFIG) {
615 if (params->pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
616 link_params->pause.autoneg = true;
617 else
618 link_params->pause.autoneg = false;
619 if (params->pause_config & QED_LINK_PAUSE_RX_ENABLE)
620 link_params->pause.forced_rx = true;
621 else
622 link_params->pause.forced_rx = false;
623 if (params->pause_config & QED_LINK_PAUSE_TX_ENABLE)
624 link_params->pause.forced_tx = true;
625 else
626 link_params->pause.forced_tx = false;
627 }
628
629 if (params->override_flags & QED_LINK_OVERRIDE_EEE_CONFIG)
630 memcpy(&link_params->eee, ¶ms->eee,
631 sizeof(link_params->eee));
632
633 rc = ecore_mcp_set_link(hwfn, ptt, params->link_up);
634
635 ecore_ptt_release(hwfn, ptt);
636
637 return rc;
638}
639
640void qed_link_update(struct ecore_hwfn *hwfn)
641{
642 struct ecore_dev *edev = hwfn->p_dev;
643 struct qede_dev *qdev = (struct qede_dev *)edev;
644 struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
645 int rc;
646
647 rc = qede_link_update(dev, 0);
648 qed_inform_vf_link_state(hwfn);
649
650 if (!rc)
651 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
652}
653
654static int qed_drain(struct ecore_dev *edev)
655{
656 struct ecore_hwfn *hwfn;
657 struct ecore_ptt *ptt;
658 int i, rc;
659
660 if (IS_VF(edev))
661 return 0;
662
663 for_each_hwfn(edev, i) {
664 hwfn = &edev->hwfns[i];
665 ptt = ecore_ptt_acquire(hwfn);
666 if (!ptt) {
667 DP_ERR(hwfn, "Failed to drain NIG; No PTT\n");
668 return -EBUSY;
669 }
670 rc = ecore_mcp_drain(hwfn, ptt);
671 if (rc)
672 return rc;
673 ecore_ptt_release(hwfn, ptt);
674 }
675
676 return 0;
677}
678
679static int qed_nic_stop(struct ecore_dev *edev)
680{
681 int i, rc;
682
683 rc = ecore_hw_stop(edev);
684 for (i = 0; i < edev->num_hwfns; i++) {
685 struct ecore_hwfn *p_hwfn = &edev->hwfns[i];
686
687 if (p_hwfn->b_sp_dpc_enabled)
688 p_hwfn->b_sp_dpc_enabled = false;
689 }
690 return rc;
691}
692
693static int qed_slowpath_stop(struct ecore_dev *edev)
694{
695#ifdef CONFIG_QED_SRIOV
696 int i;
697#endif
698
699 if (!edev)
700 return -ENODEV;
701
702 if (IS_PF(edev)) {
703#ifdef CONFIG_ECORE_ZIPPED_FW
704 qed_free_stream_mem(edev);
705#endif
706
707#ifdef CONFIG_QED_SRIOV
708 if (IS_QED_ETH_IF(edev))
709 qed_sriov_disable(edev, true);
710#endif
711 }
712
713 qed_nic_stop(edev);
714
715 ecore_resc_free(edev);
716 qed_stop_iov_task(edev);
717
718 return 0;
719}
720
721static void qed_remove(struct ecore_dev *edev)
722{
723 if (!edev)
724 return;
725
726 ecore_hw_remove(edev);
727}
728
729static int qed_send_drv_state(struct ecore_dev *edev, bool active)
730{
731 struct ecore_hwfn *hwfn = ECORE_LEADING_HWFN(edev);
732 struct ecore_ptt *ptt;
733 int status = 0;
734
735 ptt = ecore_ptt_acquire(hwfn);
736 if (!ptt)
737 return -EAGAIN;
738
739 status = ecore_mcp_ov_update_driver_state(hwfn, ptt, active ?
740 ECORE_OV_DRIVER_STATE_ACTIVE :
741 ECORE_OV_DRIVER_STATE_DISABLED);
742
743 ecore_ptt_release(hwfn, ptt);
744
745 return status;
746}
747
748static int qed_get_sb_info(struct ecore_dev *edev, struct ecore_sb_info *sb,
749 u16 qid, struct ecore_sb_info_dbg *sb_dbg)
750{
751 struct ecore_hwfn *hwfn = &edev->hwfns[qid % edev->num_hwfns];
752 struct ecore_ptt *ptt;
753 int rc;
754
755 if (IS_VF(edev))
756 return -EINVAL;
757
758 ptt = ecore_ptt_acquire(hwfn);
759 if (!ptt) {
760 DP_ERR(hwfn, "Can't acquire PTT\n");
761 return -EAGAIN;
762 }
763
764 memset(sb_dbg, 0, sizeof(*sb_dbg));
765 rc = ecore_int_get_sb_dbg(hwfn, ptt, sb, sb_dbg);
766
767 ecore_ptt_release(hwfn, ptt);
768 return rc;
769}
770
771const struct qed_common_ops qed_common_ops_pass = {
772 INIT_STRUCT_FIELD(probe, &qed_probe),
773 INIT_STRUCT_FIELD(update_pf_params, &qed_update_pf_params),
774 INIT_STRUCT_FIELD(slowpath_start, &qed_slowpath_start),
775 INIT_STRUCT_FIELD(set_name, &qed_set_name),
776 INIT_STRUCT_FIELD(chain_alloc, &ecore_chain_alloc),
777 INIT_STRUCT_FIELD(chain_free, &ecore_chain_free),
778 INIT_STRUCT_FIELD(sb_init, &qed_sb_init),
779 INIT_STRUCT_FIELD(get_sb_info, &qed_get_sb_info),
780 INIT_STRUCT_FIELD(get_link, &qed_get_current_link),
781 INIT_STRUCT_FIELD(set_link, &qed_set_link),
782 INIT_STRUCT_FIELD(drain, &qed_drain),
783 INIT_STRUCT_FIELD(slowpath_stop, &qed_slowpath_stop),
784 INIT_STRUCT_FIELD(remove, &qed_remove),
785 INIT_STRUCT_FIELD(send_drv_state, &qed_send_drv_state),
786
787
788 INIT_STRUCT_FIELD(dbg_get_debug_engine, &qed_get_debug_engine),
789 INIT_STRUCT_FIELD(dbg_set_debug_engine, &qed_set_debug_engine),
790
791 INIT_STRUCT_FIELD(dbg_protection_override,
792 &qed_dbg_protection_override),
793 INIT_STRUCT_FIELD(dbg_protection_override_size,
794 &qed_dbg_protection_override_size),
795
796 INIT_STRUCT_FIELD(dbg_grc, &qed_dbg_grc),
797 INIT_STRUCT_FIELD(dbg_grc_size, &qed_dbg_grc_size),
798
799 INIT_STRUCT_FIELD(dbg_idle_chk, &qed_dbg_idle_chk),
800 INIT_STRUCT_FIELD(dbg_idle_chk_size, &qed_dbg_idle_chk_size),
801
802 INIT_STRUCT_FIELD(dbg_mcp_trace, &qed_dbg_mcp_trace),
803 INIT_STRUCT_FIELD(dbg_mcp_trace_size, &qed_dbg_mcp_trace_size),
804
805 INIT_STRUCT_FIELD(dbg_fw_asserts, &qed_dbg_fw_asserts),
806 INIT_STRUCT_FIELD(dbg_fw_asserts_size, &qed_dbg_fw_asserts_size),
807
808 INIT_STRUCT_FIELD(dbg_ilt, &qed_dbg_ilt),
809 INIT_STRUCT_FIELD(dbg_ilt_size, &qed_dbg_ilt_size),
810
811 INIT_STRUCT_FIELD(dbg_reg_fifo_size, &qed_dbg_reg_fifo_size),
812 INIT_STRUCT_FIELD(dbg_reg_fifo, &qed_dbg_reg_fifo),
813
814 INIT_STRUCT_FIELD(dbg_igu_fifo_size, &qed_dbg_igu_fifo_size),
815 INIT_STRUCT_FIELD(dbg_igu_fifo, &qed_dbg_igu_fifo),
816};
817
818const struct qed_eth_ops qed_eth_ops_pass = {
819 INIT_STRUCT_FIELD(common, &qed_common_ops_pass),
820 INIT_STRUCT_FIELD(fill_dev_info, &qed_fill_eth_dev_info),
821 INIT_STRUCT_FIELD(sriov_configure, &qed_sriov_configure),
822};
823
824const struct qed_eth_ops *qed_get_eth_ops(void)
825{
826 return &qed_eth_ops_pass;
827}
828
