LXR dpdk/drivers/net/txgbe/txgbe

   1/* SPDX-License-Identifier: BSD-3-Clause
   2 * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd.
   3 * Copyright(c) 2010-2017 Intel Corporation
   4 */
   5
   6#ifndef _TXGBE_RXTX_H_
   7#define _TXGBE_RXTX_H_
   8
   9/*****************************************************************************
  10 * Receive Descriptor
  11 *****************************************************************************/
  12struct txgbe_rx_desc {
  13        struct {
  14                union {
  15                        __le32 dw0;
  16                        struct {
  17                                __le16 pkt;
  18                                __le16 hdr;
  19                        } lo;
  20                };
  21                union {
  22                        __le32 dw1;
  23                        struct {
  24                                __le16 ipid;
  25                                __le16 csum;
  26                        } hi;
  27                };
  28        } qw0; /* also as r.pkt_addr */
  29        struct {
  30                union {
  31                        __le32 dw2;
  32                        struct {
  33                                __le32 status;
  34                        } lo;
  35                };
  36                union {
  37                        __le32 dw3;
  38                        struct {
  39                                __le16 len;
  40                                __le16 tag;
  41                        } hi;
  42                };
  43        } qw1; /* also as r.hdr_addr */
  44};
  45
  46/* @txgbe_rx_desc.qw0 */
  47#define TXGBE_RXD_PKTADDR(rxd, v)  \
  48        (((volatile __le64 *)(rxd))[0] = cpu_to_le64(v))
  49
  50/* @txgbe_rx_desc.qw1 */
  51#define TXGBE_RXD_HDRADDR(rxd, v)  \
  52        (((volatile __le64 *)(rxd))[1] = cpu_to_le64(v))
  53
  54/* @txgbe_rx_desc.dw0 */
  55#define TXGBE_RXD_RSSTYPE(dw)      RS(dw, 0, 0xF)
  56#define   TXGBE_RSSTYPE_NONE       0
  57#define   TXGBE_RSSTYPE_IPV4TCP    1
  58#define   TXGBE_RSSTYPE_IPV4       2
  59#define   TXGBE_RSSTYPE_IPV6TCP    3
  60#define   TXGBE_RSSTYPE_IPV4SCTP   4
  61#define   TXGBE_RSSTYPE_IPV6       5
  62#define   TXGBE_RSSTYPE_IPV6SCTP   6
  63#define   TXGBE_RSSTYPE_IPV4UDP    7
  64#define   TXGBE_RSSTYPE_IPV6UDP    8
  65#define   TXGBE_RSSTYPE_FDIR       15
  66#define TXGBE_RXD_SECTYPE(dw)      RS(dw, 4, 0x3)
  67#define TXGBE_RXD_SECTYPE_NONE     LS(0, 4, 0x3)
  68#define TXGBE_RXD_SECTYPE_LINKSEC  LS(1, 4, 0x3)
  69#define TXGBE_RXD_SECTYPE_IPSECESP LS(2, 4, 0x3)
  70#define TXGBE_RXD_SECTYPE_IPSECAH  LS(3, 4, 0x3)
  71#define TXGBE_RXD_TPIDSEL(dw)      RS(dw, 6, 0x7)
  72#define TXGBE_RXD_PTID(dw)         RS(dw, 9, 0xFF)
  73#define TXGBE_RXD_RSCCNT(dw)       RS(dw, 17, 0xF)
  74#define TXGBE_RXD_HDRLEN(dw)       RS(dw, 21, 0x3FF)
  75#define TXGBE_RXD_SPH              MS(31, 0x1)
  76
  77/* @txgbe_rx_desc.dw1 */
  78/** bit 0-31, as rss hash when  **/
  79#define TXGBE_RXD_RSSHASH(rxd)     ((rxd)->qw0.dw1)
  80
  81/** bit 0-31, as ip csum when  **/
  82#define TXGBE_RXD_IPID(rxd)        ((rxd)->qw0.hi.ipid)
  83#define TXGBE_RXD_CSUM(rxd)        ((rxd)->qw0.hi.csum)
  84
  85/** bit 0-31, as fdir id when  **/
  86#define TXGBE_RXD_FDIRID(rxd)      ((rxd)->qw0.hi.dw1)
  87
  88/* @txgbe_rx_desc.dw2 */
  89#define TXGBE_RXD_STATUS(rxd)      ((rxd)->qw1.lo.status)
  90/** bit 0-1 **/
  91#define TXGBE_RXD_STAT_DD          MS(0, 0x1) /* Descriptor Done */
  92#define TXGBE_RXD_STAT_EOP         MS(1, 0x1) /* End of Packet */
  93/** bit 2-31, when EOP=0 **/
  94#define TXGBE_RXD_NEXTP_RESV(v)    LS(v, 2, 0x3)
  95#define TXGBE_RXD_NEXTP(dw)        RS(dw, 4, 0xFFFF) /* Next Descriptor */
  96/** bit 2-31, when EOP=1 **/
  97#define TXGBE_RXD_PKT_CLS_MASK     MS(2, 0x7) /* Packet Class */
  98#define TXGBE_RXD_PKT_CLS_TC_RSS   LS(0, 2, 0x7) /* RSS Hash */
  99#define TXGBE_RXD_PKT_CLS_FLM      LS(1, 2, 0x7) /* FDir Match */
 100#define TXGBE_RXD_PKT_CLS_SYN      LS(2, 2, 0x7) /* TCP Sync */
 101#define TXGBE_RXD_PKT_CLS_5TUPLE   LS(3, 2, 0x7) /* 5 Tuple */
 102#define TXGBE_RXD_PKT_CLS_ETF      LS(4, 2, 0x7) /* Ethertype Filter */
 103#define TXGBE_RXD_STAT_VLAN        MS(5, 0x1) /* IEEE VLAN Packet */
 104#define TXGBE_RXD_STAT_UDPCS       MS(6, 0x1) /* UDP xsum calculated */
 105#define TXGBE_RXD_STAT_L4CS        MS(7, 0x1) /* L4 xsum calculated */
 106#define TXGBE_RXD_STAT_IPCS        MS(8, 0x1) /* IP xsum calculated */
 107#define TXGBE_RXD_STAT_PIF         MS(9, 0x1) /* Non-unicast address */
 108#define TXGBE_RXD_STAT_EIPCS       MS(10, 0x1) /* Encap IP xsum calculated */
 109#define TXGBE_RXD_STAT_VEXT        MS(11, 0x1) /* Multi-VLAN */
 110#define TXGBE_RXD_STAT_IPV6EX      MS(12, 0x1) /* IPv6 with option header */
 111#define TXGBE_RXD_STAT_LLINT       MS(13, 0x1) /* Pkt caused LLI */
 112#define TXGBE_RXD_STAT_1588        MS(14, 0x1) /* IEEE1588 Time Stamp */
 113#define TXGBE_RXD_STAT_SECP        MS(15, 0x1) /* Security Processing */
 114#define TXGBE_RXD_STAT_LB          MS(16, 0x1) /* Loopback Status */
 115/*** bit 17-30, when PTYPE=IP ***/
 116#define TXGBE_RXD_STAT_BMC         MS(17, 0x1) /* PTYPE=IP, BMC status */
 117#define TXGBE_RXD_ERR_FDIR_LEN     MS(20, 0x1) /* FDIR Length error */
 118#define TXGBE_RXD_ERR_FDIR_DROP    MS(21, 0x1) /* FDIR Drop error */
 119#define TXGBE_RXD_ERR_FDIR_COLL    MS(22, 0x1) /* FDIR Collision error */
 120#define TXGBE_RXD_ERR_HBO          MS(23, 0x1) /* Header Buffer Overflow */
 121#define TXGBE_RXD_ERR_EIPCS        MS(26, 0x1) /* Encap IP header error */
 122#define TXGBE_RXD_ERR_SECERR       MS(27, 0x1) /* macsec or ipsec error */
 123#define TXGBE_RXD_ERR_RXE          MS(29, 0x1) /* Any MAC Error */
 124#define TXGBE_RXD_ERR_L4CS         MS(30, 0x1) /* TCP/UDP xsum error */
 125#define TXGBE_RXD_ERR_IPCS         MS(31, 0x1) /* IP xsum error */
 126#define TXGBE_RXD_ERR_CSUM(dw)     RS(dw, 30, 0x3)
 127/*** bit 17-30, when PTYPE=FCOE ***/
 128#define TXGBE_RXD_STAT_FCOEFS      MS(17, 0x1) /* PTYPE=FCOE, FCoE EOF/SOF */
 129#define TXGBE_RXD_FCSTAT_MASK      MS(18, 0x3) /* FCoE Pkt Stat */
 130#define TXGBE_RXD_FCSTAT_NOMTCH    LS(0, 18, 0x3) /* No Ctxt Match */
 131#define TXGBE_RXD_FCSTAT_NODDP     LS(1, 18, 0x3) /* Ctxt w/o DDP */
 132#define TXGBE_RXD_FCSTAT_FCPRSP    LS(2, 18, 0x3) /* Recv. FCP_RSP */
 133#define TXGBE_RXD_FCSTAT_DDP       LS(3, 18, 0x3) /* Ctxt w/ DDP */
 134#define TXGBE_RXD_FCERR_MASK       MS(20, 0x7) /* FCERR */
 135#define TXGBE_RXD_FCERR_0          LS(0, 20, 0x7)
 136#define TXGBE_RXD_FCERR_1          LS(1, 20, 0x7)
 137#define TXGBE_RXD_FCERR_2          LS(2, 20, 0x7)
 138#define TXGBE_RXD_FCERR_3          LS(3, 20, 0x7)
 139#define TXGBE_RXD_FCERR_4          LS(4, 20, 0x7)
 140#define TXGBE_RXD_FCERR_5          LS(5, 20, 0x7)
 141#define TXGBE_RXD_FCERR_6          LS(6, 20, 0x7)
 142#define TXGBE_RXD_FCERR_7          LS(7, 20, 0x7)
 143
 144/* @txgbe_rx_desc.dw3 */
 145#define TXGBE_RXD_LENGTH(rxd)           ((rxd)->qw1.hi.len)
 146#define TXGBE_RXD_VLAN(rxd)             ((rxd)->qw1.hi.tag)
 147
 148/*****************************************************************************
 149 * Transmit Descriptor
 150 *****************************************************************************/
 151/**
 152 * Transmit Context Descriptor (TXGBE_TXD_TYP=CTXT)
 153 **/
 154struct txgbe_tx_ctx_desc {
 155        __le32 dw0; /* w.vlan_macip_lens  */
 156        __le32 dw1; /* w.seqnum_seed      */
 157        __le32 dw2; /* w.type_tucmd_mlhl  */
 158        __le32 dw3; /* w.mss_l4len_idx    */
 159};
 160
 161/* @txgbe_tx_ctx_desc.dw0 */
 162#define TXGBE_TXD_IPLEN(v)         LS(v, 0, 0x1FF) /* ip/fcoe header end */
 163#define TXGBE_TXD_MACLEN(v)        LS(v, 9, 0x7F) /* desc mac len */
 164#define TXGBE_TXD_VLAN(v)          LS(v, 16, 0xFFFF) /* vlan tag */
 165
 166/* @txgbe_tx_ctx_desc.dw1 */
 167/*** bit 0-31, when TXGBE_TXD_DTYP_FCOE=0 ***/
 168#define TXGBE_TXD_IPSEC_SAIDX(v)   LS(v, 0, 0x3FF) /* ipsec SA index */
 169#define TXGBE_TXD_ETYPE(v)         LS(v, 11, 0x1) /* tunnel type */
 170#define TXGBE_TXD_ETYPE_UDP        LS(0, 11, 0x1)
 171#define TXGBE_TXD_ETYPE_GRE        LS(1, 11, 0x1)
 172#define TXGBE_TXD_EIPLEN(v)        LS(v, 12, 0x7F) /* tunnel ip header */
 173#define TXGBE_TXD_DTYP_FCOE        MS(16, 0x1) /* FCoE/IP descriptor */
 174#define TXGBE_TXD_ETUNLEN(v)       LS(v, 21, 0xFF) /* tunnel header */
 175#define TXGBE_TXD_DECTTL(v)        LS(v, 29, 0xF) /* decrease ip TTL */
 176/*** bit 0-31, when TXGBE_TXD_DTYP_FCOE=1 ***/
 177#define TXGBE_TXD_FCOEF_EOF_MASK   MS(10, 0x3) /* FC EOF index */
 178#define TXGBE_TXD_FCOEF_EOF_N      LS(0, 10, 0x3) /* EOFn */
 179#define TXGBE_TXD_FCOEF_EOF_T      LS(1, 10, 0x3) /* EOFt */
 180#define TXGBE_TXD_FCOEF_EOF_NI     LS(2, 10, 0x3) /* EOFni */
 181#define TXGBE_TXD_FCOEF_EOF_A      LS(3, 10, 0x3) /* EOFa */
 182#define TXGBE_TXD_FCOEF_SOF        MS(12, 0x1) /* FC SOF index */
 183#define TXGBE_TXD_FCOEF_PARINC     MS(13, 0x1) /* Rel_Off in F_CTL */
 184#define TXGBE_TXD_FCOEF_ORIE       MS(14, 0x1) /* orientation end */
 185#define TXGBE_TXD_FCOEF_ORIS       MS(15, 0x1) /* orientation start */
 186
 187/* @txgbe_tx_ctx_desc.dw2 */
 188#define TXGBE_TXD_IPSEC_ESPLEN(v)  LS(v, 1, 0x1FF) /* ipsec ESP length */
 189#define TXGBE_TXD_SNAP             MS(10, 0x1) /* SNAP indication */
 190#define TXGBE_TXD_TPID_SEL(v)      LS(v, 11, 0x7) /* vlan tag index */
 191#define TXGBE_TXD_IPSEC_ESP        MS(14, 0x1) /* ipsec type: esp=1 ah=0 */
 192#define TXGBE_TXD_IPSEC_ESPENC     MS(15, 0x1) /* ESP encrypt */
 193#define TXGBE_TXD_CTXT             MS(20, 0x1) /* context descriptor */
 194#define TXGBE_TXD_PTID(v)          LS(v, 24, 0xFF) /* packet type */
 195/* @txgbe_tx_ctx_desc.dw3 */
 196#define TXGBE_TXD_DD               MS(0, 0x1) /* descriptor done */
 197#define TXGBE_TXD_IDX(v)           LS(v, 4, 0x1) /* ctxt desc index */
 198#define TXGBE_TXD_L4LEN(v)         LS(v, 8, 0xFF) /* l4 header length */
 199#define TXGBE_TXD_MSS(v)           LS(v, 16, 0xFFFF) /* l4 MSS */
 200
 201/**
 202 * Transmit Data Descriptor (TXGBE_TXD_TYP=DATA)
 203 **/
 204struct txgbe_tx_desc {
 205        __le64 qw0; /* r.buffer_addr ,  w.reserved    */
 206        __le32 dw2; /* r.cmd_type_len,  w.nxtseq_seed */
 207        __le32 dw3; /* r.olinfo_status, w.status      */
 208};
 209/* @txgbe_tx_desc.qw0 */
 210
 211/* @txgbe_tx_desc.dw2 */
 212#define TXGBE_TXD_DATLEN(v)        ((0xFFFF & (v))) /* data buffer length */
 213#define TXGBE_TXD_1588             ((0x1) << 19) /* IEEE1588 time stamp */
 214#define TXGBE_TXD_DATA             ((0x0) << 20) /* data descriptor */
 215#define TXGBE_TXD_EOP              ((0x1) << 24) /* End of Packet */
 216#define TXGBE_TXD_FCS              ((0x1) << 25) /* Insert FCS */
 217#define TXGBE_TXD_LINKSEC          ((0x1) << 26) /* Insert LinkSec */
 218#define TXGBE_TXD_ECU              ((0x1) << 28) /* forward to ECU */
 219#define TXGBE_TXD_CNTAG            ((0x1) << 29) /* insert CN tag */
 220#define TXGBE_TXD_VLE              ((0x1) << 30) /* insert VLAN tag */
 221#define TXGBE_TXD_TSE              ((0x1) << 31) /* transmit segmentation */
 222
 223#define TXGBE_TXD_FLAGS (TXGBE_TXD_FCS | TXGBE_TXD_EOP)
 224
 225/* @txgbe_tx_desc.dw3 */
 226#define TXGBE_TXD_DD_UNUSED        TXGBE_TXD_DD
 227#define TXGBE_TXD_IDX_UNUSED(v)    TXGBE_TXD_IDX(v)
 228#define TXGBE_TXD_CC               ((0x1) << 7) /* check context */
 229#define TXGBE_TXD_IPSEC            ((0x1) << 8) /* request ipsec offload */
 230#define TXGBE_TXD_L4CS             ((0x1) << 9) /* insert TCP/UDP/SCTP csum */
 231#define TXGBE_TXD_IPCS             ((0x1) << 10) /* insert IPv4 csum */
 232#define TXGBE_TXD_EIPCS            ((0x1) << 11) /* insert outer IP csum */
 233#define TXGBE_TXD_MNGFLT           ((0x1) << 12) /* enable management filter */
 234#define TXGBE_TXD_PAYLEN(v)        ((0x7FFFF & (v)) << 13) /* payload length */
 235
 236#define RTE_PMD_TXGBE_TX_MAX_BURST 32
 237#define RTE_PMD_TXGBE_RX_MAX_BURST 32
 238#define RTE_TXGBE_TX_MAX_FREE_BUF_SZ 64
 239
 240#define RX_RING_SZ ((TXGBE_RING_DESC_MAX + RTE_PMD_TXGBE_RX_MAX_BURST) * \
 241                    sizeof(struct txgbe_rx_desc))
 242
 243#define rte_packet_prefetch(p)  rte_prefetch1(p)
 244
 245#define RTE_TXGBE_REGISTER_POLL_WAIT_10_MS  10
 246#define RTE_TXGBE_WAIT_100_US               100
 247
 248#define TXGBE_TX_MAX_SEG                    40
 249
 250/**
 251 * Structure associated with each descriptor of the RX ring of a RX queue.
 252 */
 253struct txgbe_rx_entry {
 254        struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
 255};
 256
 257struct txgbe_scattered_rx_entry {
 258        struct rte_mbuf *fbuf; /**< First segment of the fragmented packet. */
 259};
 260
 261/**
 262 * Structure associated with each descriptor of the TX ring of a TX queue.
 263 */
 264struct txgbe_tx_entry {
 265        struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
 266        uint16_t next_id; /**< Index of next descriptor in ring. */
 267        uint16_t last_id; /**< Index of last scattered descriptor. */
 268};
 269
 270/**
 271 * Structure associated with each descriptor of the TX ring of a TX queue.
 272 */
 273struct txgbe_tx_entry_v {
 274        struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
 275};
 276
 277/**
 278 * Structure associated with each RX queue.
 279 */
 280struct txgbe_rx_queue {
 281        struct rte_mempool  *mb_pool; /**< mbuf pool to populate RX ring. */
 282        volatile struct txgbe_rx_desc *rx_ring; /**< RX ring virtual address. */
 283        uint64_t            rx_ring_phys_addr; /**< RX ring DMA address. */
 284        volatile uint32_t   *rdt_reg_addr; /**< RDT register address. */
 285        volatile uint32_t   *rdh_reg_addr; /**< RDH register address. */
 286        struct txgbe_rx_entry *sw_ring; /**< address of RX software ring. */
 287        /**< address of scattered Rx software ring. */
 288        struct txgbe_scattered_rx_entry *sw_sc_ring;
 289        struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
 290        struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
 291        uint16_t            nb_rx_desc; /**< number of RX descriptors. */
 292        uint16_t            rx_tail;  /**< current value of RDT register. */
 293        uint16_t            nb_rx_hold; /**< number of held free RX desc. */
 294        uint16_t rx_nb_avail; /**< nr of staged pkts ready to ret to app */
 295        uint16_t rx_next_avail; /**< idx of next staged pkt to ret to app */
 296        uint16_t rx_free_trigger; /**< triggers rx buffer allocation */
 297#ifdef RTE_LIB_SECURITY
 298        uint8_t            using_ipsec;
 299        /**< indicates that IPsec RX feature is in use */
 300#endif
 301        uint16_t            rx_free_thresh; /**< max free RX desc to hold. */
 302        uint16_t            queue_id; /**< RX queue index. */
 303        uint16_t            reg_idx;  /**< RX queue register index. */
 304        /**< Packet type mask for different NICs. */
 305        uint16_t            pkt_type_mask;
 306        uint16_t            port_id;  /**< Device port identifier. */
 307        uint8_t             crc_len;  /**< 0 if CRC stripped, 4 otherwise. */
 308        uint8_t             drop_en;  /**< If not 0, set SRRCTL.Drop_En. */
 309        uint8_t             rx_deferred_start; /**< not in global dev start. */
 310        /** flags to set in mbuf when a vlan is detected. */
 311        uint64_t            vlan_flags;
 312        uint64_t            offloads; /**< Rx offloads with DEV_RX_OFFLOAD_* */
 313        /** need to alloc dummy mbuf, for wraparound when scanning hw ring */
 314        struct rte_mbuf fake_mbuf;
 315        /** hold packets to return to application */
 316        struct rte_mbuf *rx_stage[RTE_PMD_TXGBE_RX_MAX_BURST * 2];
 317};
 318
 319/**
 320 * TXGBE CTX Constants
 321 */
 322enum txgbe_ctx_num {
 323        TXGBE_CTX_0    = 0, /**< CTX0 */
 324        TXGBE_CTX_1    = 1, /**< CTX1  */
 325        TXGBE_CTX_NUM  = 2, /**< CTX NUMBER  */
 326};
 327
 328/** Offload features */
 329union txgbe_tx_offload {
 330        uint64_t data[2];
 331        struct {
 332                uint64_t ptid:8; /**< Packet Type Identifier. */
 333                uint64_t l2_len:7; /**< L2 (MAC) Header Length. */
 334                uint64_t l3_len:9; /**< L3 (IP) Header Length. */
 335                uint64_t l4_len:8; /**< L4 (TCP/UDP) Header Length. */
 336                uint64_t tso_segsz:16; /**< TCP TSO segment size */
 337                uint64_t vlan_tci:16;
 338                /**< VLAN Tag Control Identifier (CPU order). */
 339
 340                /* fields for TX offloading of tunnels */
 341                uint64_t outer_tun_len:8; /**< Outer TUN (Tunnel) Hdr Length. */
 342                uint64_t outer_l2_len:8; /**< Outer L2 (MAC) Hdr Length. */
 343                uint64_t outer_l3_len:16; /**< Outer L3 (IP) Hdr Length. */
 344#ifdef RTE_LIB_SECURITY
 345                /* inline ipsec related*/
 346                uint64_t sa_idx:8;      /**< TX SA database entry index */
 347                uint64_t sec_pad_len:4; /**< padding length */
 348#endif
 349        };
 350};
 351
 352/**
 353 * Structure to check if new context need be built
 354 */
 355struct txgbe_ctx_info {
 356        uint64_t flags;           /**< ol_flags for context build. */
 357        /**< tx offload: vlan, tso, l2-l3-l4 lengths. */
 358        union txgbe_tx_offload tx_offload;
 359        /** compare mask for tx offload. */
 360        union txgbe_tx_offload tx_offload_mask;
 361};
 362
 363/**
 364 * Structure associated with each TX queue.
 365 */
 366struct txgbe_tx_queue {
 367        /** TX ring virtual address. */
 368        volatile struct txgbe_tx_desc *tx_ring;
 369        uint64_t            tx_ring_phys_addr; /**< TX ring DMA address. */
 370        union {
 371                /**< address of SW ring for scalar PMD. */
 372                struct txgbe_tx_entry *sw_ring;
 373                /**< address of SW ring for vector PMD */
 374                struct txgbe_tx_entry_v *sw_ring_v;
 375        };
 376        volatile uint32_t   *tdt_reg_addr; /**< Address of TDT register. */
 377        volatile uint32_t   *tdc_reg_addr; /**< Address of TDC register. */
 378        uint16_t            nb_tx_desc;    /**< number of TX descriptors. */
 379        uint16_t            tx_tail;       /**< current value of TDT reg. */
 380        /**< Start freeing TX buffers if there are less free descriptors than
 381         *   this value.
 382         */
 383        uint16_t            tx_free_thresh;
 384        /** Index to last TX descriptor to have been cleaned. */
 385        uint16_t            last_desc_cleaned;
 386        /** Total number of TX descriptors ready to be allocated. */
 387        uint16_t            nb_tx_free;
 388        uint16_t            tx_next_dd;    /**< next desc to scan for DD bit */
 389        uint16_t            queue_id;      /**< TX queue index. */
 390        uint16_t            reg_idx;       /**< TX queue register index. */
 391        uint16_t            port_id;       /**< Device port identifier. */
 392        uint8_t             pthresh;       /**< Prefetch threshold register. */
 393        uint8_t             hthresh;       /**< Host threshold register. */
 394        uint8_t             wthresh;       /**< Write-back threshold reg. */
 395        uint64_t            offloads; /* Tx offload flags of DEV_TX_OFFLOAD_* */
 396        uint32_t            ctx_curr;      /**< Hardware context states. */
 397        /** Hardware context0 history. */
 398        struct txgbe_ctx_info ctx_cache[TXGBE_CTX_NUM];
 399        const struct txgbe_txq_ops *ops;       /**< txq ops */
 400        uint8_t             tx_deferred_start; /**< not in global dev start. */
 401#ifdef RTE_LIB_SECURITY
 402        uint8_t             using_ipsec;
 403        /**< indicates that IPsec TX feature is in use */
 404#endif
 405};
 406
 407struct txgbe_txq_ops {
 408        void (*release_mbufs)(struct txgbe_tx_queue *txq);
 409        void (*free_swring)(struct txgbe_tx_queue *txq);
 410        void (*reset)(struct txgbe_tx_queue *txq);
 411};
 412
 413/* Takes an ethdev and a queue and sets up the tx function to be used based on
 414 * the queue parameters. Used in tx_queue_setup by primary process and then
 415 * in dev_init by secondary process when attaching to an existing ethdev.
 416 */
 417void txgbe_set_tx_function(struct rte_eth_dev *dev, struct txgbe_tx_queue *txq);
 418
 419void txgbe_set_rx_function(struct rte_eth_dev *dev);
 420int txgbe_dev_tx_done_cleanup(void *tx_queue, uint32_t free_cnt);
 421
 422uint64_t txgbe_get_tx_port_offloads(struct rte_eth_dev *dev);
 423uint64_t txgbe_get_rx_queue_offloads(struct rte_eth_dev *dev);
 424uint64_t txgbe_get_rx_port_offloads(struct rte_eth_dev *dev);
 425uint64_t txgbe_get_tx_queue_offloads(struct rte_eth_dev *dev);
 426
 427#endif /* _TXGBE_RXTX_H_ */
 428