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5#ifndef _OPAE_SPI_H
6#define _OPAE_SPI_H
7
8#include "opae_osdep.h"
9
10#define ALTERA_SPI_RXDATA 0
11#define ALTERA_SPI_TXDATA 4
12#define ALTERA_SPI_STATUS 8
13#define ALTERA_SPI_CONTROL 12
14#define ALTERA_SPI_SLAVE_SEL 20
15
16#define ALTERA_SPI_STATUS_ROE_MSK 0x8
17#define ALTERA_SPI_STATUS_TOE_MSK 0x10
18#define ALTERA_SPI_STATUS_TMT_MSK 0x20
19#define ALTERA_SPI_STATUS_TRDY_MSK 0x40
20#define ALTERA_SPI_STATUS_RRDY_MSK 0x80
21#define ALTERA_SPI_STATUS_E_MSK 0x100
22
23#define ALTERA_SPI_CONTROL_IROE_MSK 0x8
24#define ALTERA_SPI_CONTROL_ITOE_MSK 0x10
25#define ALTERA_SPI_CONTROL_ITRDY_MSK 0x40
26#define ALTERA_SPI_CONTROL_IRRDY_MSK 0x80
27#define ALTERA_SPI_CONTROL_IE_MSK 0x100
28#define ALTERA_SPI_CONTROL_SSO_MSK 0x400
29
30#define SPI_CORE_PARAM 0x8
31#define SPI_CTRL 0x10
32#define CTRL_R BIT_ULL(9)
33#define CTRL_W BIT_ULL(8)
34#define CTRL_ADDR_MASK GENMASK_ULL(2, 0)
35#define SPI_READ 0x18
36#define READ_DATA_VALID BIT_ULL(32)
37#define READ_DATA_MASK GENMASK_ULL(31, 0)
38#define SPI_WRITE 0x20
39#define WRITE_DATA_MASK GENMASK_ULL(31, 0)
40
41#define SPI_MAX_RETRY 1000000
42
43#define TYPE_SPI 0
44#define TYPE_NIOS_SPI 1
45
46struct spi_core_param {
47 union {
48 u64 info;
49 struct {
50 u8 type:1;
51 u8 endian:1;
52 u8 data_width:6;
53 u8 num_chipselect:6;
54 u8 clock_polarity:1;
55 u8 clock_phase:1;
56 u8 stages:2;
57 u8 resvd:4;
58 u16 clock:10;
59 u16 peripheral_id:16;
60 u8 controller_type:1;
61 u16 resvd1:15;
62 };
63 };
64};
65
66struct altera_spi_device {
67 u8 *regs;
68 struct spi_core_param spi_param;
69 int data_width;
70 int endian;
71 #define SPI_BIG_ENDIAN 0
72 #define SPI_LITTLE_ENDIAN 1
73 int num_chipselect;
74 unsigned char *rxbuf;
75 unsigned char *txbuf;
76 unsigned int len;
77 int (*reg_read)(struct altera_spi_device *dev, u32 reg, u32 *val);
78 int (*reg_write)(struct altera_spi_device *dev, u32 reg,
79 u32 value);
80
81 pthread_mutex_t *mutex;
82 unsigned int *dtb_sz_ptr;
83 unsigned char *dtb;
84};
85
86#define HEADER_LEN 8
87#define RESPONSE_LEN 4
88#define SPI_TRANSACTION_MAX_LEN 1024
89#define TRAN_SEND_MAX_LEN (SPI_TRANSACTION_MAX_LEN + HEADER_LEN)
90#define TRAN_RESP_MAX_LEN SPI_TRANSACTION_MAX_LEN
91#define PACKET_SEND_MAX_LEN (2*TRAN_SEND_MAX_LEN + 4)
92#define PACKET_RESP_MAX_LEN (2*TRAN_RESP_MAX_LEN + 4)
93#define BYTES_SEND_MAX_LEN (2*PACKET_SEND_MAX_LEN)
94#define BYTES_RESP_MAX_LEN (2*PACKET_RESP_MAX_LEN)
95
96struct spi_tran_buffer {
97 unsigned char tran_send[TRAN_SEND_MAX_LEN];
98 unsigned char tran_resp[TRAN_RESP_MAX_LEN];
99 unsigned char packet_send[PACKET_SEND_MAX_LEN];
100 unsigned char packet_resp[PACKET_RESP_MAX_LEN];
101 unsigned char bytes_send[BYTES_SEND_MAX_LEN];
102 unsigned char bytes_resp[2*BYTES_RESP_MAX_LEN];
103};
104
105struct spi_transaction_dev {
106 struct altera_spi_device *dev;
107 int chipselect;
108 struct spi_tran_buffer *buffer;
109 pthread_mutex_t lock;
110 pthread_mutex_t *mutex;
111};
112
113struct spi_tran_header {
114 u8 trans_type;
115 u8 reserve;
116 u16 size;
117 u32 addr;
118};
119
120int spi_command(struct altera_spi_device *dev, unsigned int chip_select,
121 unsigned int wlen, void *wdata, unsigned int rlen, void *rdata);
122void spi_cs_deactivate(struct altera_spi_device *dev);
123void spi_cs_activate(struct altera_spi_device *dev, unsigned int chip_select);
124struct altera_spi_device *altera_spi_alloc(void *base, int type);
125void altera_spi_init(struct altera_spi_device *dev);
126void altera_spi_release(struct altera_spi_device *dev);
127int spi_transaction_read(struct spi_transaction_dev *dev, unsigned int addr,
128 unsigned int size, unsigned char *data);
129int spi_transaction_write(struct spi_transaction_dev *dev, unsigned int addr,
130 unsigned int size, unsigned char *data);
131struct spi_transaction_dev *spi_transaction_init(struct altera_spi_device *dev,
132 int chipselect);
133void spi_transaction_remove(struct spi_transaction_dev *dev);
134int spi_reg_write(struct altera_spi_device *dev, u32 reg,
135 u32 value);
136int spi_reg_read(struct altera_spi_device *dev, u32 reg, u32 *val);
137
138#define NIOS_SPI_PARAM 0x8
139#define CONTROL_TYPE BIT_ULL(48)
140#define PERI_ID GENMASK_ULL(47, 32)
141#define SPI_CLK GENMASK_ULL(31, 22)
142#define SYNC_STAGES GENMASK_ULL(17, 16)
143#define CLOCK_PHASE BIT_ULL(15)
144#define CLOCK_POLARITY BIT_ULL(14)
145#define NUM_SELECT GENMASK_ULL(13, 8)
146#define DATA_WIDTH GENMASK_ULL(7, 2)
147#define SHIFT_DIRECTION BIT_ULL(1)
148#define SPI_TYPE BIT_ULL(0)
149#define NIOS_SPI_CTRL 0x10
150#define NIOS_SPI_RD (0x1ULL << 62)
151#define NIOS_SPI_WR (0x2ULL << 62)
152#define NIOS_SPI_COMMAND GENMASK_ULL(63, 62)
153#define NIOS_SPI_ADDR GENMASK_ULL(44, 32)
154#define NIOS_SPI_WRITE_DATA GENMASK_ULL(31, 0)
155#define NIOS_SPI_STAT 0x18
156#define NIOS_SPI_VALID BIT_ULL(32)
157#define NIOS_SPI_READ_DATA GENMASK_ULL(31, 0)
158
159#define NIOS_INIT 0x1000
160#define REQ_FEC_MODE GENMASK(23, 8)
161#define REQ_FEC_MODE_SHIFT 8
162#define FEC_MODE_NO 0x0
163#define FEC_MODE_KR 0x5555
164#define FEC_MODE_RS 0xaaaa
165#define NIOS_INIT_START BIT(1)
166#define NIOS_INIT_DONE BIT(0)
167#define NIOS_VERSION 0x1004
168#define NIOS_VERSION_MAJOR_SHIFT 28
169#define NIOS_VERSION_MAJOR GENMASK(31, 28)
170#define NIOS_VERSION_MINOR GENMASK(27, 24)
171#define NIOS_VERSION_PATCH GENMASK(23, 20)
172#define PKVL_A_MODE_STS 0x1020
173#define PKVL_B_MODE_STS 0x1024
174#endif
175
