dpdk/drivers/vdpa/ifc/base/ifcvf.h
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   1/* SPDX-License-Identifier: BSD-3-Clause
   2 * Copyright(c) 2018 Intel Corporation
   3 */
   4
   5#ifndef _IFCVF_H_
   6#define _IFCVF_H_
   7
   8#include "ifcvf_osdep.h"
   9
  10#define IFCVF_VENDOR_ID         0x1AF4
  11#define IFCVF_DEVICE_ID         0x1041
  12#define IFCVF_SUBSYS_VENDOR_ID  0x8086
  13#define IFCVF_SUBSYS_DEVICE_ID  0x001A
  14
  15#define IFCVF_MAX_QUEUES                1
  16
  17#ifndef VIRTIO_F_IOMMU_PLATFORM
  18#define VIRTIO_F_IOMMU_PLATFORM         33
  19#endif
  20
  21/* Common configuration */
  22#define IFCVF_PCI_CAP_COMMON_CFG        1
  23/* Notifications */
  24#define IFCVF_PCI_CAP_NOTIFY_CFG        2
  25/* ISR Status */
  26#define IFCVF_PCI_CAP_ISR_CFG           3
  27/* Device specific configuration */
  28#define IFCVF_PCI_CAP_DEVICE_CFG        4
  29/* PCI configuration access */
  30#define IFCVF_PCI_CAP_PCI_CFG           5
  31
  32#define IFCVF_CONFIG_STATUS_RESET     0x00
  33#define IFCVF_CONFIG_STATUS_ACK       0x01
  34#define IFCVF_CONFIG_STATUS_DRIVER    0x02
  35#define IFCVF_CONFIG_STATUS_DRIVER_OK 0x04
  36#define IFCVF_CONFIG_STATUS_FEATURES_OK 0x08
  37#define IFCVF_CONFIG_STATUS_FAILED    0x80
  38
  39#define IFCVF_MSI_NO_VECTOR     0xffff
  40#define IFCVF_PCI_MAX_RESOURCE  6
  41
  42#define IFCVF_LM_CFG_SIZE               0x40
  43#define IFCVF_LM_RING_STATE_OFFSET      0x20
  44
  45#define IFCVF_LM_LOGGING_CTRL           0x0
  46
  47#define IFCVF_LM_BASE_ADDR_LOW          0x10
  48#define IFCVF_LM_BASE_ADDR_HIGH         0x14
  49#define IFCVF_LM_END_ADDR_LOW           0x18
  50#define IFCVF_LM_END_ADDR_HIGH          0x1c
  51
  52#define IFCVF_LM_DISABLE                0x0
  53#define IFCVF_LM_ENABLE_VF              0x1
  54#define IFCVF_LM_ENABLE_PF              0x3
  55#define IFCVF_LOG_BASE                  0x100000000000
  56#define IFCVF_MEDIATED_VRING            0x200000000000
  57
  58#define IFCVF_32_BIT_MASK               0xffffffff
  59
  60
  61struct ifcvf_pci_cap {
  62        u8 cap_vndr;            /* Generic PCI field: PCI_CAP_ID_VNDR */
  63        u8 cap_next;            /* Generic PCI field: next ptr. */
  64        u8 cap_len;             /* Generic PCI field: capability length */
  65        u8 cfg_type;            /* Identifies the structure. */
  66        u8 bar;                 /* Where to find it. */
  67        u8 padding[3];          /* Pad to full dword. */
  68        u32 offset;             /* Offset within bar. */
  69        u32 length;             /* Length of the structure, in bytes. */
  70};
  71
  72struct ifcvf_pci_notify_cap {
  73        struct ifcvf_pci_cap cap;
  74        u32 notify_off_multiplier;  /* Multiplier for queue_notify_off. */
  75};
  76
  77struct ifcvf_pci_common_cfg {
  78        /* About the whole device. */
  79        u32 device_feature_select;
  80        u32 device_feature;
  81        u32 guest_feature_select;
  82        u32 guest_feature;
  83        u16 msix_config;
  84        u16 num_queues;
  85        u8 device_status;
  86        u8 config_generation;
  87
  88        /* About a specific virtqueue. */
  89        u16 queue_select;
  90        u16 queue_size;
  91        u16 queue_msix_vector;
  92        u16 queue_enable;
  93        u16 queue_notify_off;
  94        u32 queue_desc_lo;
  95        u32 queue_desc_hi;
  96        u32 queue_avail_lo;
  97        u32 queue_avail_hi;
  98        u32 queue_used_lo;
  99        u32 queue_used_hi;
 100};
 101
 102struct ifcvf_net_config {
 103        u8    mac[6];
 104        u16   status;
 105        u16   max_virtqueue_pairs;
 106} __rte_packed;
 107
 108struct ifcvf_pci_mem_resource {
 109        u64      phys_addr; /**< Physical address, 0 if not resource. */
 110        u64      len;       /**< Length of the resource. */
 111        u8       *addr;     /**< Virtual address, NULL when not mapped. */
 112};
 113
 114struct vring_info {
 115        u64 desc;
 116        u64 avail;
 117        u64 used;
 118        u16 size;
 119        u16 last_avail_idx;
 120        u16 last_used_idx;
 121        bool enable;
 122};
 123
 124struct ifcvf_hw {
 125        u64    req_features;
 126        u8     notify_region;
 127        u32    notify_off_multiplier;
 128        struct ifcvf_pci_common_cfg *common_cfg;
 129        struct ifcvf_net_config *dev_cfg;
 130        u8     *isr;
 131        u16    *notify_base;
 132        u16    *notify_addr[IFCVF_MAX_QUEUES * 2];
 133        u8     *lm_cfg;
 134        struct vring_info vring[IFCVF_MAX_QUEUES * 2];
 135        u8 nr_vring;
 136        struct ifcvf_pci_mem_resource mem_resource[IFCVF_PCI_MAX_RESOURCE];
 137};
 138
 139int
 140ifcvf_init_hw(struct ifcvf_hw *hw, PCI_DEV *dev);
 141
 142u64
 143ifcvf_get_features(struct ifcvf_hw *hw);
 144
 145int
 146ifcvf_start_hw(struct ifcvf_hw *hw);
 147
 148void
 149ifcvf_stop_hw(struct ifcvf_hw *hw);
 150
 151void
 152ifcvf_enable_logging(struct ifcvf_hw *hw, u64 log_base, u64 log_size);
 153
 154void
 155ifcvf_disable_logging(struct ifcvf_hw *hw);
 156
 157void
 158ifcvf_notify_queue(struct ifcvf_hw *hw, u16 qid);
 159
 160u8
 161ifcvf_get_notify_region(struct ifcvf_hw *hw);
 162
 163u64
 164ifcvf_get_queue_notify_off(struct ifcvf_hw *hw, int qid);
 165
 166#endif /* _IFCVF_H_ */
 167