LXR dpdk/drivers/net/axgbe/axgbe

   1/*   SPDX-License-Identifier: BSD-3-Clause
   2 *   Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
   3 *   Copyright(c) 2018 Synopsys, Inc. All rights reserved.
   4 */
   5
   6#ifndef RTE_ETH_AXGBE_H_
   7#define RTE_ETH_AXGBE_H_
   8
   9#include <rte_mempool.h>
  10#include <rte_lcore.h>
  11#include "axgbe_common.h"
  12#include "rte_time.h"
  13
  14#define IRQ                             0xff
  15
  16#define AXGBE_TX_MAX_BUF_SIZE           (0x3fff & ~(64 - 1))
  17#define AXGBE_RX_MAX_BUF_SIZE           (0x3fff & ~(64 - 1))
  18#define AXGBE_RX_MIN_BUF_SIZE           (RTE_ETHER_MAX_LEN + RTE_VLAN_HLEN)
  19#define AXGBE_MAX_MAC_ADDRS             32
  20#define AXGBE_MAX_HASH_MAC_ADDRS        256
  21
  22#define AXGBE_RX_BUF_ALIGN              64
  23
  24#define AXGBE_MAX_DMA_CHANNELS          16
  25#define AXGBE_MAX_QUEUES                16
  26#define AXGBE_PRIORITY_QUEUES           8
  27#define AXGBE_DMA_STOP_TIMEOUT          1
  28
  29/* DMA cache settings - Outer sharable, write-back, write-allocate */
  30#define AXGBE_DMA_OS_AXDOMAIN           0x2
  31#define AXGBE_DMA_OS_ARCACHE            0xb
  32#define AXGBE_DMA_OS_AWCACHE            0xf
  33
  34/* DMA cache settings - System, no caches used */
  35#define AXGBE_DMA_SYS_AXDOMAIN          0x3
  36#define AXGBE_DMA_SYS_ARCACHE           0x0
  37#define AXGBE_DMA_SYS_AWCACHE           0x0
  38
  39/* DMA channel interrupt modes */
  40#define AXGBE_IRQ_MODE_EDGE             0
  41#define AXGBE_IRQ_MODE_LEVEL            1
  42
  43#define AXGBE_DMA_INTERRUPT_MASK        0x31c7
  44
  45#define AXGMAC_MIN_PACKET               60
  46#define AXGMAC_STD_PACKET_MTU           1500
  47#define AXGMAC_MAX_STD_PACKET           1518
  48#define AXGMAC_JUMBO_PACKET_MTU         9000
  49#define AXGMAC_MAX_JUMBO_PACKET         9018
  50/* Inter-frame gap + preamble */
  51#define AXGMAC_ETH_PREAMBLE             (12 + 8)
  52
  53#define AXGMAC_PFC_DATA_LEN             46
  54#define AXGMAC_PFC_DELAYS               14000
  55
  56/* PCI BAR mapping */
  57#define AXGBE_AXGMAC_BAR                0
  58#define AXGBE_XPCS_BAR                  1
  59#define AXGBE_MAC_PROP_OFFSET           0x1d000
  60#define AXGBE_I2C_CTRL_OFFSET           0x1e000
  61
  62/* PCI clock frequencies */
  63#define AXGBE_V2_DMA_CLOCK_FREQ         500000000
  64#define AXGBE_V2_PTP_CLOCK_FREQ         125000000
  65
  66/* Timestamp support - values based on 50MHz PTP clock
  67 *   50MHz => 20 nsec
  68 */
  69#define AXGBE_TSTAMP_SSINC       20
  70#define AXGBE_TSTAMP_SNSINC      0
  71#define AXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
  72
  73#define AXGMAC_FIFO_MIN_ALLOC           2048
  74#define AXGMAC_FIFO_UNIT                256
  75#define AXGMAC_FIFO_ALIGN(_x)                            \
  76        (((_x) + AXGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1))
  77#define AXGMAC_FIFO_FC_OFF              2048
  78#define AXGMAC_FIFO_FC_MIN              4096
  79
  80#define AXGBE_TC_MIN_QUANTUM            10
  81
  82/* Flow control queue count */
  83#define AXGMAC_MAX_FLOW_CONTROL_QUEUES  8
  84
  85/* Flow control threshold units */
  86#define AXGMAC_FLOW_CONTROL_UNIT        512
  87#define AXGMAC_FLOW_CONTROL_ALIGN(_x)                           \
  88        (((_x) + AXGMAC_FLOW_CONTROL_UNIT - 1) &                \
  89        ~(AXGMAC_FLOW_CONTROL_UNIT - 1))
  90#define AXGMAC_FLOW_CONTROL_VALUE(_x)                           \
  91        (((_x) < 1024) ? 0 : ((_x) / AXGMAC_FLOW_CONTROL_UNIT) - 2)
  92#define AXGMAC_FLOW_CONTROL_MAX         33280
  93
  94/* Maximum MAC address hash table size (256 bits = 8 dword) */
  95#define AXGBE_MAC_HASH_TABLE_SIZE       8
  96
  97/* Receive Side Scaling */
  98#define AXGBE_RSS_OFFLOAD  ( \
  99        RTE_ETH_RSS_IPV4 | \
 100        RTE_ETH_RSS_NONFRAG_IPV4_TCP | \
 101        RTE_ETH_RSS_NONFRAG_IPV4_UDP | \
 102        RTE_ETH_RSS_IPV6 | \
 103        RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
 104        RTE_ETH_RSS_NONFRAG_IPV6_UDP)
 105
 106#define AXGBE_RSS_HASH_KEY_SIZE         40
 107#define AXGBE_RSS_MAX_TABLE_SIZE        256
 108#define AXGBE_RSS_LOOKUP_TABLE_TYPE     0
 109#define AXGBE_RSS_HASH_KEY_TYPE         1
 110
 111/* Auto-negotiation */
 112#define AXGBE_AN_MS_TIMEOUT             500
 113#define AXGBE_LINK_TIMEOUT              5
 114
 115#define AXGBE_SGMII_AN_LINK_STATUS      BIT(1)
 116#define AXGBE_SGMII_AN_LINK_SPEED       (BIT(2) | BIT(3))
 117#define AXGBE_SGMII_AN_LINK_SPEED_100   0x04
 118#define AXGBE_SGMII_AN_LINK_SPEED_1000  0x08
 119#define AXGBE_SGMII_AN_LINK_DUPLEX      BIT(4)
 120
 121/* ECC correctable error notification window (seconds) */
 122#define AXGBE_ECC_LIMIT                 60
 123
 124/* MDIO port types */
 125#define AXGMAC_MAX_C22_PORT             3
 126
 127/* The max frame size with default MTU */
 128#define AXGBE_ETH_MAX_LEN ( \
 129        RTE_ETHER_MTU + \
 130        RTE_ETHER_HDR_LEN + \
 131        RTE_ETHER_CRC_LEN)
 132
 133/* Helper macro for descriptor handling
 134 *  Always use AXGBE_GET_DESC_DATA to access the descriptor data
 135 *  since the index is free-running and needs to be and-ed
 136 *  with the descriptor count value of the ring to index to
 137 *  the proper descriptor data.
 138 */
 139#define AXGBE_GET_DESC_DATA(_ring, _idx)                        \
 140        ((_ring)->rdata +                                       \
 141         ((_idx) & ((_ring)->rdesc_count - 1)))
 142
 143struct axgbe_port;
 144
 145enum axgbe_state {
 146        AXGBE_DOWN,
 147        AXGBE_LINK_INIT,
 148        AXGBE_LINK_ERR,
 149        AXGBE_STOPPED,
 150};
 151
 152enum axgbe_int {
 153        AXGMAC_INT_DMA_CH_SR_TI,
 154        AXGMAC_INT_DMA_CH_SR_TPS,
 155        AXGMAC_INT_DMA_CH_SR_TBU,
 156        AXGMAC_INT_DMA_CH_SR_RI,
 157        AXGMAC_INT_DMA_CH_SR_RBU,
 158        AXGMAC_INT_DMA_CH_SR_RPS,
 159        AXGMAC_INT_DMA_CH_SR_TI_RI,
 160        AXGMAC_INT_DMA_CH_SR_FBE,
 161        AXGMAC_INT_DMA_ALL,
 162};
 163
 164enum axgbe_int_state {
 165        AXGMAC_INT_STATE_SAVE,
 166        AXGMAC_INT_STATE_RESTORE,
 167};
 168
 169enum axgbe_ecc_sec {
 170        AXGBE_ECC_SEC_TX,
 171        AXGBE_ECC_SEC_RX,
 172        AXGBE_ECC_SEC_DESC,
 173};
 174
 175enum axgbe_speed {
 176        AXGBE_SPEED_1000 = 0,
 177        AXGBE_SPEED_2500,
 178        AXGBE_SPEED_10000,
 179        AXGBE_SPEEDS,
 180};
 181
 182enum axgbe_xpcs_access {
 183        AXGBE_XPCS_ACCESS_V1 = 0,
 184        AXGBE_XPCS_ACCESS_V2,
 185};
 186
 187enum axgbe_an_mode {
 188        AXGBE_AN_MODE_CL73 = 0,
 189        AXGBE_AN_MODE_CL73_REDRV,
 190        AXGBE_AN_MODE_CL37,
 191        AXGBE_AN_MODE_CL37_SGMII,
 192        AXGBE_AN_MODE_NONE,
 193};
 194
 195enum axgbe_an {
 196        AXGBE_AN_READY = 0,
 197        AXGBE_AN_PAGE_RECEIVED,
 198        AXGBE_AN_INCOMPAT_LINK,
 199        AXGBE_AN_COMPLETE,
 200        AXGBE_AN_NO_LINK,
 201        AXGBE_AN_ERROR,
 202};
 203
 204enum axgbe_rx {
 205        AXGBE_RX_BPA = 0,
 206        AXGBE_RX_XNP,
 207        AXGBE_RX_COMPLETE,
 208        AXGBE_RX_ERROR,
 209};
 210
 211enum axgbe_mode {
 212        AXGBE_MODE_KX_1000 = 0,
 213        AXGBE_MODE_KX_2500,
 214        AXGBE_MODE_KR,
 215        AXGBE_MODE_X,
 216        AXGBE_MODE_SGMII_100,
 217        AXGBE_MODE_SGMII_1000,
 218        AXGBE_MODE_SFI,
 219        AXGBE_MODE_UNKNOWN,
 220};
 221
 222enum axgbe_speedset {
 223        AXGBE_SPEEDSET_1000_10000 = 0,
 224        AXGBE_SPEEDSET_2500_10000,
 225};
 226
 227enum axgbe_mdio_mode {
 228        AXGBE_MDIO_MODE_NONE = 0,
 229        AXGBE_MDIO_MODE_CL22,
 230        AXGBE_MDIO_MODE_CL45,
 231};
 232
 233struct axgbe_phy {
 234        uint32_t supported;
 235        uint32_t advertising;
 236        uint32_t lp_advertising;
 237
 238        int address;
 239
 240        int autoneg;
 241        int speed;
 242        int duplex;
 243
 244        int link;
 245
 246        int pause_autoneg;
 247        int tx_pause;
 248        int rx_pause;
 249};
 250
 251enum axgbe_i2c_cmd {
 252        AXGBE_I2C_CMD_READ = 0,
 253        AXGBE_I2C_CMD_WRITE,
 254};
 255
 256struct axgbe_i2c_op {
 257        enum axgbe_i2c_cmd cmd;
 258
 259        unsigned int target;
 260
 261        uint8_t *buf;
 262        unsigned int len;
 263};
 264
 265struct axgbe_i2c_op_state {
 266        struct axgbe_i2c_op *op;
 267
 268        unsigned int tx_len;
 269        unsigned char *tx_buf;
 270
 271        unsigned int rx_len;
 272        unsigned char *rx_buf;
 273
 274        unsigned int tx_abort_source;
 275
 276        int ret;
 277};
 278
 279struct axgbe_i2c {
 280        unsigned int started;
 281        unsigned int max_speed_mode;
 282        unsigned int rx_fifo_size;
 283        unsigned int tx_fifo_size;
 284
 285        struct axgbe_i2c_op_state op_state;
 286};
 287
 288struct axgbe_hw_if {
 289        void (*config_flow_control)(struct axgbe_port *);
 290        int (*config_rx_mode)(struct axgbe_port *);
 291
 292        int (*init)(struct axgbe_port *);
 293
 294        int (*read_mmd_regs)(struct axgbe_port *, int, int);
 295        void (*write_mmd_regs)(struct axgbe_port *, int, int, int);
 296        int (*set_speed)(struct axgbe_port *, int);
 297
 298        int (*set_ext_mii_mode)(struct axgbe_port *, unsigned int,
 299                                enum axgbe_mdio_mode);
 300        int (*read_ext_mii_regs)(struct axgbe_port *, int, int);
 301        int (*write_ext_mii_regs)(struct axgbe_port *, int, int, uint16_t);
 302
 303        /* For FLOW ctrl */
 304        int (*config_tx_flow_control)(struct axgbe_port *);
 305        int (*config_rx_flow_control)(struct axgbe_port *);
 306
 307        /* vlan */
 308        int (*enable_rx_vlan_stripping)(struct axgbe_port *);
 309        int (*disable_rx_vlan_stripping)(struct axgbe_port *);
 310        int (*enable_rx_vlan_filtering)(struct axgbe_port *);
 311        int (*disable_rx_vlan_filtering)(struct axgbe_port *);
 312        int (*update_vlan_hash_table)(struct axgbe_port *);
 313
 314        int (*exit)(struct axgbe_port *);
 315};
 316
 317/* This structure represents implementation specific routines for an
 318 * implementation of a PHY. All routines are required unless noted below.
 319 *   Optional routines:
 320 *     kr_training_pre, kr_training_post
 321 */
 322struct axgbe_phy_impl_if {
 323        /* Perform Setup/teardown actions */
 324        int (*init)(struct axgbe_port *);
 325        void (*exit)(struct axgbe_port *);
 326
 327        /* Perform start/stop specific actions */
 328        int (*reset)(struct axgbe_port *);
 329        int (*start)(struct axgbe_port *);
 330        void (*stop)(struct axgbe_port *);
 331
 332        /* Return the link status */
 333        int (*link_status)(struct axgbe_port *, int *);
 334
 335        /* Indicate if a particular speed is valid */
 336        int (*valid_speed)(struct axgbe_port *, int);
 337
 338        /* Check if the specified mode can/should be used */
 339        bool (*use_mode)(struct axgbe_port *, enum axgbe_mode);
 340        /* Switch the PHY into various modes */
 341        void (*set_mode)(struct axgbe_port *, enum axgbe_mode);
 342        /* Retrieve mode needed for a specific speed */
 343        enum axgbe_mode (*get_mode)(struct axgbe_port *, int);
 344        /* Retrieve new/next mode when trying to auto-negotiate */
 345        enum axgbe_mode (*switch_mode)(struct axgbe_port *);
 346        /* Retrieve current mode */
 347        enum axgbe_mode (*cur_mode)(struct axgbe_port *);
 348
 349        /* Retrieve current auto-negotiation mode */
 350        enum axgbe_an_mode (*an_mode)(struct axgbe_port *);
 351
 352        /* Configure auto-negotiation settings */
 353        int (*an_config)(struct axgbe_port *);
 354
 355        /* Set/override auto-negotiation advertisement settings */
 356        unsigned int (*an_advertising)(struct axgbe_port *port);
 357
 358        /* Process results of auto-negotiation */
 359        enum axgbe_mode (*an_outcome)(struct axgbe_port *);
 360
 361        /* Pre/Post auto-negotiation support */
 362        void (*an_pre)(struct axgbe_port *port);
 363        void (*an_post)(struct axgbe_port *port);
 364
 365        /* Pre/Post KR training enablement support */
 366        void (*kr_training_pre)(struct axgbe_port *);
 367        void (*kr_training_post)(struct axgbe_port *);
 368};
 369
 370struct axgbe_phy_if {
 371        /* For PHY setup/teardown */
 372        int (*phy_init)(struct axgbe_port *);
 373        void (*phy_exit)(struct axgbe_port *);
 374
 375        /* For PHY support when setting device up/down */
 376        int (*phy_reset)(struct axgbe_port *);
 377        int (*phy_start)(struct axgbe_port *);
 378        void (*phy_stop)(struct axgbe_port *);
 379
 380        /* For PHY support while device is up */
 381        void (*phy_status)(struct axgbe_port *);
 382        int (*phy_config_aneg)(struct axgbe_port *);
 383
 384        /* For PHY settings validation */
 385        int (*phy_valid_speed)(struct axgbe_port *, int);
 386        /* For single interrupt support */
 387        void (*an_isr)(struct axgbe_port *);
 388        /* PHY implementation specific services */
 389        struct axgbe_phy_impl_if phy_impl;
 390};
 391
 392struct axgbe_i2c_if {
 393        /* For initial I2C setup */
 394        int (*i2c_init)(struct axgbe_port *);
 395
 396        /* For I2C support when setting device up/down */
 397        int (*i2c_start)(struct axgbe_port *);
 398        void (*i2c_stop)(struct axgbe_port *);
 399
 400        /* For performing I2C operations */
 401        int (*i2c_xfer)(struct axgbe_port *, struct axgbe_i2c_op *);
 402};
 403
 404/* This structure contains flags that indicate what hardware features
 405 * or configurations are present in the device.
 406 */
 407struct axgbe_hw_features {
 408        /* HW Version */
 409        unsigned int version;
 410
 411        /* HW Feature Register0 */
 412        unsigned int gmii;              /* 1000 Mbps support */
 413        unsigned int vlhash;            /* VLAN Hash Filter */
 414        unsigned int sma;               /* SMA(MDIO) Interface */
 415        unsigned int rwk;               /* PMT remote wake-up packet */
 416        unsigned int mgk;               /* PMT magic packet */
 417        unsigned int mmc;               /* RMON module */
 418        unsigned int aoe;               /* ARP Offload */
 419        unsigned int ts;                /* IEEE 1588-2008 Advanced Timestamp */
 420        unsigned int eee;               /* Energy Efficient Ethernet */
 421        unsigned int tx_coe;            /* Tx Checksum Offload */
 422        unsigned int rx_coe;            /* Rx Checksum Offload */
 423        unsigned int addn_mac;          /* Additional MAC Addresses */
 424        unsigned int ts_src;            /* Timestamp Source */
 425        unsigned int sa_vlan_ins;       /* Source Address or VLAN Insertion */
 426
 427        /* HW Feature Register1 */
 428        unsigned int rx_fifo_size;      /* MTL Receive FIFO Size */
 429        unsigned int tx_fifo_size;      /* MTL Transmit FIFO Size */
 430        unsigned int adv_ts_hi;         /* Advance Timestamping High Word */
 431        unsigned int dma_width;         /* DMA width */
 432        unsigned int dcb;               /* DCB Feature */
 433        unsigned int sph;               /* Split Header Feature */
 434        unsigned int tso;               /* TCP Segmentation Offload */
 435        unsigned int dma_debug;         /* DMA Debug Registers */
 436        unsigned int rss;               /* Receive Side Scaling */
 437        unsigned int tc_cnt;            /* Number of Traffic Classes */
 438        unsigned int hash_table_size;   /* Hash Table Size */
 439        unsigned int l3l4_filter_num;   /* Number of L3-L4 Filters */
 440
 441        /* HW Feature Register2 */
 442        unsigned int rx_q_cnt;          /* Number of MTL Receive Queues */
 443        unsigned int tx_q_cnt;          /* Number of MTL Transmit Queues */
 444        unsigned int rx_ch_cnt;         /* Number of DMA Receive Channels */
 445        unsigned int tx_ch_cnt;         /* Number of DMA Transmit Channels */
 446        unsigned int pps_out_num;       /* Number of PPS outputs */
 447        unsigned int aux_snap_num;      /* Number of Aux snapshot inputs */
 448
 449        /* HW Feature Register3 */
 450        unsigned int tx_q_vlan_tag_ins; /* Queue/Channel based VLAN tag */
 451                                        /* insertion on Tx Enable */
 452        unsigned int no_of_vlan_extn;   /* Number of Extended VLAN Tag */
 453                                        /* Filters Enabled */
 454};
 455
 456struct axgbe_version_data {
 457        void (*init_function_ptrs_phy_impl)(struct axgbe_phy_if *);
 458        enum axgbe_xpcs_access xpcs_access;
 459        unsigned int mmc_64bit;
 460        unsigned int tx_max_fifo_size;
 461        unsigned int rx_max_fifo_size;
 462        unsigned int tx_tstamp_workaround;
 463        unsigned int ecc_support;
 464        unsigned int i2c_support;
 465        unsigned int an_cdr_workaround;
 466};
 467
 468struct axgbe_mmc_stats {
 469        /* Tx Stats */
 470        uint64_t txoctetcount_gb;
 471        uint64_t txframecount_gb;
 472        uint64_t txbroadcastframes_g;
 473        uint64_t txmulticastframes_g;
 474        uint64_t tx64octets_gb;
 475        uint64_t tx65to127octets_gb;
 476        uint64_t tx128to255octets_gb;
 477        uint64_t tx256to511octets_gb;
 478        uint64_t tx512to1023octets_gb;
 479        uint64_t tx1024tomaxoctets_gb;
 480        uint64_t txunicastframes_gb;
 481        uint64_t txmulticastframes_gb;
 482        uint64_t txbroadcastframes_gb;
 483        uint64_t txunderflowerror;
 484        uint64_t txoctetcount_g;
 485        uint64_t txframecount_g;
 486        uint64_t txpauseframes;
 487        uint64_t txvlanframes_g;
 488
 489        /* Rx Stats */
 490        uint64_t rxframecount_gb;
 491        uint64_t rxoctetcount_gb;
 492        uint64_t rxoctetcount_g;
 493        uint64_t rxbroadcastframes_g;
 494        uint64_t rxmulticastframes_g;
 495        uint64_t rxcrcerror;
 496        uint64_t rxrunterror;
 497        uint64_t rxjabbererror;
 498        uint64_t rxundersize_g;
 499        uint64_t rxoversize_g;
 500        uint64_t rx64octets_gb;
 501        uint64_t rx65to127octets_gb;
 502        uint64_t rx128to255octets_gb;
 503        uint64_t rx256to511octets_gb;
 504        uint64_t rx512to1023octets_gb;
 505        uint64_t rx1024tomaxoctets_gb;
 506        uint64_t rxunicastframes_g;
 507        uint64_t rxlengtherror;
 508        uint64_t rxoutofrangetype;
 509        uint64_t rxpauseframes;
 510        uint64_t rxfifooverflow;
 511        uint64_t rxvlanframes_gb;
 512        uint64_t rxwatchdogerror;
 513};
 514
 515/* Flow control parameters */
 516struct xgbe_fc_info {
 517        uint32_t high_water[AXGBE_PRIORITY_QUEUES];
 518        uint32_t low_water[AXGBE_PRIORITY_QUEUES];
 519        uint16_t pause_time[AXGBE_PRIORITY_QUEUES];
 520        uint16_t send_xon;
 521        enum rte_eth_fc_mode mode;
 522        uint8_t autoneg;
 523};
 524
 525/*
 526 * Structure to store private data for each port.
 527 */
 528struct axgbe_port {
 529        /*  Ethdev where port belongs*/
 530        struct rte_eth_dev *eth_dev;
 531        /* Pci dev info */
 532        const struct rte_pci_device *pci_dev;
 533        /* Version related data */
 534        struct axgbe_version_data *vdata;
 535
 536        /* AXGMAC/XPCS related mmio registers */
 537        void *xgmac_regs;       /* AXGMAC CSRs */
 538        void *xpcs_regs;        /* XPCS MMD registers */
 539        void *xprop_regs;       /* AXGBE property registers */
 540        void *xi2c_regs;        /* AXGBE I2C CSRs */
 541
 542        bool cdr_track_early;
 543        /* XPCS indirect addressing lock */
 544        unsigned int xpcs_window_def_reg;
 545        unsigned int xpcs_window_sel_reg;
 546        unsigned int xpcs_window;
 547        unsigned int xpcs_window_size;
 548        unsigned int xpcs_window_mask;
 549
 550        /* Flags representing axgbe_state */
 551        uint32_t dev_state;
 552
 553        struct axgbe_hw_if hw_if;
 554        struct axgbe_phy_if phy_if;
 555        struct axgbe_i2c_if i2c_if;
 556
 557        /* AXI DMA settings */
 558        unsigned int coherent;
 559        unsigned int axdomain;
 560        unsigned int arcache;
 561        unsigned int awcache;
 562
 563        unsigned int tx_max_channel_count;
 564        unsigned int rx_max_channel_count;
 565        unsigned int channel_count;
 566        unsigned int tx_ring_count;
 567        unsigned int tx_desc_count;
 568        unsigned int rx_ring_count;
 569        unsigned int rx_desc_count;
 570
 571        unsigned int tx_max_q_count;
 572        unsigned int rx_max_q_count;
 573        unsigned int tx_q_count;
 574        unsigned int rx_q_count;
 575
 576        /* Tx/Rx common settings */
 577        unsigned int pblx8;
 578
 579        /* Tx settings */
 580        unsigned int tx_sf_mode;
 581        unsigned int tx_threshold;
 582        unsigned int tx_pbl;
 583        unsigned int tx_osp_mode;
 584        unsigned int tx_max_fifo_size;
 585
 586        /* Rx settings */
 587        unsigned int rx_sf_mode;
 588        unsigned int rx_threshold;
 589        unsigned int rx_pbl;
 590        unsigned int rx_max_fifo_size;
 591        unsigned int rx_buf_size;
 592
 593        /* Device clocks */
 594        unsigned long sysclk_rate;
 595        unsigned long ptpclk_rate;
 596
 597        /* Keeps track of power mode */
 598        unsigned int power_down;
 599
 600        /* Current PHY settings */
 601        int phy_link;
 602        int phy_speed;
 603
 604        pthread_mutex_t xpcs_mutex;
 605        pthread_mutex_t i2c_mutex;
 606        pthread_mutex_t an_mutex;
 607        pthread_mutex_t phy_mutex;
 608
 609        /* Flow control settings */
 610        unsigned int pause_autoneg;
 611        unsigned int tx_pause;
 612        unsigned int rx_pause;
 613        unsigned int rx_rfa[AXGBE_MAX_QUEUES];
 614        unsigned int rx_rfd[AXGBE_MAX_QUEUES];
 615        unsigned int fifo;
 616        unsigned int pfc_map[AXGBE_MAX_QUEUES];
 617
 618        /* Receive Side Scaling settings */
 619        u8 rss_key[AXGBE_RSS_HASH_KEY_SIZE];
 620        uint32_t rss_table[AXGBE_RSS_MAX_TABLE_SIZE];
 621        uint32_t rss_options;
 622        int rss_enable;
 623        uint64_t rss_hf;
 624
 625        /* Hardware features of the device */
 626        struct axgbe_hw_features hw_feat;
 627
 628        struct rte_ether_addr mac_addr;
 629
 630        /* Software Tx/Rx structure pointers*/
 631        void **rx_queues;
 632        void **tx_queues;
 633
 634        /* MDIO/PHY related settings */
 635        unsigned int phy_started;
 636        void *phy_data;
 637        struct axgbe_phy phy;
 638        int mdio_mmd;
 639        unsigned long link_check;
 640        volatile int mdio_completion;
 641
 642        unsigned int kr_redrv;
 643
 644        /* Auto-negotiation atate machine support */
 645        unsigned int an_int;
 646        unsigned int an_status;
 647        enum axgbe_an an_result;
 648        enum axgbe_an an_state;
 649        enum axgbe_rx kr_state;
 650        enum axgbe_rx kx_state;
 651        unsigned int an_supported;
 652        unsigned int parallel_detect;
 653        unsigned int fec_ability;
 654        unsigned long an_start;
 655        enum axgbe_an_mode an_mode;
 656
 657        /* I2C support */
 658        struct axgbe_i2c i2c;
 659        volatile int i2c_complete;
 660
 661        /* CRC stripping by H/w for Rx packet*/
 662        int crc_strip_enable;
 663        /* csum enable to hardware */
 664        uint32_t rx_csum_enable;
 665
 666        struct axgbe_mmc_stats mmc_stats;
 667        struct xgbe_fc_info fc;
 668
 669        /* Hash filtering */
 670        unsigned int hash_table_shift;
 671        unsigned int hash_table_count;
 672        unsigned int uc_hash_mac_addr;
 673        unsigned int uc_hash_table[AXGBE_MAC_HASH_TABLE_SIZE];
 674
 675        /* Filtering support */
 676        unsigned long active_vlans[VLAN_TABLE_SIZE];
 677
 678        /* For IEEE1588 PTP */
 679        struct rte_timecounter systime_tc;
 680        struct rte_timecounter tx_tstamp;
 681        unsigned int tstamp_addend;
 682
 683};
 684
 685void axgbe_init_function_ptrs_dev(struct axgbe_hw_if *hw_if);
 686void axgbe_init_function_ptrs_phy(struct axgbe_phy_if *phy_if);
 687void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if);
 688void axgbe_init_function_ptrs_i2c(struct axgbe_i2c_if *i2c_if);
 689void axgbe_set_mac_addn_addr(struct axgbe_port *pdata, u8 *addr,
 690                             uint32_t index);
 691void axgbe_set_mac_hash_table(struct axgbe_port *pdata, u8 *addr, bool add);
 692int axgbe_write_rss_lookup_table(struct axgbe_port *pdata);
 693int axgbe_write_rss_hash_key(struct axgbe_port *pdata);
 694
 695#endif /* RTE_ETH_AXGBE_H_ */
 696