1/* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5#ifndef _CXGBE_L2T_H_ 6#define _CXGBE_L2T_H_ 7 8#include "base/t4_msg.h" 9 10enum { 11 L2T_SIZE = 4096 /* # of L2T entries */ 12}; 13 14enum { 15 L2T_STATE_VALID, /* entry is up to date */ 16 L2T_STATE_SYNC_WRITE, /* synchronous write of entry underway */ 17 18 /* when state is one of the below the entry is not hashed */ 19 L2T_STATE_SWITCHING, /* entry is being used by a switching filter */ 20 L2T_STATE_UNUSED /* entry not in use */ 21}; 22 23/* 24 * State for the corresponding entry of the HW L2 table. 25 */ 26struct l2t_entry { 27 u16 state; /* entry state */ 28 u16 idx; /* entry index within in-memory table */ 29 u16 vlan; /* VLAN TCI (id: bits 0-11, prio: 13-15 */ 30 u8 lport; /* destination port */ 31 u8 dmac[RTE_ETHER_ADDR_LEN]; /* destination MAC address */ 32 rte_spinlock_t lock; /* entry lock */ 33 u32 refcnt; /* entry reference count */ 34}; 35 36struct l2t_data { 37 unsigned int l2t_start; /* start index of our piece of the L2T */ 38 unsigned int l2t_size; /* number of entries in l2tab */ 39 rte_rwlock_t lock; /* table rw lock */ 40 struct l2t_entry l2tab[0]; /* MUST BE LAST */ 41}; 42 43#define L2T_LPBK true 44#define L2T_ARPMISS true 45 46/* identifies sync vs async L2T_WRITE_REQs */ 47#define S_SYNC_WR 12 48#define V_SYNC_WR(x) ((x) << S_SYNC_WR) 49#define F_SYNC_WR V_SYNC_WR(1) 50 51struct l2t_data *t4_init_l2t(unsigned int l2t_start, unsigned int l2t_end); 52void t4_cleanup_l2t(struct adapter *adap); 53struct l2t_entry *cxgbe_l2t_alloc_switching(struct rte_eth_dev *dev, u16 vlan, 54 u8 port, u8 *dmac); 55void cxgbe_l2t_release(struct l2t_entry *e); 56void cxgbe_do_l2t_write_rpl(struct adapter *p, 57 const struct cpl_l2t_write_rpl *rpl); 58#endif /* _CXGBE_L2T_H_ */ 59