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5#ifndef _HNS3_DCB_H_
6#define _HNS3_DCB_H_
7
8#include <stdint.h>
9
10#include "hns3_cmd.h"
11
12#define HNS3_ETHER_MAX_RATE 100000
13
14
15#define HNS3_TX_MAC_PAUSE_EN_MSK BIT(0)
16#define HNS3_RX_MAC_PAUSE_EN_MSK BIT(1)
17
18#define HNS3_DEFAULT_PAUSE_TRANS_GAP 0x18
19#define HNS3_DEFAULT_PAUSE_TRANS_TIME 0xFFFF
20
21
22#define HNS3_DCB_TX_SCHD_DWRR_MSK BIT(0)
23#define HNS3_DCB_TX_SCHD_SP_MSK 0xFE
24
25enum hns3_shap_bucket {
26 HNS3_DCB_SHAP_C_BUCKET = 0,
27 HNS3_DCB_SHAP_P_BUCKET,
28};
29
30struct hns3_priority_weight_cmd {
31 uint8_t pri_id;
32 uint8_t dwrr;
33 uint8_t rsvd[22];
34};
35
36struct hns3_qs_weight_cmd {
37 uint16_t qs_id;
38 uint8_t dwrr;
39 uint8_t rsvd[21];
40};
41
42struct hns3_pg_weight_cmd {
43 uint8_t pg_id;
44 uint8_t dwrr;
45 uint8_t rsvd[22];
46};
47
48struct hns3_ets_tc_weight_cmd {
49 uint8_t tc_weight[HNS3_MAX_TC_NUM];
50 uint8_t weight_offset;
51 uint8_t rsvd[15];
52};
53
54struct hns3_qs_to_pri_link_cmd {
55 uint16_t qs_id;
56 uint16_t rsvd;
57 uint8_t priority;
58#define HNS3_DCB_QS_PRI_LINK_VLD_MSK BIT(0)
59#define HNS3_DCB_QS_ID_L_MSK GENMASK(9, 0)
60#define HNS3_DCB_QS_ID_L_S 0
61#define HNS3_DCB_QS_ID_H_MSK GENMASK(14, 10)
62#define HNS3_DCB_QS_ID_H_S 10
63#define HNS3_DCB_QS_ID_H_EXT_S 11
64#define HNS3_DCB_QS_ID_H_EXT_MSK GENMASK(15, 11)
65 uint8_t link_vld;
66 uint8_t rsvd1[18];
67};
68
69struct hns3_nq_to_qs_link_cmd {
70 uint16_t nq_id;
71 uint16_t rsvd;
72#define HNS3_DCB_Q_QS_LINK_VLD_MSK BIT(10)
73 uint16_t qset_id;
74 uint8_t rsvd1[18];
75};
76
77#define HNS3_DCB_SHAP_IR_B_MSK GENMASK(7, 0)
78#define HNS3_DCB_SHAP_IR_B_LSH 0
79#define HNS3_DCB_SHAP_IR_U_MSK GENMASK(11, 8)
80#define HNS3_DCB_SHAP_IR_U_LSH 8
81#define HNS3_DCB_SHAP_IR_S_MSK GENMASK(15, 12)
82#define HNS3_DCB_SHAP_IR_S_LSH 12
83#define HNS3_DCB_SHAP_BS_B_MSK GENMASK(20, 16)
84#define HNS3_DCB_SHAP_BS_B_LSH 16
85#define HNS3_DCB_SHAP_BS_S_MSK GENMASK(25, 21)
86#define HNS3_DCB_SHAP_BS_S_LSH 21
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99
100#define HNS3_TM_RATE_VLD_B 0
101
102struct hns3_pri_shapping_cmd {
103 uint8_t pri_id;
104 uint8_t rsvd[3];
105 uint32_t pri_shapping_para;
106 uint8_t flag;
107 uint8_t rsvd1[3];
108 uint32_t pri_rate;
109 uint8_t rsvd2[8];
110};
111
112struct hns3_pg_shapping_cmd {
113 uint8_t pg_id;
114 uint8_t rsvd[3];
115 uint32_t pg_shapping_para;
116 uint8_t flag;
117 uint8_t rsvd1[3];
118 uint32_t pg_rate;
119 uint8_t rsvd2[8];
120};
121
122struct hns3_port_shapping_cmd {
123 uint32_t port_shapping_para;
124 uint8_t flag;
125 uint8_t rsvd[3];
126 uint32_t port_rate;
127 uint8_t rsvd1[12];
128};
129
130#define HNS3_BP_GRP_NUM 32
131#define HNS3_BP_SUB_GRP_ID_S 0
132#define HNS3_BP_SUB_GRP_ID_M GENMASK(4, 0)
133#define HNS3_BP_GRP_ID_S 5
134#define HNS3_BP_GRP_ID_M GENMASK(9, 5)
135
136struct hns3_bp_to_qs_map_cmd {
137 uint8_t tc_id;
138 uint8_t rsvd[2];
139 uint8_t qs_group_id;
140 uint32_t qs_bit_map;
141 uint32_t rsvd1[4];
142};
143
144struct hns3_pfc_en_cmd {
145 uint8_t tx_rx_en_bitmap;
146 uint8_t pri_en_bitmap;
147 uint8_t rsvd[22];
148};
149
150struct hns3_cfg_pause_param_cmd {
151 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
152 uint8_t pause_trans_gap;
153 uint8_t rsvd;
154 uint16_t pause_trans_time;
155 uint8_t rsvd1[6];
156
157 uint8_t mac_addr_extra[RTE_ETHER_ADDR_LEN];
158 uint16_t rsvd2;
159};
160
161struct hns3_pg_to_pri_link_cmd {
162 uint8_t pg_id;
163 uint8_t rsvd1[3];
164 uint8_t pri_bit_map;
165 uint8_t rsvd2[19];
166};
167
168enum hns3_shaper_level {
169 HNS3_SHAPER_LVL_PRI = 0,
170 HNS3_SHAPER_LVL_PG = 1,
171 HNS3_SHAPER_LVL_PORT = 2,
172 HNS3_SHAPER_LVL_QSET = 3,
173 HNS3_SHAPER_LVL_CNT = 4,
174 HNS3_SHAPER_LVL_VF = 0,
175 HNS3_SHAPER_LVL_PF = 1,
176};
177
178struct hns3_shaper_parameter {
179 uint32_t ir_b;
180 uint32_t ir_u;
181 uint32_t ir_s;
182};
183
184#define hns3_dcb_set_field(dest, string, val) \
185 hns3_set_field((dest), \
186 (HNS3_DCB_SHAP_##string##_MSK), \
187 (HNS3_DCB_SHAP_##string##_LSH), val)
188#define hns3_dcb_get_field(src, string) \
189 hns3_get_field((src), (HNS3_DCB_SHAP_##string##_MSK), \
190 (HNS3_DCB_SHAP_##string##_LSH))
191
192int hns3_pause_addr_cfg(struct hns3_hw *hw, const uint8_t *mac_addr);
193
194int hns3_dcb_configure(struct hns3_adapter *hns);
195
196int hns3_dcb_init(struct hns3_hw *hw);
197
198int hns3_dcb_init_hw(struct hns3_hw *hw);
199
200int hns3_dcb_info_init(struct hns3_hw *hw);
201
202int hns3_fc_enable(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf);
203
204int hns3_dcb_pfc_enable(struct rte_eth_dev *dev,
205 struct rte_eth_pfc_conf *pfc_conf);
206
207int hns3_queue_to_tc_mapping(struct hns3_hw *hw, uint16_t nb_rx_q,
208 uint16_t nb_tx_q);
209
210int hns3_update_queue_map_configure(struct hns3_adapter *hns);
211int hns3_port_shaper_update(struct hns3_hw *hw, uint32_t speed);
212uint8_t hns3_txq_mapped_tc_get(struct hns3_hw *hw, uint16_t txq_no);
213
214#endif
215
