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5
6
7#include <rte_string_fns.h>
8#include <ethdev_driver.h>
9#include <rte_kvargs.h>
10#include <rte_log.h>
11#include <rte_malloc.h>
12#include <rte_bus_vdev.h>
13
14#include <fcntl.h>
15#include <linux/ethtool.h>
16#include <linux/sockios.h>
17#include <net/if.h>
18#include <net/if_arp.h>
19#include <sys/ioctl.h>
20#include <sys/socket.h>
21#include <sys/stat.h>
22#include <sys/types.h>
23
24#include <rte_mvep_common.h>
25#include "mrvl_ethdev.h"
26#include "mrvl_qos.h"
27#include "mrvl_flow.h"
28#include "mrvl_mtr.h"
29#include "mrvl_tm.h"
30
31
32#define MRVL_MUSDK_HIFS_RESERVED 0x0F
33
34#define MRVL_MUSDK_BPOOLS_RESERVED 0x07
35
36#define MRVL_MUSDK_RSS_RESERVED 0x0F
37
38#define MRVL_MUSDK_HIFS_MAX 9
39
40
41#define MRVL_MUSDK_PREFETCH_SHIFT 2
42
43
44
45
46#define MRVL_MAC_ADDRS_MAX (1 + 25)
47#define MRVL_MATCH_LEN 16
48#define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
49
50#define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
51
52#define MRVL_IFACE_NAME_ARG "iface"
53#define MRVL_CFG_ARG "cfg"
54
55#define MRVL_ARP_LENGTH 28
56
57#define MRVL_COOKIE_ADDR_INVALID ~0ULL
58#define MRVL_COOKIE_HIGH_ADDR_MASK 0xffffff0000000000
59
60
61#define MRVL_RX_OFFLOADS (RTE_ETH_RX_OFFLOAD_VLAN_FILTER | \
62 RTE_ETH_RX_OFFLOAD_CHECKSUM)
63
64
65#define MRVL_TX_OFFLOAD_CHECKSUM (RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | \
66 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | \
67 RTE_ETH_TX_OFFLOAD_TCP_CKSUM)
68#define MRVL_TX_OFFLOADS (MRVL_TX_OFFLOAD_CHECKSUM | \
69 RTE_ETH_TX_OFFLOAD_MULTI_SEGS)
70
71#define MRVL_TX_PKT_OFFLOADS (RTE_MBUF_F_TX_IP_CKSUM | \
72 RTE_MBUF_F_TX_TCP_CKSUM | \
73 RTE_MBUF_F_TX_UDP_CKSUM)
74
75static const char * const valid_args[] = {
76 MRVL_IFACE_NAME_ARG,
77 MRVL_CFG_ARG,
78 NULL
79};
80
81static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
82static struct pp2_hif *hifs[RTE_MAX_LCORE];
83static int used_bpools[PP2_NUM_PKT_PROC] = {
84 [0 ... PP2_NUM_PKT_PROC - 1] = MRVL_MUSDK_BPOOLS_RESERVED
85};
86
87static struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
88static int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
89static uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
90static int dummy_pool_id[PP2_NUM_PKT_PROC];
91struct pp2_bpool *dummy_pool[PP2_NUM_PKT_PROC] = {0};
92
93struct mrvl_ifnames {
94 const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
95 int idx;
96};
97
98
99
100
101
102
103
104
105
106
107
108
109struct mrvl_shadow_txq {
110 int head;
111 int tail;
112 u16 size;
113 u16 num_to_release;
114
115
116 struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE];
117};
118
119struct mrvl_rxq {
120 struct mrvl_priv *priv;
121 struct rte_mempool *mp;
122 int queue_id;
123 int port_id;
124 int cksum_enabled;
125 uint64_t bytes_recv;
126 uint64_t drop_mac;
127};
128
129struct mrvl_txq {
130 struct mrvl_priv *priv;
131 int queue_id;
132 int port_id;
133 uint64_t bytes_sent;
134 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE];
135 int tx_deferred_start;
136};
137
138static int mrvl_lcore_first;
139static int mrvl_lcore_last;
140static int mrvl_dev_num;
141
142static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num);
143static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio,
144 struct pp2_hif *hif, unsigned int core_id,
145 struct mrvl_shadow_txq *sq, int qid, int force);
146
147static uint16_t mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts,
148 uint16_t nb_pkts);
149static uint16_t mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts,
150 uint16_t nb_pkts);
151static int rte_pmd_mrvl_remove(struct rte_vdev_device *vdev);
152static void mrvl_deinit_pp2(void);
153static void mrvl_deinit_hifs(void);
154
155static int
156mrvl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
157 uint32_t index, uint32_t vmdq __rte_unused);
158static int
159mrvl_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
160static int
161mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
162static int mrvl_promiscuous_enable(struct rte_eth_dev *dev);
163static int mrvl_allmulticast_enable(struct rte_eth_dev *dev);
164static int
165mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf);
166
167#define MRVL_XSTATS_TBL_ENTRY(name) { \
168 #name, offsetof(struct pp2_ppio_statistics, name), \
169 sizeof(((struct pp2_ppio_statistics *)0)->name) \
170}
171
172
173static struct {
174 const char *name;
175 unsigned int offset;
176 unsigned int size;
177} mrvl_xstats_tbl[] = {
178 MRVL_XSTATS_TBL_ENTRY(rx_bytes),
179 MRVL_XSTATS_TBL_ENTRY(rx_packets),
180 MRVL_XSTATS_TBL_ENTRY(rx_unicast_packets),
181 MRVL_XSTATS_TBL_ENTRY(rx_errors),
182 MRVL_XSTATS_TBL_ENTRY(rx_fullq_dropped),
183 MRVL_XSTATS_TBL_ENTRY(rx_bm_dropped),
184 MRVL_XSTATS_TBL_ENTRY(rx_early_dropped),
185 MRVL_XSTATS_TBL_ENTRY(rx_fifo_dropped),
186 MRVL_XSTATS_TBL_ENTRY(rx_cls_dropped),
187 MRVL_XSTATS_TBL_ENTRY(tx_bytes),
188 MRVL_XSTATS_TBL_ENTRY(tx_packets),
189 MRVL_XSTATS_TBL_ENTRY(tx_unicast_packets),
190 MRVL_XSTATS_TBL_ENTRY(tx_errors)
191};
192
193static inline int
194mrvl_reserve_bit(int *bitmap, int max)
195{
196 int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
197
198 if (n >= max)
199 return -1;
200
201 *bitmap |= 1 << n;
202
203 return n;
204}
205
206static int
207mrvl_pp2_fixup_init(void)
208{
209 struct pp2_bpool_params bpool_params;
210 char name[15];
211 int err, i;
212
213 memset(dummy_pool, 0, sizeof(dummy_pool));
214 for (i = 0; i < pp2_get_num_inst(); i++) {
215 dummy_pool_id[i] = mrvl_reserve_bit(&used_bpools[i],
216 PP2_BPOOL_NUM_POOLS);
217 if (dummy_pool_id[i] < 0) {
218 MRVL_LOG(ERR, "Can't find free pool\n");
219 return -1;
220 }
221
222 memset(name, 0, sizeof(name));
223 snprintf(name, sizeof(name), "pool-%d:%d", i, dummy_pool_id[i]);
224 memset(&bpool_params, 0, sizeof(bpool_params));
225 bpool_params.match = name;
226 bpool_params.buff_len = MRVL_PKT_OFFS;
227 bpool_params.dummy_short_pool = 1;
228 err = pp2_bpool_init(&bpool_params, &dummy_pool[i]);
229 if (err != 0 || !dummy_pool[i]) {
230 MRVL_LOG(ERR, "BPool init failed!\n");
231 used_bpools[i] &= ~(1 << dummy_pool_id[i]);
232 return -1;
233 }
234 }
235
236 return 0;
237}
238
239
240
241
242
243
244
245static int
246mrvl_init_pp2(void)
247{
248 struct pp2_init_params init_params;
249 int err;
250
251 memset(&init_params, 0, sizeof(init_params));
252 init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
253 init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
254 init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
255 if (mrvl_cfg && mrvl_cfg->pp2_cfg.prs_udfs.num_udfs)
256 memcpy(&init_params.prs_udfs, &mrvl_cfg->pp2_cfg.prs_udfs,
257 sizeof(struct pp2_parse_udfs));
258 err = pp2_init(&init_params);
259 if (err != 0) {
260 MRVL_LOG(ERR, "PP2 init failed");
261 return -1;
262 }
263
264 err = mrvl_pp2_fixup_init();
265 if (err != 0) {
266 MRVL_LOG(ERR, "PP2 fixup init failed");
267 return -1;
268 }
269
270 return 0;
271}
272
273static void
274mrvl_pp2_fixup_deinit(void)
275{
276 int i;
277
278 for (i = 0; i < PP2_NUM_PKT_PROC; i++) {
279 if (!dummy_pool[i])
280 continue;
281 pp2_bpool_deinit(dummy_pool[i]);
282 used_bpools[i] &= ~(1 << dummy_pool_id[i]);
283 }
284}
285
286
287
288
289
290
291
292static void
293mrvl_deinit_pp2(void)
294{
295 mrvl_pp2_fixup_deinit();
296 pp2_deinit();
297}
298
299static inline void
300mrvl_fill_shadowq(struct mrvl_shadow_txq *sq, struct rte_mbuf *buf)
301{
302 sq->ent[sq->head].buff.cookie = (uint64_t)buf;
303 sq->ent[sq->head].buff.addr = buf ?
304 rte_mbuf_data_iova_default(buf) : 0;
305
306 sq->ent[sq->head].bpool =
307 (unlikely(!buf || buf->port >= RTE_MAX_ETHPORTS ||
308 buf->refcnt > 1)) ? NULL :
309 mrvl_port_to_bpool_lookup[buf->port];
310
311 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
312 sq->size++;
313}
314
315
316
317
318static void
319mrvl_deinit_hifs(void)
320{
321 int i;
322
323 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) {
324 if (hifs[i])
325 pp2_hif_deinit(hifs[i]);
326 }
327 used_hifs = MRVL_MUSDK_HIFS_RESERVED;
328 memset(hifs, 0, sizeof(hifs));
329}
330
331static inline void
332mrvl_fill_desc(struct pp2_ppio_desc *desc, struct rte_mbuf *buf)
333{
334 pp2_ppio_outq_desc_reset(desc);
335 pp2_ppio_outq_desc_set_phys_addr(desc, rte_pktmbuf_iova(buf));
336 pp2_ppio_outq_desc_set_pkt_offset(desc, 0);
337 pp2_ppio_outq_desc_set_pkt_len(desc, rte_pktmbuf_data_len(buf));
338}
339
340static inline int
341mrvl_get_bpool_size(int pp2_id, int pool_id)
342{
343 int i;
344 int size = 0;
345
346 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
347 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
348
349 return size;
350}
351
352static int
353mrvl_init_hif(int core_id)
354{
355 struct pp2_hif_params params;
356 char match[MRVL_MATCH_LEN];
357 int ret;
358
359 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
360 if (ret < 0) {
361 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id);
362 return ret;
363 }
364
365 snprintf(match, sizeof(match), "hif-%d", ret);
366 memset(¶ms, 0, sizeof(params));
367 params.match = match;
368 params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
369 ret = pp2_hif_init(¶ms, &hifs[core_id]);
370 if (ret) {
371 MRVL_LOG(ERR, "Failed to initialize hif %d", core_id);
372 return ret;
373 }
374
375 return 0;
376}
377
378static inline struct pp2_hif*
379mrvl_get_hif(struct mrvl_priv *priv, int core_id)
380{
381 int ret;
382
383 if (likely(hifs[core_id] != NULL))
384 return hifs[core_id];
385
386 rte_spinlock_lock(&priv->lock);
387
388 ret = mrvl_init_hif(core_id);
389 if (ret < 0) {
390 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id);
391 goto out;
392 }
393
394 if (core_id < mrvl_lcore_first)
395 mrvl_lcore_first = core_id;
396
397 if (core_id > mrvl_lcore_last)
398 mrvl_lcore_last = core_id;
399out:
400 rte_spinlock_unlock(&priv->lock);
401
402 return hifs[core_id];
403}
404
405
406
407
408
409
410
411static void
412mrvl_set_tx_function(struct rte_eth_dev *dev)
413{
414 struct mrvl_priv *priv = dev->data->dev_private;
415
416
417 if (priv->multiseg) {
418 RTE_LOG(INFO, PMD, "Using multi-segment tx callback\n");
419 dev->tx_pkt_burst = mrvl_tx_sg_pkt_burst;
420 } else {
421 RTE_LOG(INFO, PMD, "Using single-segment tx callback\n");
422 dev->tx_pkt_burst = mrvl_tx_pkt_burst;
423 }
424}
425
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427
428
429
430
431
432
433
434
435
436
437static int
438mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
439{
440 if (rss_conf->rss_key)
441 MRVL_LOG(WARNING, "Changing hash key is not supported");
442
443 if (rss_conf->rss_hf == 0) {
444 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
445 } else if (rss_conf->rss_hf & RTE_ETH_RSS_IPV4) {
446 priv->ppio_params.inqs_params.hash_type =
447 PP2_PPIO_HASH_T_2_TUPLE;
448 } else if (rss_conf->rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_TCP) {
449 priv->ppio_params.inqs_params.hash_type =
450 PP2_PPIO_HASH_T_5_TUPLE;
451 priv->rss_hf_tcp = 1;
452 } else if (rss_conf->rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_UDP) {
453 priv->ppio_params.inqs_params.hash_type =
454 PP2_PPIO_HASH_T_5_TUPLE;
455 priv->rss_hf_tcp = 0;
456 } else {
457 return -EINVAL;
458 }
459
460 return 0;
461}
462
463
464
465
466
467
468
469
470
471
472
473
474
475static int
476mrvl_dev_configure(struct rte_eth_dev *dev)
477{
478 struct mrvl_priv *priv = dev->data->dev_private;
479 int ret;
480
481 if (priv->ppio) {
482 MRVL_LOG(INFO, "Device reconfiguration is not supported");
483 return -EINVAL;
484 }
485
486 if (dev->data->dev_conf.rxmode.mq_mode != RTE_ETH_MQ_RX_NONE &&
487 dev->data->dev_conf.rxmode.mq_mode != RTE_ETH_MQ_RX_RSS) {
488 MRVL_LOG(INFO, "Unsupported rx multi queue mode %d",
489 dev->data->dev_conf.rxmode.mq_mode);
490 return -EINVAL;
491 }
492
493 if (dev->data->dev_conf.rxmode.split_hdr_size) {
494 MRVL_LOG(INFO, "Split headers not supported");
495 return -EINVAL;
496 }
497
498 if (dev->data->dev_conf.rxmode.mtu > priv->max_mtu) {
499 MRVL_LOG(ERR, "MTU %u is larger than max_mtu %u\n",
500 dev->data->dev_conf.rxmode.mtu,
501 priv->max_mtu);
502 return -EINVAL;
503 }
504
505 if (dev->data->dev_conf.txmode.offloads & RTE_ETH_TX_OFFLOAD_MULTI_SEGS)
506 priv->multiseg = 1;
507
508 ret = mrvl_configure_rxqs(priv, dev->data->port_id,
509 dev->data->nb_rx_queues);
510 if (ret < 0)
511 return ret;
512
513 ret = mrvl_configure_txqs(priv, dev->data->port_id,
514 dev->data->nb_tx_queues);
515 if (ret < 0)
516 return ret;
517
518 priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
519 priv->ppio_params.maintain_stats = 1;
520 priv->nb_rx_queues = dev->data->nb_rx_queues;
521
522 ret = mrvl_tm_init(dev);
523 if (ret < 0)
524 return ret;
525
526 if (dev->data->nb_rx_queues == 1 &&
527 dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) {
528 MRVL_LOG(WARNING, "Disabling hash for 1 rx queue");
529 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
530 priv->configured = 1;
531 return 0;
532 }
533
534 ret = mrvl_configure_rss(priv,
535 &dev->data->dev_conf.rx_adv_conf.rss_conf);
536 if (ret < 0)
537 return ret;
538
539 priv->configured = 1;
540
541 return 0;
542}
543
544
545
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547
548
549
550
551
552
553
554
555
556
557
558static int
559mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
560{
561 struct mrvl_priv *priv = dev->data->dev_private;
562 uint16_t mru;
563 uint16_t mbuf_data_size = 0;
564 int ret;
565
566 mru = MRVL_PP2_MTU_TO_MRU(mtu);
567
568
569
570
571 mbuf_data_size = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
572
573
574
575
576
577
578
579 if (mru - RTE_ETHER_CRC_LEN + MRVL_PKT_OFFS > mbuf_data_size) {
580 mru = mbuf_data_size + RTE_ETHER_CRC_LEN - MRVL_PKT_OFFS;
581 mtu = MRVL_PP2_MRU_TO_MTU(mru);
582 MRVL_LOG(WARNING, "MTU too big, max MTU possible limitted "
583 "by current mbuf size: %u. Set MTU to %u, MRU to %u",
584 mbuf_data_size, mtu, mru);
585 }
586
587 if (mtu < RTE_ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX) {
588 MRVL_LOG(ERR, "Invalid MTU [%u] or MRU [%u]", mtu, mru);
589 return -EINVAL;
590 }
591
592 if (!priv->ppio)
593 return 0;
594
595 ret = pp2_ppio_set_mru(priv->ppio, mru);
596 if (ret) {
597 MRVL_LOG(ERR, "Failed to change MRU");
598 return ret;
599 }
600
601 ret = pp2_ppio_set_mtu(priv->ppio, mtu);
602 if (ret) {
603 MRVL_LOG(ERR, "Failed to change MTU");
604 return ret;
605 }
606
607 return 0;
608}
609
610
611
612
613
614
615
616
617
618
619static int
620mrvl_dev_set_link_up(struct rte_eth_dev *dev)
621{
622 struct mrvl_priv *priv = dev->data->dev_private;
623 int ret;
624
625 if (!priv->ppio) {
626 dev->data->dev_link.link_status = RTE_ETH_LINK_UP;
627 return 0;
628 }
629
630 ret = pp2_ppio_enable(priv->ppio);
631 if (ret)
632 return ret;
633
634
635
636
637
638
639
640
641 ret = mrvl_mtu_set(dev, dev->data->mtu);
642 if (ret) {
643 pp2_ppio_disable(priv->ppio);
644 return ret;
645 }
646
647 dev->data->dev_link.link_status = RTE_ETH_LINK_UP;
648 return 0;
649}
650
651
652
653
654
655
656
657
658
659
660static int
661mrvl_dev_set_link_down(struct rte_eth_dev *dev)
662{
663 struct mrvl_priv *priv = dev->data->dev_private;
664 int ret;
665
666 if (!priv->ppio) {
667 dev->data->dev_link.link_status = RTE_ETH_LINK_DOWN;
668 return 0;
669 }
670 ret = pp2_ppio_disable(priv->ppio);
671 if (ret)
672 return ret;
673
674 dev->data->dev_link.link_status = RTE_ETH_LINK_DOWN;
675 return 0;
676}
677
678
679
680
681
682
683
684
685
686
687
688
689static int
690mrvl_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id)
691{
692 struct mrvl_priv *priv = dev->data->dev_private;
693 int ret;
694
695 if (!priv)
696 return -EPERM;
697
698
699 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 1);
700 if (ret) {
701 MRVL_LOG(ERR, "Failed to start txq %d", queue_id);
702 return ret;
703 }
704
705 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
706
707 return 0;
708}
709
710
711
712
713
714
715
716
717
718
719
720
721static int
722mrvl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id)
723{
724 struct mrvl_priv *priv = dev->data->dev_private;
725 int ret;
726
727 if (!priv->ppio)
728 return -EPERM;
729
730
731 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 0);
732 if (ret) {
733 MRVL_LOG(ERR, "Failed to stop txq %d", queue_id);
734 return ret;
735 }
736
737 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
738
739 return 0;
740}
741
742
743
744
745
746
747
748
749
750
751
752
753static int mrvl_populate_vlan_table(struct rte_eth_dev *dev, int on)
754{
755 uint32_t j;
756 int ret;
757 struct rte_vlan_filter_conf *vfc;
758
759 vfc = &dev->data->vlan_filter_conf;
760 for (j = 0; j < RTE_DIM(vfc->ids); j++) {
761 uint64_t vlan;
762 uint64_t vbit;
763 uint64_t ids = vfc->ids[j];
764
765 if (ids == 0)
766 continue;
767
768 while (ids) {
769 vlan = 64 * j;
770
771 vbit = ~ids & (ids - 1);
772
773 ids ^= (ids ^ (ids - 1)) ^ vbit;
774 for (; vbit; vlan++)
775 vbit >>= 1;
776 ret = mrvl_vlan_filter_set(dev, vlan, on);
777 if (ret) {
778 MRVL_LOG(ERR, "Failed to setup VLAN filter\n");
779 return ret;
780 }
781 }
782 }
783
784 return 0;
785}
786
787
788
789
790
791
792
793
794
795
796static int
797mrvl_dev_start(struct rte_eth_dev *dev)
798{
799 struct mrvl_priv *priv = dev->data->dev_private;
800 char match[MRVL_MATCH_LEN];
801 int ret = 0, i, def_init_size;
802 struct rte_ether_addr *mac_addr;
803
804 if (priv->ppio)
805 return mrvl_dev_set_link_up(dev);
806
807 snprintf(match, sizeof(match), "ppio-%d:%d",
808 priv->pp_id, priv->ppio_id);
809 priv->ppio_params.match = match;
810 priv->ppio_params.eth_start_hdr = PP2_PPIO_HDR_ETH;
811 priv->forward_bad_frames = 0;
812 priv->fill_bpool_buffs = MRVL_BURST_SIZE;
813
814 if (mrvl_cfg) {
815 priv->ppio_params.eth_start_hdr =
816 mrvl_cfg->port[dev->data->port_id].eth_start_hdr;
817 priv->forward_bad_frames =
818 mrvl_cfg->port[dev->data->port_id].forward_bad_frames;
819 priv->fill_bpool_buffs =
820 mrvl_cfg->port[dev->data->port_id].fill_bpool_buffs;
821 }
822
823
824
825
826
827
828
829 priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
830
831
832
833
834 def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2;
835 if (priv->bpool_init_size < def_init_size) {
836 int buffs_to_add = def_init_size - priv->bpool_init_size;
837
838 priv->bpool_init_size += buffs_to_add;
839 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add);
840 if (ret)
841 MRVL_LOG(ERR, "Failed to add buffers to bpool");
842 }
843
844
845
846
847
848
849
850
851 priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) +
852 priv->bpool_min_size;
853
854 ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
855 if (ret) {
856 MRVL_LOG(ERR, "Failed to init ppio");
857 return ret;
858 }
859
860
861
862
863
864
865
866 if (!priv->uc_mc_flushed) {
867 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
868 if (ret) {
869 MRVL_LOG(ERR,
870 "Failed to flush uc/mc filter list");
871 goto out;
872 }
873 priv->uc_mc_flushed = 1;
874 }
875
876 ret = mrvl_mtu_set(dev, dev->data->mtu);
877 if (ret)
878 MRVL_LOG(ERR, "Failed to set MTU to %d", dev->data->mtu);
879
880 if (!rte_is_zero_ether_addr(&dev->data->mac_addrs[0]))
881 mrvl_mac_addr_set(dev, &dev->data->mac_addrs[0]);
882
883 for (i = 1; i < MRVL_MAC_ADDRS_MAX; i++) {
884 mac_addr = &dev->data->mac_addrs[i];
885
886
887 if (rte_is_zero_ether_addr(mac_addr))
888 continue;
889
890 mrvl_mac_addr_add(dev, mac_addr, i, 0);
891 }
892
893 if (dev->data->all_multicast == 1)
894 mrvl_allmulticast_enable(dev);
895
896 if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
897 ret = mrvl_populate_vlan_table(dev, 1);
898 if (ret) {
899 MRVL_LOG(ERR, "Failed to populate VLAN table");
900 goto out;
901 }
902 }
903
904
905 if (mrvl_cfg &&
906 mrvl_cfg->port[dev->data->port_id].use_qos_global_defaults == 0) {
907 ret = mrvl_start_qos_mapping(priv);
908 if (ret) {
909 MRVL_LOG(ERR, "Failed to setup QoS mapping");
910 goto out;
911 }
912 }
913
914 ret = pp2_ppio_set_loopback(priv->ppio, dev->data->dev_conf.lpbk_mode);
915 if (ret) {
916 MRVL_LOG(ERR, "Failed to set loopback");
917 goto out;
918 }
919
920 if (dev->data->promiscuous == 1)
921 mrvl_promiscuous_enable(dev);
922
923 if (priv->flow_ctrl) {
924 ret = mrvl_flow_ctrl_set(dev, &priv->fc_conf);
925 if (ret) {
926 MRVL_LOG(ERR, "Failed to configure flow control");
927 goto out;
928 }
929 priv->flow_ctrl = 0;
930 }
931
932 if (dev->data->dev_link.link_status == RTE_ETH_LINK_UP) {
933 ret = mrvl_dev_set_link_up(dev);
934 if (ret) {
935 MRVL_LOG(ERR, "Failed to set link up");
936 dev->data->dev_link.link_status = RTE_ETH_LINK_DOWN;
937 goto out;
938 }
939 }
940
941
942 for (i = 0; i < dev->data->nb_tx_queues; i++) {
943 struct mrvl_txq *txq = dev->data->tx_queues[i];
944
945 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED;
946
947 if (!txq->tx_deferred_start)
948 continue;
949
950
951
952
953
954 ret = mrvl_tx_queue_stop(dev, i);
955 if (ret)
956 goto out;
957 }
958
959 mrvl_flow_init(dev);
960 mrvl_mtr_init(dev);
961 mrvl_set_tx_function(dev);
962
963 return 0;
964out:
965 MRVL_LOG(ERR, "Failed to start device");
966 pp2_ppio_deinit(priv->ppio);
967 return ret;
968}
969
970
971
972
973
974
975
976static void
977mrvl_flush_rx_queues(struct rte_eth_dev *dev)
978{
979 int i;
980
981 MRVL_LOG(INFO, "Flushing rx queues");
982 for (i = 0; i < dev->data->nb_rx_queues; i++) {
983 int ret, num;
984
985 do {
986 struct mrvl_rxq *q = dev->data->rx_queues[i];
987 struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
988
989 num = MRVL_PP2_RXD_MAX;
990 ret = pp2_ppio_recv(q->priv->ppio,
991 q->priv->rxq_map[q->queue_id].tc,
992 q->priv->rxq_map[q->queue_id].inq,
993 descs, (uint16_t *)&num);
994 } while (ret == 0 && num);
995 }
996}
997
998
999
1000
1001
1002
1003
1004static void
1005mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
1006{
1007 int i, j;
1008 struct mrvl_txq *txq;
1009
1010 MRVL_LOG(INFO, "Flushing tx shadow queues");
1011 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1012 txq = (struct mrvl_txq *)dev->data->tx_queues[i];
1013
1014 for (j = 0; j < RTE_MAX_LCORE; j++) {
1015 struct mrvl_shadow_txq *sq;
1016
1017 if (!hifs[j])
1018 continue;
1019
1020 sq = &txq->shadow_txqs[j];
1021 mrvl_free_sent_buffers(txq->priv->ppio,
1022 hifs[j], j, sq, txq->queue_id, 1);
1023 while (sq->tail != sq->head) {
1024 uint64_t addr = cookie_addr_high |
1025 sq->ent[sq->tail].buff.cookie;
1026 rte_pktmbuf_free(
1027 (struct rte_mbuf *)addr);
1028 sq->tail = (sq->tail + 1) &
1029 MRVL_PP2_TX_SHADOWQ_MASK;
1030 }
1031 memset(sq, 0, sizeof(*sq));
1032 }
1033 }
1034}
1035
1036
1037
1038
1039
1040
1041
1042static void
1043mrvl_flush_bpool(struct rte_eth_dev *dev)
1044{
1045 struct mrvl_priv *priv = dev->data->dev_private;
1046 struct pp2_hif *hif;
1047 uint32_t num;
1048 int ret;
1049 unsigned int core_id = rte_lcore_id();
1050
1051 if (core_id == LCORE_ID_ANY)
1052 core_id = rte_get_main_lcore();
1053
1054 hif = mrvl_get_hif(priv, core_id);
1055
1056 ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
1057 if (ret) {
1058 MRVL_LOG(ERR, "Failed to get bpool buffers number");
1059 return;
1060 }
1061
1062 while (num--) {
1063 struct pp2_buff_inf inf;
1064 uint64_t addr;
1065
1066 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf);
1067 if (ret)
1068 break;
1069
1070 addr = cookie_addr_high | inf.cookie;
1071 rte_pktmbuf_free((struct rte_mbuf *)addr);
1072 }
1073}
1074
1075
1076
1077
1078
1079
1080
1081static int
1082mrvl_dev_stop(struct rte_eth_dev *dev)
1083{
1084 return mrvl_dev_set_link_down(dev);
1085}
1086
1087
1088
1089
1090
1091
1092
1093static int
1094mrvl_dev_close(struct rte_eth_dev *dev)
1095{
1096 struct mrvl_priv *priv = dev->data->dev_private;
1097 size_t i;
1098
1099 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1100 return 0;
1101
1102 mrvl_flush_rx_queues(dev);
1103 mrvl_flush_tx_shadow_queues(dev);
1104 mrvl_flow_deinit(dev);
1105 mrvl_mtr_deinit(dev);
1106
1107 for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
1108 struct pp2_ppio_tc_params *tc_params =
1109 &priv->ppio_params.inqs_params.tcs_params[i];
1110
1111 if (tc_params->inqs_params) {
1112 rte_free(tc_params->inqs_params);
1113 tc_params->inqs_params = NULL;
1114 }
1115 }
1116
1117 if (priv->cls_tbl) {
1118 pp2_cls_tbl_deinit(priv->cls_tbl);
1119 priv->cls_tbl = NULL;
1120 }
1121
1122 if (priv->qos_tbl) {
1123 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
1124 priv->qos_tbl = NULL;
1125 }
1126
1127 mrvl_flush_bpool(dev);
1128 mrvl_tm_deinit(dev);
1129
1130 if (priv->ppio) {
1131 pp2_ppio_deinit(priv->ppio);
1132 priv->ppio = NULL;
1133 }
1134
1135
1136 if (priv->default_policer) {
1137 pp2_cls_plcr_deinit(priv->default_policer);
1138 priv->default_policer = NULL;
1139 }
1140
1141
1142 if (priv->bpool) {
1143 pp2_bpool_deinit(priv->bpool);
1144 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
1145 priv->bpool = NULL;
1146 }
1147
1148 mrvl_dev_num--;
1149
1150 if (mrvl_dev_num == 0) {
1151 MRVL_LOG(INFO, "Perform MUSDK deinit");
1152 mrvl_deinit_hifs();
1153 mrvl_deinit_pp2();
1154 rte_mvep_deinit(MVEP_MOD_T_PP2);
1155 }
1156
1157 return 0;
1158}
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171static int
1172mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
1173{
1174
1175
1176
1177
1178 struct mrvl_priv *priv = dev->data->dev_private;
1179 struct ethtool_cmd edata;
1180 struct ifreq req;
1181 int ret, fd, link_up;
1182
1183 if (!priv->ppio)
1184 return -EPERM;
1185
1186 edata.cmd = ETHTOOL_GSET;
1187
1188 strcpy(req.ifr_name, dev->data->name);
1189 req.ifr_data = (void *)&edata;
1190
1191 fd = socket(AF_INET, SOCK_DGRAM, 0);
1192 if (fd == -1)
1193 return -EFAULT;
1194
1195 ret = ioctl(fd, SIOCETHTOOL, &req);
1196 if (ret == -1) {
1197 close(fd);
1198 return -EFAULT;
1199 }
1200
1201 close(fd);
1202
1203 switch (ethtool_cmd_speed(&edata)) {
1204 case SPEED_10:
1205 dev->data->dev_link.link_speed = RTE_ETH_SPEED_NUM_10M;
1206 break;
1207 case SPEED_100:
1208 dev->data->dev_link.link_speed = RTE_ETH_SPEED_NUM_100M;
1209 break;
1210 case SPEED_1000:
1211 dev->data->dev_link.link_speed = RTE_ETH_SPEED_NUM_1G;
1212 break;
1213 case SPEED_2500:
1214 dev->data->dev_link.link_speed = RTE_ETH_SPEED_NUM_2_5G;
1215 break;
1216 case SPEED_10000:
1217 dev->data->dev_link.link_speed = RTE_ETH_SPEED_NUM_10G;
1218 break;
1219 default:
1220 dev->data->dev_link.link_speed = RTE_ETH_SPEED_NUM_NONE;
1221 }
1222
1223 dev->data->dev_link.link_duplex = edata.duplex ? RTE_ETH_LINK_FULL_DUPLEX :
1224 RTE_ETH_LINK_HALF_DUPLEX;
1225 dev->data->dev_link.link_autoneg = edata.autoneg ? RTE_ETH_LINK_AUTONEG :
1226 RTE_ETH_LINK_FIXED;
1227 pp2_ppio_get_link_state(priv->ppio, &link_up);
1228 dev->data->dev_link.link_status = link_up ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
1229
1230 return 0;
1231}
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242static int
1243mrvl_promiscuous_enable(struct rte_eth_dev *dev)
1244{
1245 struct mrvl_priv *priv = dev->data->dev_private;
1246 int ret;
1247
1248 if (priv->isolated)
1249 return -ENOTSUP;
1250
1251 if (!priv->ppio)
1252 return 0;
1253
1254 ret = pp2_ppio_set_promisc(priv->ppio, 1);
1255 if (ret) {
1256 MRVL_LOG(ERR, "Failed to enable promiscuous mode");
1257 return -EAGAIN;
1258 }
1259
1260 return 0;
1261}
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272static int
1273mrvl_allmulticast_enable(struct rte_eth_dev *dev)
1274{
1275 struct mrvl_priv *priv = dev->data->dev_private;
1276 int ret;
1277
1278 if (priv->isolated)
1279 return -ENOTSUP;
1280
1281 if (!priv->ppio)
1282 return 0;
1283
1284 ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
1285 if (ret) {
1286 MRVL_LOG(ERR, "Failed enable all-multicast mode");
1287 return -EAGAIN;
1288 }
1289
1290 return 0;
1291}
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302static int
1303mrvl_promiscuous_disable(struct rte_eth_dev *dev)
1304{
1305 struct mrvl_priv *priv = dev->data->dev_private;
1306 int ret;
1307
1308 if (priv->isolated)
1309 return -ENOTSUP;
1310
1311 if (!priv->ppio)
1312 return 0;
1313
1314 ret = pp2_ppio_set_promisc(priv->ppio, 0);
1315 if (ret) {
1316 MRVL_LOG(ERR, "Failed to disable promiscuous mode");
1317 return -EAGAIN;
1318 }
1319
1320 return 0;
1321}
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332static int
1333mrvl_allmulticast_disable(struct rte_eth_dev *dev)
1334{
1335 struct mrvl_priv *priv = dev->data->dev_private;
1336 int ret;
1337
1338 if (priv->isolated)
1339 return -ENOTSUP;
1340
1341 if (!priv->ppio)
1342 return 0;
1343
1344 ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
1345 if (ret) {
1346 MRVL_LOG(ERR, "Failed to disable all-multicast mode");
1347 return -EAGAIN;
1348 }
1349
1350 return 0;
1351}
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361static void
1362mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
1363{
1364 struct mrvl_priv *priv = dev->data->dev_private;
1365 char buf[RTE_ETHER_ADDR_FMT_SIZE];
1366 int ret;
1367
1368 if (priv->isolated)
1369 return;
1370
1371 if (!priv->ppio)
1372 return;
1373
1374 ret = pp2_ppio_remove_mac_addr(priv->ppio,
1375 dev->data->mac_addrs[index].addr_bytes);
1376 if (ret) {
1377 rte_ether_format_addr(buf, sizeof(buf),
1378 &dev->data->mac_addrs[index]);
1379 MRVL_LOG(ERR, "Failed to remove mac %s", buf);
1380 }
1381}
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398static int
1399mrvl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1400 uint32_t index, uint32_t vmdq __rte_unused)
1401{
1402 struct mrvl_priv *priv = dev->data->dev_private;
1403 char buf[RTE_ETHER_ADDR_FMT_SIZE];
1404 int ret;
1405
1406 if (priv->isolated)
1407 return -ENOTSUP;
1408
1409 if (!priv->ppio)
1410 return 0;
1411
1412 if (index == 0)
1413
1414 return -1;
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429 ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
1430 if (ret) {
1431 rte_ether_format_addr(buf, sizeof(buf), mac_addr);
1432 MRVL_LOG(ERR, "Failed to add mac %s", buf);
1433 return -1;
1434 }
1435
1436 return 0;
1437}
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450static int
1451mrvl_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
1452{
1453 struct mrvl_priv *priv = dev->data->dev_private;
1454 int ret;
1455
1456 if (priv->isolated)
1457 return -ENOTSUP;
1458
1459 if (!priv->ppio)
1460 return 0;
1461
1462 ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
1463 if (ret) {
1464 char buf[RTE_ETHER_ADDR_FMT_SIZE];
1465 rte_ether_format_addr(buf, sizeof(buf), mac_addr);
1466 MRVL_LOG(ERR, "Failed to set mac to %s", buf);
1467 }
1468
1469 return ret;
1470}
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483static int
1484mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1485{
1486 struct mrvl_priv *priv = dev->data->dev_private;
1487 struct pp2_ppio_statistics ppio_stats;
1488 uint64_t drop_mac = 0;
1489 unsigned int i, idx, ret;
1490
1491 if (!priv->ppio)
1492 return -EPERM;
1493
1494 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1495 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1496 struct pp2_ppio_inq_statistics rx_stats;
1497
1498 if (!rxq)
1499 continue;
1500
1501 idx = rxq->queue_id;
1502 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1503 MRVL_LOG(ERR,
1504 "rx queue %d stats out of range (0 - %d)",
1505 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1506 continue;
1507 }
1508
1509 ret = pp2_ppio_inq_get_statistics(priv->ppio,
1510 priv->rxq_map[idx].tc,
1511 priv->rxq_map[idx].inq,
1512 &rx_stats, 0);
1513 if (unlikely(ret)) {
1514 MRVL_LOG(ERR,
1515 "Failed to update rx queue %d stats", idx);
1516 break;
1517 }
1518
1519 stats->q_ibytes[idx] = rxq->bytes_recv;
1520 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac;
1521 stats->q_errors[idx] = rx_stats.drop_early +
1522 rx_stats.drop_fullq +
1523 rx_stats.drop_bm +
1524 rxq->drop_mac;
1525 stats->ibytes += rxq->bytes_recv;
1526 drop_mac += rxq->drop_mac;
1527 }
1528
1529 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1530 struct mrvl_txq *txq = dev->data->tx_queues[i];
1531 struct pp2_ppio_outq_statistics tx_stats;
1532
1533 if (!txq)
1534 continue;
1535
1536 idx = txq->queue_id;
1537 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1538 MRVL_LOG(ERR,
1539 "tx queue %d stats out of range (0 - %d)",
1540 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1541 }
1542
1543 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx,
1544 &tx_stats, 0);
1545 if (unlikely(ret)) {
1546 MRVL_LOG(ERR,
1547 "Failed to update tx queue %d stats", idx);
1548 break;
1549 }
1550
1551 stats->q_opackets[idx] = tx_stats.deq_desc;
1552 stats->q_obytes[idx] = txq->bytes_sent;
1553 stats->obytes += txq->bytes_sent;
1554 }
1555
1556 ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1557 if (unlikely(ret)) {
1558 MRVL_LOG(ERR, "Failed to update port statistics");
1559 return ret;
1560 }
1561
1562 stats->ipackets += ppio_stats.rx_packets - drop_mac;
1563 stats->opackets += ppio_stats.tx_packets;
1564 stats->imissed += ppio_stats.rx_fullq_dropped +
1565 ppio_stats.rx_bm_dropped +
1566 ppio_stats.rx_early_dropped +
1567 ppio_stats.rx_fifo_dropped +
1568 ppio_stats.rx_cls_dropped;
1569 stats->ierrors = drop_mac;
1570
1571 return 0;
1572}
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583static int
1584mrvl_stats_reset(struct rte_eth_dev *dev)
1585{
1586 struct mrvl_priv *priv = dev->data->dev_private;
1587 int i;
1588
1589 if (!priv->ppio)
1590 return 0;
1591
1592 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1593 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1594
1595 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc,
1596 priv->rxq_map[i].inq, NULL, 1);
1597 rxq->bytes_recv = 0;
1598 rxq->drop_mac = 0;
1599 }
1600
1601 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1602 struct mrvl_txq *txq = dev->data->tx_queues[i];
1603
1604 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1);
1605 txq->bytes_sent = 0;
1606 }
1607
1608 return pp2_ppio_get_statistics(priv->ppio, NULL, 1);
1609}
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623static int
1624mrvl_xstats_get(struct rte_eth_dev *dev,
1625 struct rte_eth_xstat *stats, unsigned int n)
1626{
1627 struct mrvl_priv *priv = dev->data->dev_private;
1628 struct pp2_ppio_statistics ppio_stats;
1629 unsigned int i;
1630
1631 if (!stats)
1632 return 0;
1633
1634 pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1635 for (i = 0; i < n && i < RTE_DIM(mrvl_xstats_tbl); i++) {
1636 uint64_t val;
1637
1638 if (mrvl_xstats_tbl[i].size == sizeof(uint32_t))
1639 val = *(uint32_t *)((uint8_t *)&ppio_stats +
1640 mrvl_xstats_tbl[i].offset);
1641 else if (mrvl_xstats_tbl[i].size == sizeof(uint64_t))
1642 val = *(uint64_t *)((uint8_t *)&ppio_stats +
1643 mrvl_xstats_tbl[i].offset);
1644 else
1645 return -EINVAL;
1646
1647 stats[i].id = i;
1648 stats[i].value = val;
1649 }
1650
1651 return n;
1652}
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663static int
1664mrvl_xstats_reset(struct rte_eth_dev *dev)
1665{
1666 return mrvl_stats_reset(dev);
1667}
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681static int
1682mrvl_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
1683 struct rte_eth_xstat_name *xstats_names,
1684 unsigned int size)
1685{
1686 unsigned int i;
1687
1688 if (!xstats_names)
1689 return RTE_DIM(mrvl_xstats_tbl);
1690
1691 for (i = 0; i < size && i < RTE_DIM(mrvl_xstats_tbl); i++)
1692 strlcpy(xstats_names[i].name, mrvl_xstats_tbl[i].name,
1693 RTE_ETH_XSTATS_NAME_SIZE);
1694
1695 return size;
1696}
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706static int
1707mrvl_dev_infos_get(struct rte_eth_dev *dev,
1708 struct rte_eth_dev_info *info)
1709{
1710 struct mrvl_priv *priv = dev->data->dev_private;
1711
1712 info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
1713
1714 info->speed_capa = RTE_ETH_LINK_SPEED_10M |
1715 RTE_ETH_LINK_SPEED_100M |
1716 RTE_ETH_LINK_SPEED_1G |
1717 RTE_ETH_LINK_SPEED_2_5G |
1718 RTE_ETH_LINK_SPEED_10G;
1719
1720 info->max_rx_queues = MRVL_PP2_RXQ_MAX;
1721 info->max_tx_queues = MRVL_PP2_TXQ_MAX;
1722 info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
1723
1724 info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
1725 info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
1726 info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
1727
1728 info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
1729 info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
1730 info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
1731
1732 info->rx_offload_capa = MRVL_RX_OFFLOADS;
1733 info->rx_queue_offload_capa = MRVL_RX_OFFLOADS;
1734
1735 info->tx_offload_capa = MRVL_TX_OFFLOADS;
1736 info->tx_queue_offload_capa = MRVL_TX_OFFLOADS;
1737
1738 info->flow_type_rss_offloads = RTE_ETH_RSS_IPV4 |
1739 RTE_ETH_RSS_NONFRAG_IPV4_TCP |
1740 RTE_ETH_RSS_NONFRAG_IPV4_UDP;
1741
1742
1743 info->default_rxconf.rx_drop_en = 1;
1744
1745 info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
1746 info->max_mtu = priv->max_mtu;
1747
1748 return 0;
1749}
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760static const uint32_t *
1761mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1762{
1763 static const uint32_t ptypes[] = {
1764 RTE_PTYPE_L2_ETHER,
1765 RTE_PTYPE_L2_ETHER_VLAN,
1766 RTE_PTYPE_L2_ETHER_QINQ,
1767 RTE_PTYPE_L3_IPV4,
1768 RTE_PTYPE_L3_IPV4_EXT,
1769 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1770 RTE_PTYPE_L3_IPV6,
1771 RTE_PTYPE_L3_IPV6_EXT,
1772 RTE_PTYPE_L2_ETHER_ARP,
1773 RTE_PTYPE_L4_TCP,
1774 RTE_PTYPE_L4_UDP
1775 };
1776
1777 return ptypes;
1778}
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
1791 struct rte_eth_rxq_info *qinfo)
1792{
1793 struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
1794 struct mrvl_priv *priv = dev->data->dev_private;
1795 int inq = priv->rxq_map[rx_queue_id].inq;
1796 int tc = priv->rxq_map[rx_queue_id].tc;
1797 struct pp2_ppio_tc_params *tc_params =
1798 &priv->ppio_params.inqs_params.tcs_params[tc];
1799
1800 qinfo->mp = q->mp;
1801 qinfo->nb_desc = tc_params->inqs_params[inq].size;
1802}
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
1815 struct rte_eth_txq_info *qinfo)
1816{
1817 struct mrvl_priv *priv = dev->data->dev_private;
1818 struct mrvl_txq *txq = dev->data->tx_queues[tx_queue_id];
1819
1820 qinfo->nb_desc =
1821 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
1822 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1823}
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838static int
1839mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1840{
1841 struct mrvl_priv *priv = dev->data->dev_private;
1842
1843 if (priv->isolated)
1844 return -ENOTSUP;
1845
1846 if (!priv->ppio)
1847 return 0;
1848
1849 return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
1850 pp2_ppio_remove_vlan(priv->ppio, vlan_id);
1851}
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864static int mrvl_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1865{
1866 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1867 int ret;
1868
1869 if (mask & RTE_ETH_VLAN_STRIP_MASK) {
1870 MRVL_LOG(ERR, "VLAN stripping is not supported\n");
1871 return -ENOTSUP;
1872 }
1873
1874 if (mask & RTE_ETH_VLAN_FILTER_MASK) {
1875 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
1876 ret = mrvl_populate_vlan_table(dev, 1);
1877 else
1878 ret = mrvl_populate_vlan_table(dev, 0);
1879
1880 if (ret)
1881 return ret;
1882 }
1883
1884 if (mask & RTE_ETH_VLAN_EXTEND_MASK) {
1885 MRVL_LOG(ERR, "Extend VLAN not supported\n");
1886 return -ENOTSUP;
1887 }
1888
1889 return 0;
1890}
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903static int
1904mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
1905{
1906 struct buff_release_entry entries[num];
1907 struct rte_mbuf *mbufs[num];
1908 int i, ret;
1909 unsigned int core_id;
1910 struct pp2_hif *hif;
1911 struct pp2_bpool *bpool;
1912
1913 core_id = rte_lcore_id();
1914 if (core_id == LCORE_ID_ANY)
1915 core_id = rte_get_main_lcore();
1916
1917 hif = mrvl_get_hif(rxq->priv, core_id);
1918 if (!hif)
1919 return -1;
1920
1921 bpool = rxq->priv->bpool;
1922
1923 ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
1924 if (ret)
1925 return ret;
1926
1927 if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
1928 cookie_addr_high =
1929 (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
1930
1931 for (i = 0; i < num; i++) {
1932 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
1933 != cookie_addr_high) {
1934 MRVL_LOG(ERR,
1935 "mbuf virtual addr high is out of range "
1936 "0x%x instead of 0x%x\n",
1937 (uint32_t)((uint64_t)mbufs[i] >> 32),
1938 (uint32_t)(cookie_addr_high >> 32));
1939 goto out;
1940 }
1941
1942 entries[i].buff.addr =
1943 rte_mbuf_data_iova_default(mbufs[i]);
1944 entries[i].buff.cookie = (uintptr_t)mbufs[i];
1945 entries[i].bpool = bpool;
1946 }
1947
1948 pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
1949 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
1950
1951 if (i != num)
1952 goto out;
1953
1954 return 0;
1955out:
1956 for (; i < num; i++)
1957 rte_pktmbuf_free(mbufs[i]);
1958
1959 return -1;
1960}
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981static int
1982mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1983 unsigned int socket,
1984 const struct rte_eth_rxconf *conf,
1985 struct rte_mempool *mp)
1986{
1987 struct mrvl_priv *priv = dev->data->dev_private;
1988 struct mrvl_rxq *rxq;
1989 uint32_t frame_size, buf_size = rte_pktmbuf_data_room_size(mp);
1990 uint32_t max_rx_pktlen = dev->data->mtu + RTE_ETHER_HDR_LEN;
1991 int ret, tc, inq;
1992 uint64_t offloads;
1993
1994 offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads;
1995
1996 if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
1997
1998
1999
2000 MRVL_LOG(ERR, "Unknown TC mapping for queue %hu eth%hhu",
2001 idx, priv->ppio_id);
2002 return -EFAULT;
2003 }
2004
2005 frame_size = buf_size - RTE_PKTMBUF_HEADROOM - MRVL_PKT_EFFEC_OFFS;
2006 if (frame_size < max_rx_pktlen) {
2007 MRVL_LOG(WARNING,
2008 "Mbuf size must be increased to %u bytes to hold up "
2009 "to %u bytes of data.",
2010 max_rx_pktlen + buf_size - frame_size,
2011 max_rx_pktlen);
2012 dev->data->mtu = frame_size - RTE_ETHER_HDR_LEN;
2013 MRVL_LOG(INFO, "Setting MTU to %u", dev->data->mtu);
2014 }
2015
2016 if (dev->data->rx_queues[idx]) {
2017 rte_free(dev->data->rx_queues[idx]);
2018 dev->data->rx_queues[idx] = NULL;
2019 }
2020
2021 rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
2022 if (!rxq)
2023 return -ENOMEM;
2024
2025 rxq->priv = priv;
2026 rxq->mp = mp;
2027 rxq->cksum_enabled = offloads & RTE_ETH_RX_OFFLOAD_IPV4_CKSUM;
2028 rxq->queue_id = idx;
2029 rxq->port_id = dev->data->port_id;
2030 mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
2031
2032 tc = priv->rxq_map[rxq->queue_id].tc,
2033 inq = priv->rxq_map[rxq->queue_id].inq;
2034 priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
2035 desc;
2036
2037 ret = mrvl_fill_bpool(rxq, desc);
2038 if (ret) {
2039 rte_free(rxq);
2040 return ret;
2041 }
2042
2043 priv->bpool_init_size += desc;
2044
2045 dev->data->rx_queues[idx] = rxq;
2046
2047 return 0;
2048}
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058static void
2059mrvl_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
2060{
2061 struct mrvl_rxq *q = dev->data->rx_queues[qid];
2062 struct pp2_ppio_tc_params *tc_params;
2063 int i, num, tc, inq;
2064 struct pp2_hif *hif;
2065 unsigned int core_id = rte_lcore_id();
2066
2067 if (core_id == LCORE_ID_ANY)
2068 core_id = rte_get_main_lcore();
2069
2070 if (!q)
2071 return;
2072
2073 hif = mrvl_get_hif(q->priv, core_id);
2074
2075 if (!hif)
2076 return;
2077
2078 tc = q->priv->rxq_map[q->queue_id].tc;
2079 inq = q->priv->rxq_map[q->queue_id].inq;
2080 tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
2081 num = tc_params->inqs_params[inq].size;
2082 for (i = 0; i < num; i++) {
2083 struct pp2_buff_inf inf;
2084 uint64_t addr;
2085
2086 pp2_bpool_get_buff(hif, q->priv->bpool, &inf);
2087 addr = cookie_addr_high | inf.cookie;
2088 rte_pktmbuf_free((struct rte_mbuf *)addr);
2089 }
2090
2091 rte_free(q);
2092}
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111static int
2112mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
2113 unsigned int socket,
2114 const struct rte_eth_txconf *conf)
2115{
2116 struct mrvl_priv *priv = dev->data->dev_private;
2117 struct mrvl_txq *txq;
2118
2119 if (dev->data->tx_queues[idx]) {
2120 rte_free(dev->data->tx_queues[idx]);
2121 dev->data->tx_queues[idx] = NULL;
2122 }
2123
2124 txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
2125 if (!txq)
2126 return -ENOMEM;
2127
2128 txq->priv = priv;
2129 txq->queue_id = idx;
2130 txq->port_id = dev->data->port_id;
2131 txq->tx_deferred_start = conf->tx_deferred_start;
2132 dev->data->tx_queues[idx] = txq;
2133
2134 priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
2135
2136 return 0;
2137}
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147static void
2148mrvl_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
2149{
2150 struct mrvl_txq *q = dev->data->tx_queues[qid];
2151
2152 if (!q)
2153 return;
2154
2155 rte_free(q);
2156}
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169static int
2170mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2171{
2172 struct mrvl_priv *priv = dev->data->dev_private;
2173 int ret, en;
2174
2175 if (!priv->ppio) {
2176 memcpy(fc_conf, &priv->fc_conf, sizeof(struct rte_eth_fc_conf));
2177 return 0;
2178 }
2179
2180 fc_conf->autoneg = 1;
2181 ret = pp2_ppio_get_rx_pause(priv->ppio, &en);
2182 if (ret) {
2183 MRVL_LOG(ERR, "Failed to read rx pause state");
2184 return ret;
2185 }
2186
2187 fc_conf->mode = en ? RTE_ETH_FC_RX_PAUSE : RTE_ETH_FC_NONE;
2188
2189 ret = pp2_ppio_get_tx_pause(priv->ppio, &en);
2190 if (ret) {
2191 MRVL_LOG(ERR, "Failed to read tx pause state");
2192 return ret;
2193 }
2194
2195 if (en) {
2196 if (fc_conf->mode == RTE_ETH_FC_NONE)
2197 fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
2198 else
2199 fc_conf->mode = RTE_ETH_FC_FULL;
2200 }
2201
2202 return 0;
2203}
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216static int
2217mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2218{
2219 struct mrvl_priv *priv = dev->data->dev_private;
2220 struct pp2_ppio_tx_pause_params mrvl_pause_params;
2221 int ret;
2222 int rx_en, tx_en;
2223
2224 if (fc_conf->high_water ||
2225 fc_conf->low_water ||
2226 fc_conf->pause_time ||
2227 fc_conf->mac_ctrl_frame_fwd) {
2228 MRVL_LOG(ERR, "Flowctrl parameter is not supported");
2229
2230 return -EINVAL;
2231 }
2232
2233 if (fc_conf->autoneg == 0) {
2234 MRVL_LOG(ERR, "Flowctrl Autoneg disable is not supported");
2235 return -EINVAL;
2236 }
2237
2238 if (!priv->ppio) {
2239 memcpy(&priv->fc_conf, fc_conf, sizeof(struct rte_eth_fc_conf));
2240 priv->flow_ctrl = 1;
2241 return 0;
2242 }
2243
2244 switch (fc_conf->mode) {
2245 case RTE_ETH_FC_FULL:
2246 rx_en = 1;
2247 tx_en = 1;
2248 break;
2249 case RTE_ETH_FC_TX_PAUSE:
2250 rx_en = 0;
2251 tx_en = 1;
2252 break;
2253 case RTE_ETH_FC_RX_PAUSE:
2254 rx_en = 1;
2255 tx_en = 0;
2256 break;
2257 case RTE_ETH_FC_NONE:
2258 rx_en = 0;
2259 tx_en = 0;
2260 break;
2261 default:
2262 MRVL_LOG(ERR, "Incorrect Flow control flag (%d)",
2263 fc_conf->mode);
2264 return -EINVAL;
2265 }
2266
2267
2268 ret = pp2_ppio_set_rx_pause(priv->ppio, rx_en);
2269 if (ret) {
2270 MRVL_LOG(ERR, "Failed to change RX flowctrl");
2271 return ret;
2272 }
2273
2274
2275 mrvl_pause_params.en = tx_en;
2276
2277 mrvl_pause_params.use_tc_pause_inqs = 0;
2278 ret = pp2_ppio_set_tx_pause(priv->ppio, &mrvl_pause_params);
2279 if (ret) {
2280 MRVL_LOG(ERR, "Failed to change TX flowctrl");
2281 return ret;
2282 }
2283
2284 return 0;
2285}
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298static int
2299mrvl_rss_hash_update(struct rte_eth_dev *dev,
2300 struct rte_eth_rss_conf *rss_conf)
2301{
2302 struct mrvl_priv *priv = dev->data->dev_private;
2303
2304 if (priv->isolated)
2305 return -ENOTSUP;
2306
2307 return mrvl_configure_rss(priv, rss_conf);
2308}
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321static int
2322mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
2323 struct rte_eth_rss_conf *rss_conf)
2324{
2325 struct mrvl_priv *priv = dev->data->dev_private;
2326 enum pp2_ppio_hash_type hash_type =
2327 priv->ppio_params.inqs_params.hash_type;
2328
2329 rss_conf->rss_key = NULL;
2330
2331 if (hash_type == PP2_PPIO_HASH_T_NONE)
2332 rss_conf->rss_hf = 0;
2333 else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
2334 rss_conf->rss_hf = RTE_ETH_RSS_IPV4;
2335 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
2336 rss_conf->rss_hf = RTE_ETH_RSS_NONFRAG_IPV4_TCP;
2337 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
2338 rss_conf->rss_hf = RTE_ETH_RSS_NONFRAG_IPV4_UDP;
2339
2340 return 0;
2341}
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354static int
2355mrvl_eth_flow_ops_get(struct rte_eth_dev *dev __rte_unused,
2356 const struct rte_flow_ops **ops)
2357{
2358 *ops = &mrvl_flow_ops;
2359 return 0;
2360}
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373static int
2374mrvl_mtr_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2375{
2376 *(const void **)ops = &mrvl_mtr_ops;
2377
2378 return 0;
2379}
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392static int
2393mrvl_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2394{
2395 *(const void **)ops = &mrvl_tm_ops;
2396
2397 return 0;
2398}
2399
2400static const struct eth_dev_ops mrvl_ops = {
2401 .dev_configure = mrvl_dev_configure,
2402 .dev_start = mrvl_dev_start,
2403 .dev_stop = mrvl_dev_stop,
2404 .dev_set_link_up = mrvl_dev_set_link_up,
2405 .dev_set_link_down = mrvl_dev_set_link_down,
2406 .dev_close = mrvl_dev_close,
2407 .link_update = mrvl_link_update,
2408 .promiscuous_enable = mrvl_promiscuous_enable,
2409 .allmulticast_enable = mrvl_allmulticast_enable,
2410 .promiscuous_disable = mrvl_promiscuous_disable,
2411 .allmulticast_disable = mrvl_allmulticast_disable,
2412 .mac_addr_remove = mrvl_mac_addr_remove,
2413 .mac_addr_add = mrvl_mac_addr_add,
2414 .mac_addr_set = mrvl_mac_addr_set,
2415 .mtu_set = mrvl_mtu_set,
2416 .stats_get = mrvl_stats_get,
2417 .stats_reset = mrvl_stats_reset,
2418 .xstats_get = mrvl_xstats_get,
2419 .xstats_reset = mrvl_xstats_reset,
2420 .xstats_get_names = mrvl_xstats_get_names,
2421 .dev_infos_get = mrvl_dev_infos_get,
2422 .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
2423 .rxq_info_get = mrvl_rxq_info_get,
2424 .txq_info_get = mrvl_txq_info_get,
2425 .vlan_filter_set = mrvl_vlan_filter_set,
2426 .vlan_offload_set = mrvl_vlan_offload_set,
2427 .tx_queue_start = mrvl_tx_queue_start,
2428 .tx_queue_stop = mrvl_tx_queue_stop,
2429 .rx_queue_setup = mrvl_rx_queue_setup,
2430 .rx_queue_release = mrvl_rx_queue_release,
2431 .tx_queue_setup = mrvl_tx_queue_setup,
2432 .tx_queue_release = mrvl_tx_queue_release,
2433 .flow_ctrl_get = mrvl_flow_ctrl_get,
2434 .flow_ctrl_set = mrvl_flow_ctrl_set,
2435 .rss_hash_update = mrvl_rss_hash_update,
2436 .rss_hash_conf_get = mrvl_rss_hash_conf_get,
2437 .flow_ops_get = mrvl_eth_flow_ops_get,
2438 .mtr_ops_get = mrvl_mtr_ops_get,
2439 .tm_ops_get = mrvl_tm_ops_get,
2440};
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455static inline uint64_t
2456mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
2457 uint8_t *l3_offset, uint8_t *l4_offset)
2458{
2459 enum pp2_inq_l3_type l3_type;
2460 enum pp2_inq_l4_type l4_type;
2461 enum pp2_inq_vlan_tag vlan_tag;
2462 uint64_t packet_type;
2463
2464 pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
2465 pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
2466 pp2_ppio_inq_desc_get_vlan_tag(desc, &vlan_tag);
2467
2468 packet_type = RTE_PTYPE_L2_ETHER;
2469
2470 switch (vlan_tag) {
2471 case PP2_INQ_VLAN_TAG_SINGLE:
2472 packet_type |= RTE_PTYPE_L2_ETHER_VLAN;
2473 break;
2474 case PP2_INQ_VLAN_TAG_DOUBLE:
2475 case PP2_INQ_VLAN_TAG_TRIPLE:
2476 packet_type |= RTE_PTYPE_L2_ETHER_QINQ;
2477 break;
2478 default:
2479 break;
2480 }
2481
2482 switch (l3_type) {
2483 case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
2484 packet_type |= RTE_PTYPE_L3_IPV4;
2485 break;
2486 case PP2_INQ_L3_TYPE_IPV4_OK:
2487 packet_type |= RTE_PTYPE_L3_IPV4_EXT;
2488 break;
2489 case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
2490 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
2491 break;
2492 case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
2493 packet_type |= RTE_PTYPE_L3_IPV6;
2494 break;
2495 case PP2_INQ_L3_TYPE_IPV6_EXT:
2496 packet_type |= RTE_PTYPE_L3_IPV6_EXT;
2497 break;
2498 case PP2_INQ_L3_TYPE_ARP:
2499 packet_type |= RTE_PTYPE_L2_ETHER_ARP;
2500
2501
2502
2503
2504
2505 *l4_offset = *l3_offset + MRVL_ARP_LENGTH;
2506 break;
2507 default:
2508 break;
2509 }
2510
2511 switch (l4_type) {
2512 case PP2_INQ_L4_TYPE_TCP:
2513 packet_type |= RTE_PTYPE_L4_TCP;
2514 break;
2515 case PP2_INQ_L4_TYPE_UDP:
2516 packet_type |= RTE_PTYPE_L4_UDP;
2517 break;
2518 default:
2519 break;
2520 }
2521
2522 return packet_type;
2523}
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534static inline uint64_t
2535mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc, uint64_t packet_type)
2536{
2537 uint64_t flags = 0;
2538 enum pp2_inq_desc_status status;
2539
2540 if (RTE_ETH_IS_IPV4_HDR(packet_type)) {
2541 status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
2542 if (unlikely(status != PP2_DESC_ERR_OK))
2543 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
2544 else
2545 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
2546 }
2547
2548 if (((packet_type & RTE_PTYPE_L4_UDP) == RTE_PTYPE_L4_UDP) ||
2549 ((packet_type & RTE_PTYPE_L4_TCP) == RTE_PTYPE_L4_TCP)) {
2550 status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
2551 if (unlikely(status != PP2_DESC_ERR_OK))
2552 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
2553 else
2554 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
2555 }
2556
2557 return flags;
2558}
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573static uint16_t
2574mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2575{
2576 struct mrvl_rxq *q = rxq;
2577 struct pp2_ppio_desc descs[nb_pkts];
2578 struct pp2_bpool *bpool;
2579 int i, ret, rx_done = 0;
2580 int num;
2581 struct pp2_hif *hif;
2582 unsigned int core_id = rte_lcore_id();
2583
2584 hif = mrvl_get_hif(q->priv, core_id);
2585
2586 if (unlikely(!q->priv->ppio || !hif))
2587 return 0;
2588
2589 bpool = q->priv->bpool;
2590
2591 ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
2592 q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
2593 if (unlikely(ret < 0))
2594 return 0;
2595
2596 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
2597
2598 for (i = 0; i < nb_pkts; i++) {
2599 struct rte_mbuf *mbuf;
2600 uint8_t l3_offset, l4_offset;
2601 enum pp2_inq_desc_status status;
2602 uint64_t addr;
2603
2604 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2605 struct pp2_ppio_desc *pref_desc;
2606 u64 pref_addr;
2607
2608 pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
2609 pref_addr = cookie_addr_high |
2610 pp2_ppio_inq_desc_get_cookie(pref_desc);
2611 rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
2612 rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
2613 }
2614
2615 addr = cookie_addr_high |
2616 pp2_ppio_inq_desc_get_cookie(&descs[i]);
2617 mbuf = (struct rte_mbuf *)addr;
2618 rte_pktmbuf_reset(mbuf);
2619
2620
2621 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
2622 if ((unlikely(status != PP2_DESC_ERR_OK)) &&
2623 !(q->priv->forward_bad_frames)) {
2624 struct pp2_buff_inf binf = {
2625 .addr = rte_mbuf_data_iova_default(mbuf),
2626 .cookie = (uint64_t)mbuf,
2627 };
2628
2629 pp2_bpool_put_buff(hif, bpool, &binf);
2630 mrvl_port_bpool_size
2631 [bpool->pp2_id][bpool->id][core_id]++;
2632 q->drop_mac++;
2633 continue;
2634 }
2635
2636 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
2637 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
2638 mbuf->data_len = mbuf->pkt_len;
2639 mbuf->port = q->port_id;
2640 mbuf->packet_type =
2641 mrvl_desc_to_packet_type_and_offset(&descs[i],
2642 &l3_offset,
2643 &l4_offset);
2644 mbuf->l2_len = l3_offset;
2645 mbuf->l3_len = l4_offset - l3_offset;
2646
2647 if (likely(q->cksum_enabled))
2648 mbuf->ol_flags =
2649 mrvl_desc_to_ol_flags(&descs[i],
2650 mbuf->packet_type);
2651
2652 rx_pkts[rx_done++] = mbuf;
2653 q->bytes_recv += mbuf->pkt_len;
2654 }
2655
2656 if (rte_spinlock_trylock(&q->priv->lock) == 1) {
2657 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
2658
2659 if (unlikely(num <= q->priv->bpool_min_size ||
2660 (!rx_done && num < q->priv->bpool_init_size))) {
2661 mrvl_fill_bpool(q, q->priv->fill_bpool_buffs);
2662 } else if (unlikely(num > q->priv->bpool_max_size)) {
2663 int i;
2664 int pkt_to_remove = num - q->priv->bpool_init_size;
2665 struct rte_mbuf *mbuf;
2666 struct pp2_buff_inf buff;
2667
2668 for (i = 0; i < pkt_to_remove; i++) {
2669 ret = pp2_bpool_get_buff(hif, bpool, &buff);
2670 if (ret)
2671 break;
2672 mbuf = (struct rte_mbuf *)
2673 (cookie_addr_high | buff.cookie);
2674 rte_pktmbuf_free(mbuf);
2675 }
2676 mrvl_port_bpool_size
2677 [bpool->pp2_id][bpool->id][core_id] -= i;
2678 }
2679 rte_spinlock_unlock(&q->priv->lock);
2680 }
2681
2682 return rx_done;
2683}
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699static inline void
2700mrvl_prepare_proto_info(uint64_t ol_flags,
2701 enum pp2_outq_l3_type *l3_type,
2702 enum pp2_outq_l4_type *l4_type,
2703 int *gen_l3_cksum,
2704 int *gen_l4_cksum)
2705{
2706
2707
2708
2709
2710
2711
2712
2713 *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
2714 *gen_l3_cksum = ol_flags & RTE_MBUF_F_TX_IP_CKSUM ? 1 : 0;
2715
2716 if (ol_flags & RTE_MBUF_F_TX_IPV6) {
2717 *l3_type = PP2_OUTQ_L3_TYPE_IPV6;
2718
2719 *gen_l3_cksum = 0;
2720 }
2721
2722 if ((ol_flags & RTE_MBUF_F_TX_L4_MASK) == RTE_MBUF_F_TX_TCP_CKSUM) {
2723 *l4_type = PP2_OUTQ_L4_TYPE_TCP;
2724 *gen_l4_cksum = 1;
2725 } else if ((ol_flags & RTE_MBUF_F_TX_L4_MASK) == RTE_MBUF_F_TX_UDP_CKSUM) {
2726 *l4_type = PP2_OUTQ_L4_TYPE_UDP;
2727 *gen_l4_cksum = 1;
2728 } else {
2729 *l4_type = PP2_OUTQ_L4_TYPE_OTHER;
2730
2731 *gen_l4_cksum = 0;
2732 }
2733}
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749static inline void
2750mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
2751 unsigned int core_id, struct mrvl_shadow_txq *sq,
2752 int qid, int force)
2753{
2754 struct buff_release_entry *entry;
2755 uint16_t nb_done = 0, num = 0, skip_bufs = 0;
2756 int i;
2757
2758 pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
2759
2760 sq->num_to_release += nb_done;
2761
2762 if (likely(!force &&
2763 sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
2764 return;
2765
2766 nb_done = sq->num_to_release;
2767 sq->num_to_release = 0;
2768
2769 for (i = 0; i < nb_done; i++) {
2770 entry = &sq->ent[sq->tail + num];
2771 if (unlikely(!entry->buff.addr)) {
2772 MRVL_LOG(ERR,
2773 "Shadow memory @%d: cookie(%lx), pa(%lx)!",
2774 sq->tail, (u64)entry->buff.cookie,
2775 (u64)entry->buff.addr);
2776 skip_bufs = 1;
2777 goto skip;
2778 }
2779
2780 if (unlikely(!entry->bpool)) {
2781 struct rte_mbuf *mbuf;
2782
2783 mbuf = (struct rte_mbuf *)entry->buff.cookie;
2784 rte_pktmbuf_free(mbuf);
2785 skip_bufs = 1;
2786 goto skip;
2787 }
2788
2789 mrvl_port_bpool_size
2790 [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
2791 num++;
2792 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
2793 goto skip;
2794 continue;
2795skip:
2796 if (likely(num))
2797 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2798 num += skip_bufs;
2799 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2800 sq->size -= num;
2801 num = 0;
2802 skip_bufs = 0;
2803 }
2804
2805 if (likely(num)) {
2806 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2807 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2808 sq->size -= num;
2809 }
2810}
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825static uint16_t
2826mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2827{
2828 struct mrvl_txq *q = txq;
2829 struct mrvl_shadow_txq *sq;
2830 struct pp2_hif *hif;
2831 struct pp2_ppio_desc descs[nb_pkts];
2832 unsigned int core_id = rte_lcore_id();
2833 int i, bytes_sent = 0;
2834 uint16_t num, sq_free_size;
2835 uint64_t addr;
2836
2837 hif = mrvl_get_hif(q->priv, core_id);
2838 sq = &q->shadow_txqs[core_id];
2839
2840 if (unlikely(!q->priv->ppio || !hif))
2841 return 0;
2842
2843 if (sq->size)
2844 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
2845 sq, q->queue_id, 0);
2846
2847 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
2848 if (unlikely(nb_pkts > sq_free_size))
2849 nb_pkts = sq_free_size;
2850
2851 for (i = 0; i < nb_pkts; i++) {
2852 struct rte_mbuf *mbuf = tx_pkts[i];
2853 int gen_l3_cksum, gen_l4_cksum;
2854 enum pp2_outq_l3_type l3_type;
2855 enum pp2_outq_l4_type l4_type;
2856
2857 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2858 struct rte_mbuf *pref_pkt_hdr;
2859
2860 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2861 rte_mbuf_prefetch_part1(pref_pkt_hdr);
2862 rte_mbuf_prefetch_part2(pref_pkt_hdr);
2863 }
2864
2865 mrvl_fill_shadowq(sq, mbuf);
2866 mrvl_fill_desc(&descs[i], mbuf);
2867
2868 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
2869
2870
2871
2872
2873 if (!(mbuf->ol_flags & MRVL_TX_PKT_OFFLOADS))
2874 continue;
2875 mrvl_prepare_proto_info(mbuf->ol_flags, &l3_type, &l4_type,
2876 &gen_l3_cksum, &gen_l4_cksum);
2877
2878 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
2879 mbuf->l2_len,
2880 mbuf->l2_len + mbuf->l3_len,
2881 gen_l3_cksum, gen_l4_cksum);
2882 }
2883
2884 num = nb_pkts;
2885 pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
2886
2887 if (unlikely(num > nb_pkts)) {
2888 for (i = nb_pkts; i < num; i++) {
2889 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2890 MRVL_PP2_TX_SHADOWQ_MASK;
2891 addr = sq->ent[sq->head].buff.cookie;
2892 bytes_sent -=
2893 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr);
2894 }
2895 sq->size -= num - nb_pkts;
2896 }
2897
2898 q->bytes_sent += bytes_sent;
2899
2900 return nb_pkts;
2901}
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915static uint16_t
2916mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts,
2917 uint16_t nb_pkts)
2918{
2919 struct mrvl_txq *q = txq;
2920 struct mrvl_shadow_txq *sq;
2921 struct pp2_hif *hif;
2922 struct pp2_ppio_desc descs[nb_pkts * PP2_PPIO_DESC_NUM_FRAGS];
2923 struct pp2_ppio_sg_pkts pkts;
2924 uint8_t frags[nb_pkts];
2925 unsigned int core_id = rte_lcore_id();
2926 int i, j, bytes_sent = 0;
2927 int tail, tail_first;
2928 uint16_t num, sq_free_size;
2929 uint16_t nb_segs, total_descs = 0;
2930 uint64_t addr;
2931
2932 hif = mrvl_get_hif(q->priv, core_id);
2933 sq = &q->shadow_txqs[core_id];
2934 pkts.frags = frags;
2935 pkts.num = 0;
2936
2937 if (unlikely(!q->priv->ppio || !hif))
2938 return 0;
2939
2940 if (sq->size)
2941 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
2942 sq, q->queue_id, 0);
2943
2944
2945 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
2946
2947 tail = 0;
2948 for (i = 0; i < nb_pkts; i++) {
2949 struct rte_mbuf *mbuf = tx_pkts[i];
2950 struct rte_mbuf *seg = NULL;
2951 int gen_l3_cksum, gen_l4_cksum;
2952 enum pp2_outq_l3_type l3_type;
2953 enum pp2_outq_l4_type l4_type;
2954
2955 nb_segs = mbuf->nb_segs;
2956 tail_first = tail;
2957 total_descs += nb_segs;
2958
2959
2960
2961
2962
2963 if (unlikely(total_descs > sq_free_size)) {
2964 total_descs -= nb_segs;
2965 break;
2966 }
2967
2968
2969
2970
2971 if (nb_segs > PP2_PPIO_DESC_NUM_FRAGS) {
2972 total_descs -= nb_segs;
2973 RTE_LOG(ERR, PMD,
2974 "Too many segments. Packet won't be sent.\n");
2975 break;
2976 }
2977
2978 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2979 struct rte_mbuf *pref_pkt_hdr;
2980
2981 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2982 rte_mbuf_prefetch_part1(pref_pkt_hdr);
2983 rte_mbuf_prefetch_part2(pref_pkt_hdr);
2984 }
2985
2986 pkts.frags[pkts.num] = nb_segs;
2987 pkts.num++;
2988
2989 seg = mbuf;
2990 for (j = 0; j < nb_segs - 1; j++) {
2991
2992
2993
2994 mrvl_fill_shadowq(sq, NULL);
2995 mrvl_fill_desc(&descs[tail], seg);
2996
2997 tail++;
2998 seg = seg->next;
2999 }
3000
3001 mrvl_fill_shadowq(sq, mbuf);
3002
3003 mrvl_fill_desc(&descs[tail++], seg);
3004
3005 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
3006
3007
3008
3009 if (!(mbuf->ol_flags & MRVL_TX_PKT_OFFLOADS))
3010 continue;
3011 mrvl_prepare_proto_info(mbuf->ol_flags, &l3_type, &l4_type,
3012 &gen_l3_cksum, &gen_l4_cksum);
3013
3014 pp2_ppio_outq_desc_set_proto_info(&descs[tail_first], l3_type,
3015 l4_type, mbuf->l2_len,
3016 mbuf->l2_len + mbuf->l3_len,
3017 gen_l3_cksum, gen_l4_cksum);
3018 }
3019
3020 num = total_descs;
3021 pp2_ppio_send_sg(q->priv->ppio, hif, q->queue_id, descs,
3022 &total_descs, &pkts);
3023
3024 if (unlikely(num > total_descs)) {
3025 for (i = total_descs; i < num; i++) {
3026 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
3027 MRVL_PP2_TX_SHADOWQ_MASK;
3028
3029 addr = sq->ent[sq->head].buff.cookie;
3030 if (addr)
3031 bytes_sent -=
3032 rte_pktmbuf_pkt_len((struct rte_mbuf *)
3033 (cookie_addr_high | addr));
3034 }
3035 sq->size -= num - total_descs;
3036 nb_pkts = pkts.num;
3037 }
3038
3039 q->bytes_sent += bytes_sent;
3040
3041 return nb_pkts;
3042}
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053static struct mrvl_priv *
3054mrvl_priv_create(const char *dev_name)
3055{
3056 struct pp2_bpool_params bpool_params;
3057 char match[MRVL_MATCH_LEN];
3058 struct mrvl_priv *priv;
3059 uint16_t max_frame_size;
3060 int ret, bpool_bit;
3061
3062 priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
3063 if (!priv)
3064 return NULL;
3065
3066 ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
3067 &priv->pp_id, &priv->ppio_id);
3068 if (ret)
3069 goto out_free_priv;
3070
3071 ret = pp2_ppio_get_l4_cksum_max_frame_size(priv->pp_id, priv->ppio_id,
3072 &max_frame_size);
3073 if (ret)
3074 goto out_free_priv;
3075
3076 priv->max_mtu = max_frame_size + RTE_ETHER_CRC_LEN -
3077 MRVL_PP2_ETH_HDRS_LEN;
3078
3079 bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
3080 PP2_BPOOL_NUM_POOLS);
3081 if (bpool_bit < 0)
3082 goto out_free_priv;
3083 priv->bpool_bit = bpool_bit;
3084
3085 snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
3086 priv->bpool_bit);
3087 memset(&bpool_params, 0, sizeof(bpool_params));
3088 bpool_params.match = match;
3089 bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
3090 ret = pp2_bpool_init(&bpool_params, &priv->bpool);
3091 if (ret)
3092 goto out_clear_bpool_bit;
3093
3094 priv->ppio_params.type = PP2_PPIO_T_NIC;
3095 rte_spinlock_init(&priv->lock);
3096
3097 return priv;
3098out_clear_bpool_bit:
3099 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
3100out_free_priv:
3101 rte_free(priv);
3102 return NULL;
3103}
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114static int
3115mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
3116{
3117 int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
3118 struct rte_eth_dev *eth_dev;
3119 struct mrvl_priv *priv;
3120 struct ifreq req;
3121
3122 eth_dev = rte_eth_dev_allocate(name);
3123 if (!eth_dev)
3124 return -ENOMEM;
3125
3126 priv = mrvl_priv_create(name);
3127 if (!priv) {
3128 ret = -ENOMEM;
3129 goto out_free;
3130 }
3131 eth_dev->data->dev_private = priv;
3132
3133 eth_dev->data->mac_addrs =
3134 rte_zmalloc("mac_addrs",
3135 RTE_ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
3136 if (!eth_dev->data->mac_addrs) {
3137 MRVL_LOG(ERR, "Failed to allocate space for eth addrs");
3138 ret = -ENOMEM;
3139 goto out_free;
3140 }
3141
3142 memset(&req, 0, sizeof(req));
3143 strcpy(req.ifr_name, name);
3144 ret = ioctl(fd, SIOCGIFHWADDR, &req);
3145 if (ret)
3146 goto out_free;
3147
3148 memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
3149 req.ifr_addr.sa_data, RTE_ETHER_ADDR_LEN);
3150
3151 eth_dev->device = &vdev->device;
3152 eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
3153 mrvl_set_tx_function(eth_dev);
3154 eth_dev->dev_ops = &mrvl_ops;
3155 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
3156
3157 eth_dev->data->dev_link.link_status = RTE_ETH_LINK_UP;
3158
3159 rte_eth_dev_probing_finish(eth_dev);
3160 return 0;
3161out_free:
3162 rte_eth_dev_release_port(eth_dev);
3163
3164 return ret;
3165}
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181static int
3182mrvl_get_ifnames(const char *key __rte_unused, const char *value,
3183 void *extra_args)
3184{
3185 struct mrvl_ifnames *ifnames = extra_args;
3186
3187 ifnames->names[ifnames->idx++] = value;
3188
3189 return 0;
3190}
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201static int
3202rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
3203{
3204 struct rte_kvargs *kvlist;
3205 struct mrvl_ifnames ifnames;
3206 int ret = -EINVAL;
3207 uint32_t i, ifnum, cfgnum;
3208 const char *params;
3209
3210 params = rte_vdev_device_args(vdev);
3211 if (!params)
3212 return -EINVAL;
3213
3214 kvlist = rte_kvargs_parse(params, valid_args);
3215 if (!kvlist)
3216 return -EINVAL;
3217
3218 ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
3219 if (ifnum > RTE_DIM(ifnames.names))
3220 goto out_free_kvlist;
3221
3222 ifnames.idx = 0;
3223 rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
3224 mrvl_get_ifnames, &ifnames);
3225
3226
3227
3228
3229
3230
3231 if (!mrvl_cfg) {
3232 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
3233 MRVL_LOG(INFO, "Parsing config file!");
3234 if (cfgnum > 1) {
3235 MRVL_LOG(ERR, "Cannot handle more than one config file!");
3236 goto out_free_kvlist;
3237 } else if (cfgnum == 1) {
3238 rte_kvargs_process(kvlist, MRVL_CFG_ARG,
3239 mrvl_get_cfg, &mrvl_cfg);
3240 }
3241 }
3242
3243 if (mrvl_dev_num)
3244 goto init_devices;
3245
3246 MRVL_LOG(INFO, "Perform MUSDK initializations");
3247
3248 ret = rte_mvep_init(MVEP_MOD_T_PP2, kvlist);
3249 if (ret)
3250 goto out_free_kvlist;
3251
3252 ret = mrvl_init_pp2();
3253 if (ret) {
3254 MRVL_LOG(ERR, "Failed to init PP!");
3255 rte_mvep_deinit(MVEP_MOD_T_PP2);
3256 goto out_free_kvlist;
3257 }
3258
3259 memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
3260 memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup));
3261
3262 mrvl_lcore_first = RTE_MAX_LCORE;
3263 mrvl_lcore_last = 0;
3264
3265init_devices:
3266 for (i = 0; i < ifnum; i++) {
3267 MRVL_LOG(INFO, "Creating %s", ifnames.names[i]);
3268 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]);
3269 if (ret)
3270 goto out_cleanup;
3271 mrvl_dev_num++;
3272 }
3273
3274 rte_kvargs_free(kvlist);
3275
3276 return 0;
3277out_cleanup:
3278 rte_pmd_mrvl_remove(vdev);
3279
3280out_free_kvlist:
3281 rte_kvargs_free(kvlist);
3282
3283 return ret;
3284}
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295static int
3296rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
3297{
3298 uint16_t port_id;
3299 int ret = 0;
3300
3301 RTE_ETH_FOREACH_DEV(port_id) {
3302 if (rte_eth_devices[port_id].device != &vdev->device)
3303 continue;
3304 ret |= rte_eth_dev_close(port_id);
3305 }
3306
3307 return ret == 0 ? 0 : -EIO;
3308}
3309
3310static struct rte_vdev_driver pmd_mrvl_drv = {
3311 .probe = rte_pmd_mrvl_probe,
3312 .remove = rte_pmd_mrvl_remove,
3313};
3314
3315RTE_PMD_REGISTER_VDEV(net_mvpp2, pmd_mrvl_drv);
3316RTE_PMD_REGISTER_ALIAS(net_mvpp2, eth_mvpp2);
3317RTE_LOG_REGISTER_DEFAULT(mrvl_logtype, NOTICE);
3318