1
2
3
4
5#ifndef __OTX2_ETHDEV_H__
6#define __OTX2_ETHDEV_H__
7
8#include <math.h>
9#include <stdint.h>
10
11#include <rte_common.h>
12#include <rte_ethdev.h>
13#include <rte_kvargs.h>
14#include <rte_mbuf.h>
15#include <rte_mempool.h>
16#include <rte_security_driver.h>
17#include <rte_spinlock.h>
18#include <rte_string_fns.h>
19#include <rte_time.h>
20
21#include "otx2_common.h"
22#include "otx2_dev.h"
23#include "otx2_flow.h"
24#include "otx2_irq.h"
25#include "otx2_mempool.h"
26#include "otx2_rx.h"
27#include "otx2_tm.h"
28#include "otx2_tx.h"
29
30#define OTX2_ETH_DEV_PMD_VERSION "1.0"
31
32
33
34
35#define OTX2_FIXUP_F_MIN_4K_Q BIT_ULL(63)
36#define otx2_ethdev_fixup_is_min_4k_q(dev) \
37 ((dev)->hwcap & OTX2_FIXUP_F_MIN_4K_Q)
38
39#define OTX2_FIXUP_F_LIMIT_CQ_FULL BIT_ULL(62)
40#define otx2_ethdev_fixup_is_limit_cq_full(dev) \
41 ((dev)->hwcap & OTX2_FIXUP_F_LIMIT_CQ_FULL)
42
43
44#define OTX2_LINK_CFG_IN_PROGRESS_F BIT_ULL(0)
45
46
47
48
49#define NIX_MAX_VTAG_INS 2
50#define NIX_MAX_VTAG_ACT_SIZE (4 * NIX_MAX_VTAG_INS)
51
52
53#define NIX_L2_OVERHEAD \
54 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 8)
55#define NIX_L2_MAX_LEN \
56 (RTE_ETHER_MTU + NIX_L2_OVERHEAD)
57
58
59#define NIX_MAX_HW_FRS 9212
60#define NIX_MIN_HW_FRS 60
61
62
63#define NIX_MAX_FRS \
64 (NIX_MAX_HW_FRS + RTE_ETHER_CRC_LEN - NIX_MAX_VTAG_ACT_SIZE)
65
66#define NIX_MIN_FRS \
67 (NIX_MIN_HW_FRS + RTE_ETHER_CRC_LEN)
68
69#define NIX_MAX_MTU \
70 (NIX_MAX_FRS - NIX_L2_OVERHEAD)
71
72#define NIX_MAX_SQB 512
73#define NIX_DEF_SQB 16
74#define NIX_MIN_SQB 8
75#define NIX_SQB_LIST_SPACE 2
76#define NIX_RSS_RETA_SIZE_MAX 256
77
78#define NIX_RSS_GRPS 8
79#define NIX_HASH_KEY_SIZE 48
80#define NIX_RSS_RETA_SIZE 64
81#define NIX_RX_MIN_DESC 16
82#define NIX_RX_MIN_DESC_ALIGN 16
83#define NIX_RX_NB_SEG_MAX 6
84#define NIX_CQ_ENTRY_SZ 128
85#define NIX_CQ_ALIGN 512
86#define NIX_SQB_LOWER_THRESH 70
87#define LMT_SLOT_MASK 0x7f
88#define NIX_RX_DEFAULT_RING_SZ 4096
89
90
91
92
93#if defined(RTE_LIBRTE_IEEE1588)
94#define NIX_TX_NB_SEG_MAX 7
95#else
96#define NIX_TX_NB_SEG_MAX 9
97#endif
98
99#define NIX_TX_MSEG_SG_DWORDS \
100 ((RTE_ALIGN_MUL_CEIL(NIX_TX_NB_SEG_MAX, 3) / 3) \
101 + NIX_TX_NB_SEG_MAX)
102
103
104#define NIX_CQ_THRESH_LEVEL (5 * 256 / 100)
105#define NIX_CQ_FULL_ERRATA_SKID (1024ull * 256)
106
107#define CQ_OP_STAT_OP_ERR 63
108#define CQ_OP_STAT_CQ_ERR 46
109
110#define OP_ERR BIT_ULL(CQ_OP_STAT_OP_ERR)
111#define CQ_ERR BIT_ULL(CQ_OP_STAT_CQ_ERR)
112
113#define CQ_CQE_THRESH_DEFAULT 0x1ULL
114
115
116
117#define CQ_TIMER_THRESH_DEFAULT 0xAULL
118#define CQ_TIMER_THRESH_MAX 255
119
120#define NIX_RSS_L3_L4_SRC_DST (RTE_ETH_RSS_L3_SRC_ONLY | RTE_ETH_RSS_L3_DST_ONLY \
121 | RTE_ETH_RSS_L4_SRC_ONLY | RTE_ETH_RSS_L4_DST_ONLY)
122
123#define NIX_RSS_OFFLOAD (RTE_ETH_RSS_PORT | RTE_ETH_RSS_IP | RTE_ETH_RSS_UDP |\
124 RTE_ETH_RSS_TCP | RTE_ETH_RSS_SCTP | \
125 RTE_ETH_RSS_TUNNEL | RTE_ETH_RSS_L2_PAYLOAD | \
126 NIX_RSS_L3_L4_SRC_DST | RTE_ETH_RSS_LEVEL_MASK | \
127 RTE_ETH_RSS_C_VLAN)
128
129#define NIX_TX_OFFLOAD_CAPA ( \
130 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE | \
131 RTE_ETH_TX_OFFLOAD_MT_LOCKFREE | \
132 RTE_ETH_TX_OFFLOAD_VLAN_INSERT | \
133 RTE_ETH_TX_OFFLOAD_QINQ_INSERT | \
134 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
135 RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM | \
136 RTE_ETH_TX_OFFLOAD_TCP_CKSUM | \
137 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | \
138 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | \
139 RTE_ETH_TX_OFFLOAD_TCP_TSO | \
140 RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO | \
141 RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO | \
142 RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO | \
143 RTE_ETH_TX_OFFLOAD_MULTI_SEGS | \
144 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM)
145
146#define NIX_RX_OFFLOAD_CAPA ( \
147 RTE_ETH_RX_OFFLOAD_CHECKSUM | \
148 RTE_ETH_RX_OFFLOAD_SCTP_CKSUM | \
149 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
150 RTE_ETH_RX_OFFLOAD_SCATTER | \
151 RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM | \
152 RTE_ETH_RX_OFFLOAD_VLAN_STRIP | \
153 RTE_ETH_RX_OFFLOAD_VLAN_FILTER | \
154 RTE_ETH_RX_OFFLOAD_QINQ_STRIP | \
155 RTE_ETH_RX_OFFLOAD_TIMESTAMP | \
156 RTE_ETH_RX_OFFLOAD_RSS_HASH)
157
158#define NIX_DEFAULT_RSS_CTX_GROUP 0
159#define NIX_DEFAULT_RSS_MCAM_IDX -1
160
161#define otx2_ethdev_is_ptp_en(dev) ((dev)->ptp_en)
162
163#define NIX_TIMESYNC_TX_CMD_LEN 8
164
165#define OTX2_CYCLECOUNTER_MASK 0xffffffffffffffffULL
166
167#define OCTEONTX2_PMD net_octeontx2
168
169#define otx2_ethdev_is_same_driver(dev) \
170 (strcmp((dev)->device->driver->name, RTE_STR(OCTEONTX2_PMD)) == 0)
171
172enum nix_q_size_e {
173 nix_q_size_16,
174 nix_q_size_64,
175 nix_q_size_256,
176 nix_q_size_1K,
177 nix_q_size_4K,
178 nix_q_size_16K,
179 nix_q_size_64K,
180 nix_q_size_256K,
181 nix_q_size_1M,
182 nix_q_size_max
183};
184
185enum nix_lso_tun_type {
186 NIX_LSO_TUN_V4V4,
187 NIX_LSO_TUN_V4V6,
188 NIX_LSO_TUN_V6V4,
189 NIX_LSO_TUN_V6V6,
190 NIX_LSO_TUN_MAX,
191};
192
193struct otx2_qint {
194 struct rte_eth_dev *eth_dev;
195 uint8_t qintx;
196};
197
198struct otx2_rss_info {
199 uint64_t nix_rss;
200 uint32_t flowkey_cfg;
201 uint16_t rss_size;
202 uint8_t rss_grps;
203 uint8_t alg_idx;
204 uint16_t ind_tbl[NIX_RSS_RETA_SIZE_MAX];
205 uint8_t key[NIX_HASH_KEY_SIZE];
206};
207
208struct otx2_eth_qconf {
209 union {
210 struct rte_eth_txconf tx;
211 struct rte_eth_rxconf rx;
212 } conf;
213 void *mempool;
214 uint32_t socket_id;
215 uint16_t nb_desc;
216 uint8_t valid;
217};
218
219struct otx2_fc_info {
220 enum rte_eth_fc_mode mode;
221 uint8_t rx_pause;
222 uint8_t tx_pause;
223 uint8_t chan_cnt;
224 uint16_t bpid[NIX_MAX_CHAN];
225};
226
227struct vlan_mkex_info {
228 struct npc_xtract_info la_xtract;
229 struct npc_xtract_info lb_xtract;
230 uint64_t lb_lt_offset;
231};
232
233struct mcast_entry {
234 struct rte_ether_addr mcast_mac;
235 uint16_t mcam_index;
236 TAILQ_ENTRY(mcast_entry) next;
237};
238
239TAILQ_HEAD(otx2_nix_mc_filter_tbl, mcast_entry);
240
241struct vlan_entry {
242 uint32_t mcam_idx;
243 uint16_t vlan_id;
244 TAILQ_ENTRY(vlan_entry) next;
245};
246
247TAILQ_HEAD(otx2_vlan_filter_tbl, vlan_entry);
248
249struct otx2_vlan_info {
250 struct otx2_vlan_filter_tbl fltr_tbl;
251
252 struct mcam_entry def_tx_mcam_ent;
253 struct mcam_entry def_rx_mcam_ent;
254 struct vlan_mkex_info mkex;
255
256 uint32_t def_rx_mcam_idx;
257 uint32_t def_tx_mcam_idx;
258
259 uint32_t qinq_mcam_idx;
260
261 uint32_t outer_vlan_idx;
262 uint32_t inner_vlan_idx;
263 uint16_t outer_vlan_tpid;
264 uint16_t inner_vlan_tpid;
265 uint16_t pvid;
266
267 uint8_t qinq_before_def;
268 uint8_t pvid_insert_on;
269
270 uint8_t vtag_type_idx;
271 uint8_t filter_on;
272 uint8_t strip_on;
273 uint8_t qinq_on;
274 uint8_t promisc_on;
275};
276
277struct otx2_eth_dev {
278 OTX2_DEV;
279 RTE_MARKER otx2_eth_dev_data_start;
280 uint16_t sqb_size;
281 uint16_t rx_chan_base;
282 uint16_t tx_chan_base;
283 uint8_t rx_chan_cnt;
284 uint8_t tx_chan_cnt;
285 uint8_t lso_tsov4_idx;
286 uint8_t lso_tsov6_idx;
287 uint8_t lso_udp_tun_idx[NIX_LSO_TUN_MAX];
288 uint8_t lso_tun_idx[NIX_LSO_TUN_MAX];
289 uint64_t lso_tun_fmt;
290 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
291 uint8_t mkex_pfl_name[MKEX_NAME_LEN];
292 uint8_t max_mac_entries;
293 bool dmac_filter_enable;
294 uint8_t lf_tx_stats;
295 uint8_t lf_rx_stats;
296 uint8_t lock_rx_ctx;
297 uint8_t lock_tx_ctx;
298 uint16_t flags;
299 uint16_t cints;
300 uint16_t qints;
301 uint8_t configured;
302 uint8_t configured_qints;
303 uint8_t configured_cints;
304 uint8_t configured_nb_rx_qs;
305 uint8_t configured_nb_tx_qs;
306 uint8_t ptype_disable;
307 uint16_t nix_msixoff;
308 uintptr_t base;
309 uintptr_t lmt_addr;
310 uint16_t scalar_ena;
311 uint16_t rss_tag_as_xor;
312 uint16_t max_sqb_count;
313 uint16_t rx_offload_flags;
314 uint64_t rx_offloads;
315 uint16_t tx_offload_flags;
316 uint64_t tx_offloads;
317 uint64_t rx_offload_capa;
318 uint64_t tx_offload_capa;
319 struct otx2_qint qints_mem[RTE_MAX_QUEUES_PER_PORT];
320 struct otx2_qint cints_mem[RTE_MAX_QUEUES_PER_PORT];
321 uint16_t txschq[NIX_TXSCH_LVL_CNT];
322 uint16_t txschq_contig[NIX_TXSCH_LVL_CNT];
323 uint16_t txschq_index[NIX_TXSCH_LVL_CNT];
324 uint16_t txschq_contig_index[NIX_TXSCH_LVL_CNT];
325
326 uint16_t txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
327
328 uint16_t txschq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
329 uint16_t otx2_tm_root_lvl;
330 uint16_t link_cfg_lvl;
331 uint16_t tm_flags;
332 uint16_t tm_leaf_cnt;
333 uint64_t tm_rate_min;
334 struct otx2_nix_tm_node_list node_list;
335 struct otx2_nix_tm_shaper_profile_list shaper_profile_list;
336 struct otx2_rss_info rss_info;
337 struct otx2_fc_info fc_info;
338 uint32_t txmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];
339 uint32_t rxmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];
340 struct otx2_npc_flow_info npc_flow;
341 struct otx2_vlan_info vlan_info;
342 struct otx2_eth_qconf *tx_qconf;
343 struct otx2_eth_qconf *rx_qconf;
344 struct rte_eth_dev *eth_dev;
345 eth_rx_burst_t rx_pkt_burst_no_offload;
346
347 bool ptp_en;
348 struct otx2_timesync_info tstamp;
349 struct rte_timecounter systime_tc;
350 struct rte_timecounter rx_tstamp_tc;
351 struct rte_timecounter tx_tstamp_tc;
352 double clk_freq_mult;
353 uint64_t clk_delta;
354 bool mc_tbl_set;
355 struct otx2_nix_mc_filter_tbl mc_fltr_tbl;
356 bool sdp_link;
357
358 uint16_t ipsec_in_max_spi;
359 rte_spinlock_t ipsec_tbl_lock;
360 uint8_t duplex;
361 uint32_t speed;
362} __rte_cache_aligned;
363
364struct otx2_eth_txq {
365 uint64_t cmd[8];
366 int64_t fc_cache_pkts;
367 uint64_t *fc_mem;
368 void *lmt_addr;
369 rte_iova_t io_addr;
370 rte_iova_t fc_iova;
371 uint16_t sqes_per_sqb_log2;
372 int16_t nb_sqb_bufs_adj;
373 uint64_t lso_tun_fmt;
374 RTE_MARKER slow_path_start;
375 uint16_t nb_sqb_bufs;
376 uint16_t sq;
377 uint64_t offloads;
378 struct otx2_eth_dev *dev;
379 struct rte_mempool *sqb_pool;
380 struct otx2_eth_qconf qconf;
381} __rte_cache_aligned;
382
383struct otx2_eth_rxq {
384 uint64_t mbuf_initializer;
385 uint64_t data_off;
386 uintptr_t desc;
387 void *lookup_mem;
388 uintptr_t cq_door;
389 uint64_t wdata;
390 int64_t *cq_status;
391 uint32_t head;
392 uint32_t qmask;
393 uint32_t available;
394 uint16_t rq;
395 struct otx2_timesync_info *tstamp;
396 RTE_MARKER slow_path_start;
397 uint64_t aura;
398 uint64_t offloads;
399 uint32_t qlen;
400 struct rte_mempool *pool;
401 enum nix_q_size_e qsize;
402 struct rte_eth_dev *eth_dev;
403 struct otx2_eth_qconf qconf;
404 uint16_t cq_drop;
405} __rte_cache_aligned;
406
407static inline struct otx2_eth_dev *
408otx2_eth_pmd_priv(struct rte_eth_dev *eth_dev)
409{
410 return eth_dev->data->dev_private;
411}
412
413
414int otx2_nix_info_get(struct rte_eth_dev *eth_dev,
415 struct rte_eth_dev_info *dev_info);
416int otx2_nix_dev_flow_ops_get(struct rte_eth_dev *eth_dev,
417 const struct rte_flow_ops **ops);
418int otx2_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
419 size_t fw_size);
420int otx2_nix_get_module_info(struct rte_eth_dev *eth_dev,
421 struct rte_eth_dev_module_info *modinfo);
422int otx2_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,
423 struct rte_dev_eeprom_info *info);
424int otx2_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool);
425void otx2_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
426 struct rte_eth_rxq_info *qinfo);
427void otx2_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
428 struct rte_eth_txq_info *qinfo);
429int otx2_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,
430 struct rte_eth_burst_mode *mode);
431int otx2_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,
432 struct rte_eth_burst_mode *mode);
433uint32_t otx2_nix_rx_queue_count(void *rx_queue);
434int otx2_nix_tx_done_cleanup(void *txq, uint32_t free_cnt);
435int otx2_nix_rx_descriptor_status(void *rx_queue, uint16_t offset);
436int otx2_nix_tx_descriptor_status(void *tx_queue, uint16_t offset);
437
438void otx2_nix_promisc_config(struct rte_eth_dev *eth_dev, int en);
439int otx2_nix_promisc_enable(struct rte_eth_dev *eth_dev);
440int otx2_nix_promisc_disable(struct rte_eth_dev *eth_dev);
441int otx2_nix_allmulticast_enable(struct rte_eth_dev *eth_dev);
442int otx2_nix_allmulticast_disable(struct rte_eth_dev *eth_dev);
443int otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx);
444int otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx);
445uint64_t otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id);
446
447
448void otx2_nix_mc_filter_init(struct otx2_eth_dev *dev);
449void otx2_nix_mc_filter_fini(struct otx2_eth_dev *dev);
450int otx2_nix_mc_addr_list_install(struct rte_eth_dev *eth_dev);
451int otx2_nix_mc_addr_list_uninstall(struct rte_eth_dev *eth_dev);
452int otx2_nix_set_mc_addr_list(struct rte_eth_dev *eth_dev,
453 struct rte_ether_addr *mc_addr_set,
454 uint32_t nb_mc_addr);
455
456
457int otx2_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu);
458int otx2_nix_recalc_mtu(struct rte_eth_dev *eth_dev);
459void otx2_nix_enable_mseg_on_jumbo(struct otx2_eth_rxq *rxq);
460
461
462
463void otx2_nix_toggle_flag_link_cfg(struct otx2_eth_dev *dev, bool set);
464int otx2_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
465void otx2_eth_dev_link_status_update(struct otx2_dev *dev,
466 struct cgx_link_user_info *link);
467void otx2_eth_dev_link_status_get(struct otx2_dev *dev,
468 struct cgx_link_user_info *link);
469int otx2_nix_dev_set_link_up(struct rte_eth_dev *eth_dev);
470int otx2_nix_dev_set_link_down(struct rte_eth_dev *eth_dev);
471int otx2_apply_link_speed(struct rte_eth_dev *eth_dev);
472
473
474int otx2_nix_register_irqs(struct rte_eth_dev *eth_dev);
475int oxt2_nix_register_queue_irqs(struct rte_eth_dev *eth_dev);
476int oxt2_nix_register_cq_irqs(struct rte_eth_dev *eth_dev);
477void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev);
478void oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev);
479void oxt2_nix_unregister_cq_irqs(struct rte_eth_dev *eth_dev);
480void otx2_nix_err_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb);
481void otx2_nix_ras_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb);
482
483int otx2_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
484 uint16_t rx_queue_id);
485int otx2_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
486 uint16_t rx_queue_id);
487
488
489int otx2_nix_reg_dump(struct otx2_eth_dev *dev, uint64_t *data);
490int otx2_nix_dev_get_reg(struct rte_eth_dev *eth_dev,
491 struct rte_dev_reg_info *regs);
492int otx2_nix_queues_ctx_dump(struct rte_eth_dev *eth_dev);
493void otx2_nix_cqe_dump(const struct nix_cqe_hdr_s *cq);
494void otx2_nix_tm_dump(struct otx2_eth_dev *dev);
495
496
497int otx2_nix_dev_stats_get(struct rte_eth_dev *eth_dev,
498 struct rte_eth_stats *stats);
499int otx2_nix_dev_stats_reset(struct rte_eth_dev *eth_dev);
500
501int otx2_nix_queue_stats_mapping(struct rte_eth_dev *dev,
502 uint16_t queue_id, uint8_t stat_idx,
503 uint8_t is_rx);
504int otx2_nix_xstats_get(struct rte_eth_dev *eth_dev,
505 struct rte_eth_xstat *xstats, unsigned int n);
506int otx2_nix_xstats_get_names(struct rte_eth_dev *eth_dev,
507 struct rte_eth_xstat_name *xstats_names,
508 unsigned int limit);
509int otx2_nix_xstats_reset(struct rte_eth_dev *eth_dev);
510
511int otx2_nix_xstats_get_by_id(struct rte_eth_dev *eth_dev,
512 const uint64_t *ids,
513 uint64_t *values, unsigned int n);
514int otx2_nix_xstats_get_names_by_id(struct rte_eth_dev *eth_dev,
515 const uint64_t *ids,
516 struct rte_eth_xstat_name *xstats_names,
517 unsigned int limit);
518
519
520void otx2_nix_rss_set_key(struct otx2_eth_dev *dev,
521 uint8_t *key, uint32_t key_len);
522uint32_t otx2_rss_ethdev_to_nix(struct otx2_eth_dev *dev,
523 uint64_t ethdev_rss, uint8_t rss_level);
524int otx2_rss_set_hf(struct otx2_eth_dev *dev,
525 uint32_t flowkey_cfg, uint8_t *alg_idx,
526 uint8_t group, int mcam_index);
527int otx2_nix_rss_tbl_init(struct otx2_eth_dev *dev, uint8_t group,
528 uint16_t *ind_tbl);
529int otx2_nix_rss_config(struct rte_eth_dev *eth_dev);
530
531int otx2_nix_dev_reta_update(struct rte_eth_dev *eth_dev,
532 struct rte_eth_rss_reta_entry64 *reta_conf,
533 uint16_t reta_size);
534int otx2_nix_dev_reta_query(struct rte_eth_dev *eth_dev,
535 struct rte_eth_rss_reta_entry64 *reta_conf,
536 uint16_t reta_size);
537int otx2_nix_rss_hash_update(struct rte_eth_dev *eth_dev,
538 struct rte_eth_rss_conf *rss_conf);
539
540int otx2_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
541 struct rte_eth_rss_conf *rss_conf);
542
543
544int otx2_cgx_rxtx_start(struct otx2_eth_dev *dev);
545int otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev);
546int otx2_cgx_mac_addr_set(struct rte_eth_dev *eth_dev,
547 struct rte_ether_addr *addr);
548
549
550int otx2_nix_flow_ctrl_init(struct rte_eth_dev *eth_dev);
551
552int otx2_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,
553 struct rte_eth_fc_conf *fc_conf);
554
555int otx2_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,
556 struct rte_eth_fc_conf *fc_conf);
557
558int otx2_nix_rxchan_bpid_cfg(struct rte_eth_dev *eth_dev, bool enb);
559
560int otx2_nix_update_flow_ctrl_mode(struct rte_eth_dev *eth_dev);
561
562
563int otx2_nix_vlan_offload_init(struct rte_eth_dev *eth_dev);
564int otx2_nix_vlan_fini(struct rte_eth_dev *eth_dev);
565int otx2_nix_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask);
566void otx2_nix_vlan_update_promisc(struct rte_eth_dev *eth_dev, int enable);
567int otx2_nix_vlan_filter_set(struct rte_eth_dev *eth_dev, uint16_t vlan_id,
568 int on);
569void otx2_nix_vlan_strip_queue_set(struct rte_eth_dev *dev,
570 uint16_t queue, int on);
571int otx2_nix_vlan_tpid_set(struct rte_eth_dev *eth_dev,
572 enum rte_vlan_type type, uint16_t tpid);
573int otx2_nix_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
574
575
576void *otx2_nix_fastpath_lookup_mem_get(void);
577
578
579const uint32_t *otx2_nix_supported_ptypes_get(struct rte_eth_dev *dev);
580int otx2_nix_ptypes_set(struct rte_eth_dev *eth_dev, uint32_t ptype_mask);
581
582
583int otx2_nix_mac_addr_set(struct rte_eth_dev *eth_dev,
584 struct rte_ether_addr *addr);
585int otx2_nix_mac_addr_get(struct rte_eth_dev *eth_dev, uint8_t *addr);
586int otx2_nix_mac_addr_add(struct rte_eth_dev *eth_dev,
587 struct rte_ether_addr *addr,
588 uint32_t index, uint32_t pool);
589void otx2_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index);
590int otx2_cgx_mac_max_entries_get(struct otx2_eth_dev *dev);
591
592
593int otx2_ethdev_parse_devargs(struct rte_devargs *devargs,
594 struct otx2_eth_dev *dev);
595
596
597void otx2_eth_set_rx_function(struct rte_eth_dev *eth_dev);
598void otx2_eth_set_tx_function(struct rte_eth_dev *eth_dev);
599void otx2_nix_form_default_desc(struct otx2_eth_txq *txq);
600
601
602int otx2_nix_timesync_enable(struct rte_eth_dev *eth_dev);
603int otx2_nix_timesync_disable(struct rte_eth_dev *eth_dev);
604int otx2_nix_timesync_read_rx_timestamp(struct rte_eth_dev *eth_dev,
605 struct timespec *timestamp,
606 uint32_t flags);
607int otx2_nix_timesync_read_tx_timestamp(struct rte_eth_dev *eth_dev,
608 struct timespec *timestamp);
609int otx2_nix_timesync_adjust_time(struct rte_eth_dev *eth_dev, int64_t delta);
610int otx2_nix_timesync_write_time(struct rte_eth_dev *eth_dev,
611 const struct timespec *ts);
612int otx2_nix_timesync_read_time(struct rte_eth_dev *eth_dev,
613 struct timespec *ts);
614int otx2_eth_dev_ptp_info_update(struct otx2_dev *dev, bool ptp_en);
615int otx2_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *time);
616int otx2_nix_raw_clock_tsc_conv(struct otx2_eth_dev *dev);
617void otx2_nix_ptp_enable_vf(struct rte_eth_dev *eth_dev);
618
619#endif
620
