LXR dpdk/drivers/baseband/acc100/rte_acc100

   1/* SPDX-License-Identifier: BSD-3-Clause
   2 * Copyright(c) 2020 Intel Corporation
   3 */
   4
   5#ifndef _RTE_ACC100_PMD_H_
   6#define _RTE_ACC100_PMD_H_
   7
   8#include "acc100_pf_enum.h"
   9#include "acc100_vf_enum.h"
  10#include "rte_acc100_cfg.h"
  11
  12/* Helper macro for logging */
  13#define rte_bbdev_log(level, fmt, ...) \
  14        rte_log(RTE_LOG_ ## level, acc100_logtype, fmt "\n", \
  15                ##__VA_ARGS__)
  16
  17#ifdef RTE_LIBRTE_BBDEV_DEBUG
  18#define rte_bbdev_log_debug(fmt, ...) \
  19                rte_bbdev_log(DEBUG, "acc100_pmd: " fmt, \
  20                ##__VA_ARGS__)
  21#else
  22#define rte_bbdev_log_debug(fmt, ...)
  23#endif
  24
  25/* ACC100 PF and VF driver names */
  26#define ACC100PF_DRIVER_NAME           intel_acc100_pf
  27#define ACC100VF_DRIVER_NAME           intel_acc100_vf
  28
  29/* ACC100 PCI vendor & device IDs */
  30#define RTE_ACC100_VENDOR_ID           (0x8086)
  31#define RTE_ACC100_PF_DEVICE_ID        (0x0d5c)
  32#define RTE_ACC100_VF_DEVICE_ID        (0x0d5d)
  33
  34/* Define as 1 to use only a single FEC engine */
  35#ifndef RTE_ACC100_SINGLE_FEC
  36#define RTE_ACC100_SINGLE_FEC 0
  37#endif
  38
  39/* Values used in filling in descriptors */
  40#define ACC100_DMA_DESC_TYPE           2
  41#define ACC100_DMA_CODE_BLK_MODE       0
  42#define ACC100_DMA_BLKID_FCW           1
  43#define ACC100_DMA_BLKID_IN            2
  44#define ACC100_DMA_BLKID_OUT_ENC       1
  45#define ACC100_DMA_BLKID_OUT_HARD      1
  46#define ACC100_DMA_BLKID_OUT_SOFT      2
  47#define ACC100_DMA_BLKID_OUT_HARQ      3
  48#define ACC100_DMA_BLKID_IN_HARQ       3
  49
  50/* Values used in filling in decode FCWs */
  51#define ACC100_FCW_TD_VER              1
  52#define ACC100_FCW_TD_EXT_COLD_REG_EN  1
  53#define ACC100_FCW_TD_AUTOMAP          0x0f
  54#define ACC100_FCW_TD_RVIDX_0          2
  55#define ACC100_FCW_TD_RVIDX_1          26
  56#define ACC100_FCW_TD_RVIDX_2          50
  57#define ACC100_FCW_TD_RVIDX_3          74
  58
  59/* Values used in writing to the registers */
  60#define ACC100_REG_IRQ_EN_ALL          0x1FF83FF  /* Enable all interrupts */
  61
  62/* ACC100 Specific Dimensioning */
  63#define ACC100_SIZE_64MBYTE            (64*1024*1024)
  64/* Number of elements in an Info Ring */
  65#define ACC100_INFO_RING_NUM_ENTRIES   1024
  66/* Number of elements in HARQ layout memory */
  67#define ACC100_HARQ_LAYOUT             (64*1024*1024)
  68/* Assume offset for HARQ in memory */
  69#define ACC100_HARQ_OFFSET             (32*1024)
  70/* Mask used to calculate an index in an Info Ring array (not a byte offset) */
  71#define ACC100_INFO_RING_MASK          (ACC100_INFO_RING_NUM_ENTRIES-1)
  72/* Number of Virtual Functions ACC100 supports */
  73#define ACC100_NUM_VFS                  16
  74#define ACC100_NUM_QGRPS                8
  75#define ACC100_NUM_QGRPS_PER_WORD       8
  76#define ACC100_NUM_AQS                  16
  77#define MAX_ENQ_BATCH_SIZE              255
  78/* All ACC100 Registers alignment are 32bits = 4B */
  79#define ACC100_BYTES_IN_WORD                 4
  80#define ACC100_MAX_E_MBUF                64000
  81
  82#define ACC100_GRP_ID_SHIFT    10 /* Queue Index Hierarchy */
  83#define ACC100_VF_ID_SHIFT     4  /* Queue Index Hierarchy */
  84#define ACC100_VF_OFFSET_QOS   16 /* offset in Memory specific to QoS Mon */
  85#define ACC100_TMPL_PRI_0      0x03020100
  86#define ACC100_TMPL_PRI_1      0x07060504
  87#define ACC100_TMPL_PRI_2      0x0b0a0908
  88#define ACC100_TMPL_PRI_3      0x0f0e0d0c
  89#define ACC100_QUEUE_ENABLE    0x80000000  /* Bit to mark Queue as Enabled */
  90#define ACC100_WORDS_IN_ARAM_SIZE (128 * 1024 / 4)
  91#define ACC100_FDONE    0x80000000
  92#define ACC100_SDONE    0x40000000
  93
  94#define ACC100_NUM_TMPL       32
  95/* Mapping of signals for the available engines */
  96#define ACC100_SIG_UL_5G      0
  97#define ACC100_SIG_UL_5G_LAST 7
  98#define ACC100_SIG_DL_5G      13
  99#define ACC100_SIG_DL_5G_LAST 15
 100#define ACC100_SIG_UL_4G      16
 101#define ACC100_SIG_UL_4G_LAST 21
 102#define ACC100_SIG_DL_4G      27
 103#define ACC100_SIG_DL_4G_LAST 31
 104#define ACC100_NUM_ACCS       5
 105#define ACC100_ACCMAP_0       0
 106#define ACC100_ACCMAP_1       2
 107#define ACC100_ACCMAP_2       1
 108#define ACC100_ACCMAP_3       3
 109#define ACC100_ACCMAP_4       4
 110#define ACC100_PF_VAL         2
 111
 112/* max number of iterations to allocate memory block for all rings */
 113#define ACC100_SW_RING_MEM_ALLOC_ATTEMPTS 5
 114#define ACC100_MAX_QUEUE_DEPTH            1024
 115#define ACC100_DMA_MAX_NUM_POINTERS       14
 116#define ACC100_DMA_MAX_NUM_POINTERS_IN    7
 117#define ACC100_DMA_DESC_PADDING           8
 118#define ACC100_FCW_PADDING                12
 119#define ACC100_DESC_FCW_OFFSET            192
 120#define ACC100_DESC_SIZE                  256
 121#define ACC100_DESC_OFFSET                (ACC100_DESC_SIZE / 64)
 122#define ACC100_FCW_TE_BLEN                32
 123#define ACC100_FCW_TD_BLEN                24
 124#define ACC100_FCW_LE_BLEN                32
 125#define ACC100_FCW_LD_BLEN                36
 126#define ACC100_5GUL_SIZE_0                16
 127#define ACC100_5GUL_SIZE_1                40
 128#define ACC100_5GUL_OFFSET_0              36
 129
 130#define ACC100_FCW_VER         2
 131#define ACC100_MUX_5GDL_DESC   6
 132#define ACC100_CMP_ENC_SIZE    20
 133#define ACC100_CMP_DEC_SIZE    24
 134#define ACC100_ENC_OFFSET     (32)
 135#define ACC100_DEC_OFFSET     (80)
 136#define ACC100_EXT_MEM /* Default option with memory external to CPU */
 137#define ACC100_HARQ_OFFSET_THRESHOLD 1024
 138
 139/* Constants from K0 computation from 3GPP 38.212 Table 5.4.2.1-2 */
 140#define ACC100_N_ZC_1 66 /* N = 66 Zc for BG 1 */
 141#define ACC100_N_ZC_2 50 /* N = 50 Zc for BG 2 */
 142#define ACC100_K0_1_1 17 /* K0 fraction numerator for rv 1 and BG 1 */
 143#define ACC100_K0_1_2 13 /* K0 fraction numerator for rv 1 and BG 2 */
 144#define ACC100_K0_2_1 33 /* K0 fraction numerator for rv 2 and BG 1 */
 145#define ACC100_K0_2_2 25 /* K0 fraction numerator for rv 2 and BG 2 */
 146#define ACC100_K0_3_1 56 /* K0 fraction numerator for rv 3 and BG 1 */
 147#define ACC100_K0_3_2 43 /* K0 fraction numerator for rv 3 and BG 2 */
 148
 149/* ACC100 Configuration */
 150#define ACC100_DDR_ECC_ENABLE
 151#define ACC100_CFG_DMA_ERROR    0x3D7
 152#define ACC100_CFG_AXI_CACHE    0x11
 153#define ACC100_CFG_QMGR_HI_P    0x0F0F
 154#define ACC100_CFG_PCI_AXI      0xC003
 155#define ACC100_CFG_PCI_BRIDGE   0x40006033
 156#define ACC100_ENGINE_OFFSET    0x1000
 157#define ACC100_RESET_HI         0x20100
 158#define ACC100_RESET_LO         0x20000
 159#define ACC100_RESET_HARD       0x1FF
 160#define ACC100_ENGINES_MAX      9
 161#define ACC100_LONG_WAIT        1000
 162#define ACC100_GPEX_AXIMAP_NUM  17
 163
 164/* ACC100 DMA Descriptor triplet */
 165struct acc100_dma_triplet {
 166        uint64_t address;
 167        uint32_t blen:20,
 168                res0:4,
 169                last:1,
 170                dma_ext:1,
 171                res1:2,
 172                blkid:4;
 173} __rte_packed;
 174
 175/* ACC100 DMA Response Descriptor */
 176union acc100_dma_rsp_desc {
 177        uint32_t val;
 178        struct {
 179                uint32_t crc_status:1,
 180                        synd_ok:1,
 181                        dma_err:1,
 182                        neg_stop:1,
 183                        fcw_err:1,
 184                        output_err:1,
 185                        input_err:1,
 186                        timestampEn:1,
 187                        iterCountFrac:8,
 188                        iter_cnt:8,
 189                        rsrvd3:6,
 190                        sdone:1,
 191                        fdone:1;
 192                uint32_t add_info_0;
 193                uint32_t add_info_1;
 194        };
 195};
 196
 197
 198/* ACC100 Queue Manager Enqueue PCI Register */
 199union acc100_enqueue_reg_fmt {
 200        uint32_t val;
 201        struct {
 202                uint32_t num_elem:8,
 203                        addr_offset:3,
 204                        rsrvd:1,
 205                        req_elem_addr:20;
 206        };
 207};
 208
 209/* FEC 4G Uplink Frame Control Word */
 210struct __rte_packed acc100_fcw_td {
 211        uint8_t fcw_ver:4,
 212                num_maps:4; /* Unused */
 213        uint8_t filler:6, /* Unused */
 214                rsrvd0:1,
 215                bypass_sb_deint:1;
 216        uint16_t k_pos;
 217        uint16_t k_neg; /* Unused */
 218        uint8_t c_neg; /* Unused */
 219        uint8_t c; /* Unused */
 220        uint32_t ea; /* Unused */
 221        uint32_t eb; /* Unused */
 222        uint8_t cab; /* Unused */
 223        uint8_t k0_start_col; /* Unused */
 224        uint8_t rsrvd1;
 225        uint8_t code_block_mode:1, /* Unused */
 226                turbo_crc_type:1,
 227                rsrvd2:3,
 228                bypass_teq:1, /* Unused */
 229                soft_output_en:1, /* Unused */
 230                ext_td_cold_reg_en:1;
 231        union { /* External Cold register */
 232                uint32_t ext_td_cold_reg;
 233                struct {
 234                        uint32_t min_iter:4, /* Unused */
 235                                max_iter:4,
 236                                ext_scale:5, /* Unused */
 237                                rsrvd3:3,
 238                                early_stop_en:1, /* Unused */
 239                                sw_soft_out_dis:1, /* Unused */
 240                                sw_et_cont:1, /* Unused */
 241                                sw_soft_out_saturation:1, /* Unused */
 242                                half_iter_on:1, /* Unused */
 243                                raw_decoder_input_on:1, /* Unused */
 244                                rsrvd4:10;
 245                };
 246        };
 247};
 248
 249/* FEC 5GNR Uplink Frame Control Word */
 250struct __rte_packed acc100_fcw_ld {
 251        uint32_t FCWversion:4,
 252                qm:4,
 253                nfiller:11,
 254                BG:1,
 255                Zc:9,
 256                res0:1,
 257                synd_precoder:1,
 258                synd_post:1;
 259        uint32_t ncb:16,
 260                k0:16;
 261        uint32_t rm_e:24,
 262                hcin_en:1,
 263                hcout_en:1,
 264                crc_select:1,
 265                bypass_dec:1,
 266                bypass_intlv:1,
 267                so_en:1,
 268                so_bypass_rm:1,
 269                so_bypass_intlv:1;
 270        uint32_t hcin_offset:16,
 271                hcin_size0:16;
 272        uint32_t hcin_size1:16,
 273                hcin_decomp_mode:3,
 274                llr_pack_mode:1,
 275                hcout_comp_mode:3,
 276                res2:1,
 277                dec_convllr:4,
 278                hcout_convllr:4;
 279        uint32_t itmax:7,
 280                itstop:1,
 281                so_it:7,
 282                res3:1,
 283                hcout_offset:16;
 284        uint32_t hcout_size0:16,
 285                hcout_size1:16;
 286        uint32_t gain_i:8,
 287                gain_h:8,
 288                negstop_th:16;
 289        uint32_t negstop_it:7,
 290                negstop_en:1,
 291                res4:24;
 292};
 293
 294/* FEC 4G Downlink Frame Control Word */
 295struct __rte_packed acc100_fcw_te {
 296        uint16_t k_neg;
 297        uint16_t k_pos;
 298        uint8_t c_neg;
 299        uint8_t c;
 300        uint8_t filler;
 301        uint8_t cab;
 302        uint32_t ea:17,
 303                rsrvd0:15;
 304        uint32_t eb:17,
 305                rsrvd1:15;
 306        uint16_t ncb_neg;
 307        uint16_t ncb_pos;
 308        uint8_t rv_idx0:2,
 309                rsrvd2:2,
 310                rv_idx1:2,
 311                rsrvd3:2;
 312        uint8_t bypass_rv_idx0:1,
 313                bypass_rv_idx1:1,
 314                bypass_rm:1,
 315                rsrvd4:5;
 316        uint8_t rsrvd5:1,
 317                rsrvd6:3,
 318                code_block_crc:1,
 319                rsrvd7:3;
 320        uint8_t code_block_mode:1,
 321                rsrvd8:7;
 322        uint64_t rsrvd9;
 323};
 324
 325/* FEC 5GNR Downlink Frame Control Word */
 326struct __rte_packed acc100_fcw_le {
 327        uint32_t FCWversion:4,
 328                qm:4,
 329                nfiller:11,
 330                BG:1,
 331                Zc:9,
 332                res0:3;
 333        uint32_t ncb:16,
 334                k0:16;
 335        uint32_t rm_e:24,
 336                res1:2,
 337                crc_select:1,
 338                res2:1,
 339                bypass_intlv:1,
 340                res3:3;
 341        uint32_t res4_a:12,
 342                mcb_count:3,
 343                res4_b:17;
 344        uint32_t res5;
 345        uint32_t res6;
 346        uint32_t res7;
 347        uint32_t res8;
 348};
 349
 350/* ACC100 DMA Request Descriptor */
 351struct __rte_packed acc100_dma_req_desc {
 352        union {
 353                struct{
 354                        uint32_t type:4,
 355                                rsrvd0:26,
 356                                sdone:1,
 357                                fdone:1;
 358                        uint32_t rsrvd1;
 359                        uint32_t rsrvd2;
 360                        uint32_t pass_param:8,
 361                                sdone_enable:1,
 362                                irq_enable:1,
 363                                timeStampEn:1,
 364                                res0:5,
 365                                numCBs:4,
 366                                res1:4,
 367                                m2dlen:4,
 368                                d2mlen:4;
 369                };
 370                struct{
 371                        uint32_t word0;
 372                        uint32_t word1;
 373                        uint32_t word2;
 374                        uint32_t word3;
 375                };
 376        };
 377        struct acc100_dma_triplet data_ptrs[ACC100_DMA_MAX_NUM_POINTERS];
 378
 379        /* Virtual addresses used to retrieve SW context info */
 380        union {
 381                void *op_addr;
 382                uint64_t pad1;  /* pad to 64 bits */
 383        };
 384        /*
 385         * Stores additional information needed for driver processing:
 386         * - last_desc_in_batch - flag used to mark last descriptor (CB)
 387         *                        in batch
 388         * - cbs_in_tb - stores information about total number of Code Blocks
 389         *               in currently processed Transport Block
 390         */
 391        union {
 392                struct {
 393                        union {
 394                                struct acc100_fcw_ld fcw_ld;
 395                                struct acc100_fcw_td fcw_td;
 396                                struct acc100_fcw_le fcw_le;
 397                                struct acc100_fcw_te fcw_te;
 398                                uint32_t pad2[ACC100_FCW_PADDING];
 399                        };
 400                        uint32_t last_desc_in_batch :8,
 401                                cbs_in_tb:8,
 402                                pad4 : 16;
 403                };
 404                uint64_t pad3[ACC100_DMA_DESC_PADDING]; /* pad to 64 bits */
 405        };
 406};
 407
 408/* ACC100 DMA Descriptor */
 409union acc100_dma_desc {
 410        struct acc100_dma_req_desc req;
 411        union acc100_dma_rsp_desc rsp;
 412        uint64_t atom_hdr;
 413};
 414
 415
 416/* Union describing Info Ring entry */
 417union acc100_harq_layout_data {
 418        uint32_t val;
 419        struct {
 420                uint16_t offset;
 421                uint16_t size0;
 422        };
 423} __rte_packed;
 424
 425
 426/* Union describing Info Ring entry */
 427union acc100_info_ring_data {
 428        uint32_t val;
 429        struct {
 430                union {
 431                        uint16_t detailed_info;
 432                        struct {
 433                                uint16_t aq_id: 4;
 434                                uint16_t qg_id: 4;
 435                                uint16_t vf_id: 6;
 436                                uint16_t reserved: 2;
 437                        };
 438                };
 439                uint16_t int_nb: 7;
 440                uint16_t msi_0: 1;
 441                uint16_t vf2pf: 6;
 442                uint16_t loop: 1;
 443                uint16_t valid: 1;
 444        };
 445} __rte_packed;
 446
 447struct acc100_registry_addr {
 448        unsigned int dma_ring_dl5g_hi;
 449        unsigned int dma_ring_dl5g_lo;
 450        unsigned int dma_ring_ul5g_hi;
 451        unsigned int dma_ring_ul5g_lo;
 452        unsigned int dma_ring_dl4g_hi;
 453        unsigned int dma_ring_dl4g_lo;
 454        unsigned int dma_ring_ul4g_hi;
 455        unsigned int dma_ring_ul4g_lo;
 456        unsigned int ring_size;
 457        unsigned int info_ring_hi;
 458        unsigned int info_ring_lo;
 459        unsigned int info_ring_en;
 460        unsigned int info_ring_ptr;
 461        unsigned int tail_ptrs_dl5g_hi;
 462        unsigned int tail_ptrs_dl5g_lo;
 463        unsigned int tail_ptrs_ul5g_hi;
 464        unsigned int tail_ptrs_ul5g_lo;
 465        unsigned int tail_ptrs_dl4g_hi;
 466        unsigned int tail_ptrs_dl4g_lo;
 467        unsigned int tail_ptrs_ul4g_hi;
 468        unsigned int tail_ptrs_ul4g_lo;
 469        unsigned int depth_log0_offset;
 470        unsigned int depth_log1_offset;
 471        unsigned int qman_group_func;
 472        unsigned int ddr_range;
 473};
 474
 475/* Structure holding registry addresses for PF */
 476static const struct acc100_registry_addr pf_reg_addr = {
 477        .dma_ring_dl5g_hi = HWPfDmaFec5GdlDescBaseHiRegVf,
 478        .dma_ring_dl5g_lo = HWPfDmaFec5GdlDescBaseLoRegVf,
 479        .dma_ring_ul5g_hi = HWPfDmaFec5GulDescBaseHiRegVf,
 480        .dma_ring_ul5g_lo = HWPfDmaFec5GulDescBaseLoRegVf,
 481        .dma_ring_dl4g_hi = HWPfDmaFec4GdlDescBaseHiRegVf,
 482        .dma_ring_dl4g_lo = HWPfDmaFec4GdlDescBaseLoRegVf,
 483        .dma_ring_ul4g_hi = HWPfDmaFec4GulDescBaseHiRegVf,
 484        .dma_ring_ul4g_lo = HWPfDmaFec4GulDescBaseLoRegVf,
 485        .ring_size = HWPfQmgrRingSizeVf,
 486        .info_ring_hi = HWPfHiInfoRingBaseHiRegPf,
 487        .info_ring_lo = HWPfHiInfoRingBaseLoRegPf,
 488        .info_ring_en = HWPfHiInfoRingIntWrEnRegPf,
 489        .info_ring_ptr = HWPfHiInfoRingPointerRegPf,
 490        .tail_ptrs_dl5g_hi = HWPfDmaFec5GdlRespPtrHiRegVf,
 491        .tail_ptrs_dl5g_lo = HWPfDmaFec5GdlRespPtrLoRegVf,
 492        .tail_ptrs_ul5g_hi = HWPfDmaFec5GulRespPtrHiRegVf,
 493        .tail_ptrs_ul5g_lo = HWPfDmaFec5GulRespPtrLoRegVf,
 494        .tail_ptrs_dl4g_hi = HWPfDmaFec4GdlRespPtrHiRegVf,
 495        .tail_ptrs_dl4g_lo = HWPfDmaFec4GdlRespPtrLoRegVf,
 496        .tail_ptrs_ul4g_hi = HWPfDmaFec4GulRespPtrHiRegVf,
 497        .tail_ptrs_ul4g_lo = HWPfDmaFec4GulRespPtrLoRegVf,
 498        .depth_log0_offset = HWPfQmgrGrpDepthLog20Vf,
 499        .depth_log1_offset = HWPfQmgrGrpDepthLog21Vf,
 500        .qman_group_func = HWPfQmgrGrpFunction0,
 501        .ddr_range = HWPfDmaVfDdrBaseRw,
 502};
 503
 504/* Structure holding registry addresses for VF */
 505static const struct acc100_registry_addr vf_reg_addr = {
 506        .dma_ring_dl5g_hi = HWVfDmaFec5GdlDescBaseHiRegVf,
 507        .dma_ring_dl5g_lo = HWVfDmaFec5GdlDescBaseLoRegVf,
 508        .dma_ring_ul5g_hi = HWVfDmaFec5GulDescBaseHiRegVf,
 509        .dma_ring_ul5g_lo = HWVfDmaFec5GulDescBaseLoRegVf,
 510        .dma_ring_dl4g_hi = HWVfDmaFec4GdlDescBaseHiRegVf,
 511        .dma_ring_dl4g_lo = HWVfDmaFec4GdlDescBaseLoRegVf,
 512        .dma_ring_ul4g_hi = HWVfDmaFec4GulDescBaseHiRegVf,
 513        .dma_ring_ul4g_lo = HWVfDmaFec4GulDescBaseLoRegVf,
 514        .ring_size = HWVfQmgrRingSizeVf,
 515        .info_ring_hi = HWVfHiInfoRingBaseHiVf,
 516        .info_ring_lo = HWVfHiInfoRingBaseLoVf,
 517        .info_ring_en = HWVfHiInfoRingIntWrEnVf,
 518        .info_ring_ptr = HWVfHiInfoRingPointerVf,
 519        .tail_ptrs_dl5g_hi = HWVfDmaFec5GdlRespPtrHiRegVf,
 520        .tail_ptrs_dl5g_lo = HWVfDmaFec5GdlRespPtrLoRegVf,
 521        .tail_ptrs_ul5g_hi = HWVfDmaFec5GulRespPtrHiRegVf,
 522        .tail_ptrs_ul5g_lo = HWVfDmaFec5GulRespPtrLoRegVf,
 523        .tail_ptrs_dl4g_hi = HWVfDmaFec4GdlRespPtrHiRegVf,
 524        .tail_ptrs_dl4g_lo = HWVfDmaFec4GdlRespPtrLoRegVf,
 525        .tail_ptrs_ul4g_hi = HWVfDmaFec4GulRespPtrHiRegVf,
 526        .tail_ptrs_ul4g_lo = HWVfDmaFec4GulRespPtrLoRegVf,
 527        .depth_log0_offset = HWVfQmgrGrpDepthLog20Vf,
 528        .depth_log1_offset = HWVfQmgrGrpDepthLog21Vf,
 529        .qman_group_func = HWVfQmgrGrpFunction0Vf,
 530        .ddr_range = HWVfDmaDdrBaseRangeRoVf,
 531};
 532
 533/* Structure associated with each queue. */
 534struct __rte_cache_aligned acc100_queue {
 535        union acc100_dma_desc *ring_addr;  /* Virtual address of sw ring */
 536        rte_iova_t ring_addr_iova;  /* IOVA address of software ring */
 537        uint32_t sw_ring_head;  /* software ring head */
 538        uint32_t sw_ring_tail;  /* software ring tail */
 539        /* software ring size (descriptors, not bytes) */
 540        uint32_t sw_ring_depth;
 541        /* mask used to wrap enqueued descriptors on the sw ring */
 542        uint32_t sw_ring_wrap_mask;
 543        /* MMIO register used to enqueue descriptors */
 544        void *mmio_reg_enqueue;
 545        uint8_t vf_id;  /* VF ID (max = 63) */
 546        uint8_t qgrp_id;  /* Queue Group ID */
 547        uint16_t aq_id;  /* Atomic Queue ID */
 548        uint16_t aq_depth;  /* Depth of atomic queue */
 549        uint32_t aq_enqueued;  /* Count how many "batches" have been enqueued */
 550        uint32_t aq_dequeued;  /* Count how many "batches" have been dequeued */
 551        uint32_t irq_enable;  /* Enable ops dequeue interrupts if set to 1 */
 552        struct rte_mempool *fcw_mempool;  /* FCW mempool */
 553        enum rte_bbdev_op_type op_type;  /* Type of this Queue: TE or TD */
 554        /* Internal Buffers for loopback input */
 555        uint8_t *lb_in;
 556        uint8_t *lb_out;
 557        rte_iova_t lb_in_addr_iova;
 558        rte_iova_t lb_out_addr_iova;
 559        struct acc100_device *d;
 560};
 561
 562/* Private data structure for each ACC100 device */
 563struct acc100_device {
 564        void *mmio_base;  /**< Base address of MMIO registers (BAR0) */
 565        void *sw_rings_base;  /* Base addr of un-aligned memory for sw rings */
 566        void *sw_rings;  /* 64MBs of 64MB aligned memory for sw rings */
 567        rte_iova_t sw_rings_iova;  /* IOVA address of sw_rings */
 568        /* Virtual address of the info memory routed to the this function under
 569         * operation, whether it is PF or VF.
 570         * HW may DMA information data at this location asynchronously
 571         */
 572        union acc100_info_ring_data *info_ring;
 573
 574        union acc100_harq_layout_data *harq_layout;
 575        /* Virtual Info Ring head */
 576        uint16_t info_ring_head;
 577        /* Number of bytes available for each queue in device, depending on
 578         * how many queues are enabled with configure()
 579         */
 580        uint32_t sw_ring_size;
 581        uint32_t ddr_size; /* Size in kB */
 582        uint32_t *tail_ptrs; /* Base address of response tail pointer buffer */
 583        rte_iova_t tail_ptr_iova; /* IOVA address of tail pointers */
 584        /* Max number of entries available for each queue in device, depending
 585         * on how many queues are enabled with configure()
 586         */
 587        uint32_t sw_ring_max_depth;
 588        struct rte_acc100_conf acc100_conf; /* ACC100 Initial configuration */
 589        /* Bitmap capturing which Queues have already been assigned */
 590        uint16_t q_assigned_bit_map[ACC100_NUM_QGRPS];
 591        bool pf_device; /**< True if this is a PF ACC100 device */
 592        bool configured; /**< True if this ACC100 device is configured */
 593};
 594
 595/**
 596 * Structure with details about RTE_BBDEV_EVENT_DEQUEUE event. It's passed to
 597 * the callback function.
 598 */
 599struct acc100_deq_intr_details {
 600        uint16_t queue_id;
 601};
 602
 603#endif /* _RTE_ACC100_PMD_H_ */
 604