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4
5#ifndef _VMXNET3_ETHDEV_H_
6#define _VMXNET3_ETHDEV_H_
7
8#include <rte_io.h>
9#include <rte_mbuf_dyn.h>
10
11#define VMXNET3_MAX_MAC_ADDRS 1
12
13
14#define VMXNET3_F_RXCSUM 0x0001
15#define VMXNET3_F_RSS 0x0002
16#define VMXNET3_F_RXVLAN 0x0004
17#define VMXNET3_F_LRO 0x0008
18
19
20#define VMXNET3_RSS_HASH_TYPE_NONE 0x0
21#define VMXNET3_RSS_HASH_TYPE_IPV4 0x01
22#define VMXNET3_RSS_HASH_TYPE_TCP_IPV4 0x02
23#define VMXNET3_RSS_HASH_TYPE_IPV6 0x04
24#define VMXNET3_RSS_HASH_TYPE_TCP_IPV6 0x08
25
26#define VMXNET3_RSS_HASH_FUNC_NONE 0x0
27#define VMXNET3_RSS_HASH_FUNC_TOEPLITZ 0x01
28
29#define VMXNET3_RSS_MAX_KEY_SIZE 40
30#define VMXNET3_RSS_MAX_IND_TABLE_SIZE 128
31#define VMXNET3_MAX_MSIX_VECT (VMXNET3_MAX_TX_QUEUES + \
32 VMXNET3_MAX_RX_QUEUES + 1)
33
34#define VMXNET3_RSS_OFFLOAD_ALL ( \
35 RTE_ETH_RSS_IPV4 | \
36 RTE_ETH_RSS_NONFRAG_IPV4_TCP | \
37 RTE_ETH_RSS_IPV6 | \
38 RTE_ETH_RSS_NONFRAG_IPV6_TCP)
39
40#define VMXNET3_V4_RSS_MASK ( \
41 RTE_ETH_RSS_NONFRAG_IPV4_UDP | \
42 RTE_ETH_RSS_NONFRAG_IPV6_UDP)
43
44#define VMXNET3_MANDATORY_V4_RSS ( \
45 RTE_ETH_RSS_NONFRAG_IPV4_TCP | \
46 RTE_ETH_RSS_NONFRAG_IPV6_TCP)
47
48
49typedef struct VMXNET3_RSSConf {
50 uint16_t hashType;
51 uint16_t hashFunc;
52 uint16_t hashKeySize;
53 uint16_t indTableSize;
54 uint8_t hashKey[VMXNET3_RSS_MAX_KEY_SIZE];
55
56
57
58
59 uint8_t indTable[VMXNET3_RSS_MAX_IND_TABLE_SIZE];
60} VMXNET3_RSSConf;
61
62typedef struct vmxnet3_mf_table {
63 void *mfTableBase;
64 uint64_t mfTablePA;
65 uint16_t num_addrs;
66} vmxnet3_mf_table_t;
67
68struct vmxnet3_intr {
69 enum vmxnet3_intr_mask_mode mask_mode;
70 enum vmxnet3_intr_type type;
71 uint8_t num_intrs;
72 uint8_t event_intr_idx;
73 uint8_t mod_levels[VMXNET3_MAX_MSIX_VECT];
74 bool lsc_only;
75};
76
77struct vmxnet3_hw {
78 uint8_t *hw_addr0;
79 uint8_t *hw_addr1;
80
81
82 void *back;
83
84 uint16_t device_id;
85 uint16_t vendor_id;
86 uint16_t subsystem_device_id;
87 uint16_t subsystem_vendor_id;
88 bool adapter_stopped;
89
90 uint8_t perm_addr[RTE_ETHER_ADDR_LEN];
91 uint8_t num_tx_queues;
92 uint8_t num_rx_queues;
93 uint8_t bufs_per_pkt;
94
95 uint8_t version;
96
97 uint16_t txdata_desc_size;
98 uint16_t rxdata_desc_size;
99
100 uint8_t num_intrs;
101
102 Vmxnet3_TxQueueDesc *tqd_start;
103 Vmxnet3_RxQueueDesc *rqd_start;
104
105 Vmxnet3_DriverShared *shared;
106 uint64_t sharedPA;
107
108 uint64_t queueDescPA;
109 uint16_t queue_desc_len;
110 uint16_t mtu;
111
112 VMXNET3_RSSConf *rss_conf;
113 uint64_t rss_confPA;
114 vmxnet3_mf_table_t *mf_table;
115 uint32_t shadow_vfta[VMXNET3_VFT_SIZE];
116 struct vmxnet3_intr intr;
117 Vmxnet3_MemRegs *memRegs;
118 uint64_t memRegsPA;
119#define VMXNET3_VFT_TABLE_SIZE (VMXNET3_VFT_SIZE * sizeof(uint32_t))
120 UPT1_TxStats saved_tx_stats[VMXNET3_MAX_TX_QUEUES];
121 UPT1_RxStats saved_rx_stats[VMXNET3_MAX_RX_QUEUES];
122
123 UPT1_TxStats snapshot_tx_stats[VMXNET3_MAX_TX_QUEUES];
124 UPT1_RxStats snapshot_rx_stats[VMXNET3_MAX_RX_QUEUES];
125};
126
127#define VMXNET3_REV_4 3
128#define VMXNET3_REV_3 2
129#define VMXNET3_REV_2 1
130#define VMXNET3_REV_1 0
131
132#define VMXNET3_VERSION_GE_4(hw) ((hw)->version >= VMXNET3_REV_4 + 1)
133#define VMXNET3_VERSION_GE_3(hw) ((hw)->version >= VMXNET3_REV_3 + 1)
134#define VMXNET3_VERSION_GE_2(hw) ((hw)->version >= VMXNET3_REV_2 + 1)
135
136#define VMXNET3_GET_ADDR_LO(reg) ((uint32_t)(reg))
137#define VMXNET3_GET_ADDR_HI(reg) ((uint32_t)(((uint64_t)(reg)) >> 32))
138
139
140
141#define VMXNET3_PCI_REG(reg) rte_read32(reg)
142
143static inline uint32_t
144vmxnet3_read_addr(volatile void *addr)
145{
146 return VMXNET3_PCI_REG(addr);
147}
148
149#define VMXNET3_PCI_REG_WRITE(reg, value) rte_write32((value), (reg))
150
151#define VMXNET3_PCI_BAR0_REG_ADDR(hw, reg) \
152 ((volatile uint32_t *)((char *)(hw)->hw_addr0 + (reg)))
153#define VMXNET3_READ_BAR0_REG(hw, reg) \
154 vmxnet3_read_addr(VMXNET3_PCI_BAR0_REG_ADDR((hw), (reg)))
155#define VMXNET3_WRITE_BAR0_REG(hw, reg, value) \
156 VMXNET3_PCI_REG_WRITE(VMXNET3_PCI_BAR0_REG_ADDR((hw), (reg)), (value))
157
158#define VMXNET3_PCI_BAR1_REG_ADDR(hw, reg) \
159 ((volatile uint32_t *)((char *)(hw)->hw_addr1 + (reg)))
160#define VMXNET3_READ_BAR1_REG(hw, reg) \
161 vmxnet3_read_addr(VMXNET3_PCI_BAR1_REG_ADDR((hw), (reg)))
162#define VMXNET3_WRITE_BAR1_REG(hw, reg, value) \
163 VMXNET3_PCI_REG_WRITE(VMXNET3_PCI_BAR1_REG_ADDR((hw), (reg)), (value))
164
165static inline uint8_t
166vmxnet3_get_ring_idx(struct vmxnet3_hw *hw, uint32 rqID)
167{
168 return (rqID >= hw->num_rx_queues &&
169 rqID < 2 * hw->num_rx_queues) ? 1 : 0;
170}
171
172static inline bool
173vmxnet3_rx_data_ring(struct vmxnet3_hw *hw, uint32 rqID)
174{
175 return (rqID >= 2 * hw->num_rx_queues &&
176 rqID < 3 * hw->num_rx_queues);
177}
178
179
180
181
182
183void vmxnet3_dev_clear_queues(struct rte_eth_dev *dev);
184
185void vmxnet3_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
186void vmxnet3_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
187
188int vmxnet3_v4_rss_configure(struct rte_eth_dev *dev);
189
190int vmxnet3_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
191 uint16_t nb_rx_desc, unsigned int socket_id,
192 const struct rte_eth_rxconf *rx_conf,
193 struct rte_mempool *mb_pool);
194int vmxnet3_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
195 uint16_t nb_tx_desc, unsigned int socket_id,
196 const struct rte_eth_txconf *tx_conf);
197
198int vmxnet3_dev_rxtx_init(struct rte_eth_dev *dev);
199
200int vmxnet3_rss_configure(struct rte_eth_dev *dev);
201
202uint16_t vmxnet3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
203 uint16_t nb_pkts);
204uint16_t vmxnet3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
205 uint16_t nb_pkts);
206uint16_t vmxnet3_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
207 uint16_t nb_pkts);
208
209#define VMXNET3_SEGS_DYNFIELD_NAME "rte_net_vmxnet3_dynfield_segs"
210typedef uint8_t vmxnet3_segs_dynfield_t;
211extern int vmxnet3_segs_dynfield_offset;
212
213static inline vmxnet3_segs_dynfield_t *
214vmxnet3_segs_dynfield(struct rte_mbuf *mbuf)
215{
216 return RTE_MBUF_DYNFIELD(mbuf, \
217 vmxnet3_segs_dynfield_offset, vmxnet3_segs_dynfield_t *);
218}
219
220#endif
221
