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5#include "fm10k_vf.h"
6
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11
12STATIC s32 fm10k_stop_hw_vf(struct fm10k_hw *hw)
13{
14 u8 *perm_addr = hw->mac.perm_addr;
15 u32 bal = 0, bah = 0, tdlen;
16 s32 err;
17 u16 i;
18
19 DEBUGFUNC("fm10k_stop_hw_vf");
20
21
22 err = fm10k_stop_hw_generic(hw);
23 if (err && err != FM10K_ERR_REQUESTS_PENDING)
24 return err;
25
26
27 if (IS_VALID_ETHER_ADDR(perm_addr)) {
28 bal = (((u32)perm_addr[3]) << 24) |
29 (((u32)perm_addr[4]) << 16) |
30 (((u32)perm_addr[5]) << 8);
31 bah = (((u32)0xFF) << 24) |
32 (((u32)perm_addr[0]) << 16) |
33 (((u32)perm_addr[1]) << 8) |
34 ((u32)perm_addr[2]);
35 }
36
37
38 tdlen = hw->mac.itr_scale << FM10K_TDLEN_ITR_SCALE_SHIFT;
39
40
41
42
43 for (i = 0; i < hw->mac.max_queues; i++) {
44 FM10K_WRITE_REG(hw, FM10K_TDBAL(i), bal);
45 FM10K_WRITE_REG(hw, FM10K_TDBAH(i), bah);
46 FM10K_WRITE_REG(hw, FM10K_RDBAL(i), bal);
47 FM10K_WRITE_REG(hw, FM10K_RDBAH(i), bah);
48
49
50
51
52
53 FM10K_WRITE_REG(hw, FM10K_TDLEN(i), tdlen);
54 }
55
56 return err;
57}
58
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64
65
66STATIC s32 fm10k_reset_hw_vf(struct fm10k_hw *hw)
67{
68 s32 err;
69
70 DEBUGFUNC("fm10k_reset_hw_vf");
71
72
73 err = fm10k_stop_hw_vf(hw);
74 if (err == FM10K_ERR_REQUESTS_PENDING)
75 hw->mac.reset_while_pending++;
76 else if (err)
77 return err;
78
79
80 FM10K_WRITE_REG(hw, FM10K_VFCTRL, FM10K_VFCTRL_RST);
81
82
83 FM10K_WRITE_FLUSH(hw);
84 usec_delay(FM10K_RESET_TIMEOUT);
85
86
87 FM10K_WRITE_REG(hw, FM10K_VFCTRL, 0);
88 if (FM10K_READ_REG(hw, FM10K_VFCTRL) & FM10K_VFCTRL_RST)
89 return FM10K_ERR_RESET_FAILED;
90
91 return FM10K_SUCCESS;
92}
93
94
95
96
97
98
99STATIC s32 fm10k_init_hw_vf(struct fm10k_hw *hw)
100{
101 u32 tqdloc, tqdloc0 = ~FM10K_READ_REG(hw, FM10K_TQDLOC(0));
102 s32 err;
103 u16 i;
104
105 DEBUGFUNC("fm10k_init_hw_vf");
106
107
108 if (!~FM10K_READ_REG(hw, FM10K_TXQCTL(0)) ||
109 !~FM10K_READ_REG(hw, FM10K_RXQCTL(0))) {
110 err = FM10K_ERR_NO_RESOURCES;
111 goto reset_max_queues;
112 }
113
114
115 for (i = 1; tqdloc0 && (i < FM10K_MAX_QUEUES_POOL); i++) {
116
117 tqdloc = ~FM10K_READ_REG(hw, FM10K_TQDLOC(i));
118 if (!tqdloc || (tqdloc == tqdloc0))
119 break;
120
121
122 if (!~FM10K_READ_REG(hw, FM10K_TXQCTL(i)) ||
123 !~FM10K_READ_REG(hw, FM10K_RXQCTL(i)))
124 break;
125 }
126
127
128 err = fm10k_disable_queues_generic(hw, i);
129 if (err)
130 goto reset_max_queues;
131
132
133 hw->mac.max_queues = i;
134
135
136 hw->mac.default_vid = (FM10K_READ_REG(hw, FM10K_TXQCTL(0)) &
137 FM10K_TXQCTL_VID_MASK) >> FM10K_TXQCTL_VID_SHIFT;
138
139
140
141
142 hw->mac.itr_scale = (FM10K_READ_REG(hw, FM10K_TDLEN(0)) &
143 FM10K_TDLEN_ITR_SCALE_MASK) >>
144 FM10K_TDLEN_ITR_SCALE_SHIFT;
145
146 return FM10K_SUCCESS;
147
148reset_max_queues:
149 hw->mac.max_queues = 0;
150
151 return err;
152}
153
154#ifndef NO_IS_SLOT_APPROPRIATE_CHECK
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161
162
163STATIC bool fm10k_is_slot_appropriate_vf(struct fm10k_hw *hw)
164{
165 UNREFERENCED_1PARAMETER(hw);
166 DEBUGFUNC("fm10k_is_slot_appropriate_vf");
167
168 return TRUE;
169}
170
171#endif
172
173const struct fm10k_tlv_attr fm10k_mac_vlan_msg_attr[] = {
174 FM10K_TLV_ATTR_U32(FM10K_MAC_VLAN_MSG_VLAN),
175 FM10K_TLV_ATTR_BOOL(FM10K_MAC_VLAN_MSG_SET),
176 FM10K_TLV_ATTR_MAC_ADDR(FM10K_MAC_VLAN_MSG_MAC),
177 FM10K_TLV_ATTR_MAC_ADDR(FM10K_MAC_VLAN_MSG_DEFAULT_MAC),
178 FM10K_TLV_ATTR_MAC_ADDR(FM10K_MAC_VLAN_MSG_MULTICAST),
179 FM10K_TLV_ATTR_LAST
180};
181
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190
191
192STATIC s32 fm10k_update_vlan_vf(struct fm10k_hw *hw, u32 vid, u8 vsi, bool set)
193{
194 struct fm10k_mbx_info *mbx = &hw->mbx;
195 u32 msg[4];
196
197
198 if (vsi)
199 return FM10K_ERR_PARAM;
200
201
202 if ((vid << 16 | vid) >> 28)
203 return FM10K_ERR_PARAM;
204
205
206 if (!set)
207 vid |= FM10K_VLAN_CLEAR;
208
209
210 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MAC_VLAN);
211 fm10k_tlv_attr_put_u32(msg, FM10K_MAC_VLAN_MSG_VLAN, vid);
212
213
214 return mbx->ops.enqueue_tx(hw, mbx, msg);
215}
216
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224
225s32 fm10k_msg_mac_vlan_vf(struct fm10k_hw *hw, u32 **results,
226 struct fm10k_mbx_info *mbx)
227{
228 u8 perm_addr[ETH_ALEN];
229 u16 vid;
230 s32 err;
231
232 UNREFERENCED_1PARAMETER(mbx);
233 DEBUGFUNC("fm10k_msg_mac_vlan_vf");
234
235
236 err = fm10k_tlv_attr_get_mac_vlan(
237 results[FM10K_MAC_VLAN_MSG_DEFAULT_MAC],
238 perm_addr, &vid);
239 if (err)
240 return err;
241
242 memcpy(hw->mac.perm_addr, perm_addr, ETH_ALEN);
243 hw->mac.default_vid = vid & (FM10K_VLAN_TABLE_VID_MAX - 1);
244 hw->mac.vlan_override = !!(vid & FM10K_VLAN_OVERRIDE);
245
246 return FM10K_SUCCESS;
247}
248
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253
254
255STATIC s32 fm10k_read_mac_addr_vf(struct fm10k_hw *hw)
256{
257 u8 perm_addr[ETH_ALEN];
258 u32 base_addr;
259
260 DEBUGFUNC("fm10k_read_mac_addr_vf");
261
262 base_addr = FM10K_READ_REG(hw, FM10K_TDBAL(0));
263
264
265 if (base_addr << 24)
266 return FM10K_ERR_INVALID_MAC_ADDR;
267
268 perm_addr[3] = (u8)(base_addr >> 24);
269 perm_addr[4] = (u8)(base_addr >> 16);
270 perm_addr[5] = (u8)(base_addr >> 8);
271
272 base_addr = FM10K_READ_REG(hw, FM10K_TDBAH(0));
273
274
275 if ((~base_addr) >> 24)
276 return FM10K_ERR_INVALID_MAC_ADDR;
277
278 perm_addr[0] = (u8)(base_addr >> 16);
279 perm_addr[1] = (u8)(base_addr >> 8);
280 perm_addr[2] = (u8)(base_addr);
281
282 memcpy(hw->mac.perm_addr, perm_addr, ETH_ALEN);
283 memcpy(hw->mac.addr, perm_addr, ETH_ALEN);
284
285 return FM10K_SUCCESS;
286}
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299
300STATIC s32 fm10k_update_uc_addr_vf(struct fm10k_hw *hw, u16 glort,
301 const u8 *mac, u16 vid, bool add, u8 flags)
302{
303 struct fm10k_mbx_info *mbx = &hw->mbx;
304 u32 msg[7];
305
306 DEBUGFUNC("fm10k_update_uc_addr_vf");
307
308 UNREFERENCED_2PARAMETER(glort, flags);
309
310
311 if (vid >= FM10K_VLAN_TABLE_VID_MAX)
312 return FM10K_ERR_PARAM;
313
314
315 if (!IS_VALID_ETHER_ADDR(mac))
316 return FM10K_ERR_PARAM;
317
318
319 if (IS_VALID_ETHER_ADDR(hw->mac.perm_addr) &&
320 memcmp(hw->mac.perm_addr, mac, ETH_ALEN))
321 return FM10K_ERR_PARAM;
322
323
324 if (!add)
325 vid |= FM10K_VLAN_CLEAR;
326
327
328 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MAC_VLAN);
329 fm10k_tlv_attr_put_mac_vlan(msg, FM10K_MAC_VLAN_MSG_MAC, mac, vid);
330
331
332 return mbx->ops.enqueue_tx(hw, mbx, msg);
333}
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345
346STATIC s32 fm10k_update_mc_addr_vf(struct fm10k_hw *hw, u16 glort,
347 const u8 *mac, u16 vid, bool add)
348{
349 struct fm10k_mbx_info *mbx = &hw->mbx;
350 u32 msg[7];
351
352 DEBUGFUNC("fm10k_update_uc_addr_vf");
353
354 UNREFERENCED_1PARAMETER(glort);
355
356
357 if (vid >= FM10K_VLAN_TABLE_VID_MAX)
358 return FM10K_ERR_PARAM;
359
360
361 if (!IS_MULTICAST_ETHER_ADDR(mac))
362 return FM10K_ERR_PARAM;
363
364
365 if (!add)
366 vid |= FM10K_VLAN_CLEAR;
367
368
369 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MAC_VLAN);
370 fm10k_tlv_attr_put_mac_vlan(msg, FM10K_MAC_VLAN_MSG_MULTICAST,
371 mac, vid);
372
373
374 return mbx->ops.enqueue_tx(hw, mbx, msg);
375}
376
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383
384STATIC void fm10k_update_int_moderator_vf(struct fm10k_hw *hw)
385{
386 struct fm10k_mbx_info *mbx = &hw->mbx;
387 u32 msg[1];
388
389
390 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MSIX);
391
392
393 mbx->ops.enqueue_tx(hw, mbx, msg);
394}
395
396
397const struct fm10k_tlv_attr fm10k_lport_state_msg_attr[] = {
398 FM10K_TLV_ATTR_BOOL(FM10K_LPORT_STATE_MSG_DISABLE),
399 FM10K_TLV_ATTR_U8(FM10K_LPORT_STATE_MSG_XCAST_MODE),
400 FM10K_TLV_ATTR_BOOL(FM10K_LPORT_STATE_MSG_READY),
401 FM10K_TLV_ATTR_LAST
402};
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412
413s32 fm10k_msg_lport_state_vf(struct fm10k_hw *hw, u32 **results,
414 struct fm10k_mbx_info *mbx)
415{
416 UNREFERENCED_1PARAMETER(mbx);
417 DEBUGFUNC("fm10k_msg_lport_state_vf");
418
419 hw->mac.dglort_map = !results[FM10K_LPORT_STATE_MSG_READY] ?
420 FM10K_DGLORTMAP_NONE : FM10K_DGLORTMAP_ZERO;
421
422 return FM10K_SUCCESS;
423}
424
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434
435
436STATIC s32 fm10k_update_lport_state_vf(struct fm10k_hw *hw, u16 glort,
437 u16 count, bool enable)
438{
439 struct fm10k_mbx_info *mbx = &hw->mbx;
440 u32 msg[2];
441
442 UNREFERENCED_2PARAMETER(glort, count);
443 DEBUGFUNC("fm10k_update_lport_state_vf");
444
445
446 hw->mac.dglort_map = FM10K_DGLORTMAP_NONE;
447
448
449 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE);
450 if (!enable)
451 fm10k_tlv_attr_put_bool(msg, FM10K_LPORT_STATE_MSG_DISABLE);
452
453
454 return mbx->ops.enqueue_tx(hw, mbx, msg);
455}
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466
467STATIC s32 fm10k_update_xcast_mode_vf(struct fm10k_hw *hw, u16 glort, u8 mode)
468{
469 struct fm10k_mbx_info *mbx = &hw->mbx;
470 u32 msg[3];
471
472 UNREFERENCED_1PARAMETER(glort);
473 DEBUGFUNC("fm10k_update_xcast_mode_vf");
474
475 if (mode > FM10K_XCAST_MODE_NONE)
476 return FM10K_ERR_PARAM;
477
478
479 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE);
480 fm10k_tlv_attr_put_u8(msg, FM10K_LPORT_STATE_MSG_XCAST_MODE, mode);
481
482
483 return mbx->ops.enqueue_tx(hw, mbx, msg);
484}
485
486const struct fm10k_tlv_attr fm10k_1588_msg_attr[] = {
487 FM10K_TLV_ATTR_U64(FM10K_1588_MSG_CLK_OFFSET),
488 FM10K_TLV_ATTR_LAST
489};
490
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498
499
500void fm10k_update_hw_stats_vf(struct fm10k_hw *hw,
501 struct fm10k_hw_stats *stats)
502{
503 DEBUGFUNC("fm10k_update_hw_stats_vf");
504
505 fm10k_update_hw_stats_q(hw, stats->q, 0, hw->mac.max_queues);
506}
507
508
509
510
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513
514
515void fm10k_rebind_hw_stats_vf(struct fm10k_hw *hw,
516 struct fm10k_hw_stats *stats)
517{
518 DEBUGFUNC("fm10k_rebind_hw_stats_vf");
519
520
521 fm10k_unbind_hw_stats_q(stats->q, 0, hw->mac.max_queues);
522
523
524 fm10k_update_hw_stats_vf(hw, stats);
525}
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535
536STATIC s32 fm10k_configure_dglort_map_vf(struct fm10k_hw *hw,
537 struct fm10k_dglort_cfg *dglort)
538{
539 UNREFERENCED_1PARAMETER(hw);
540 DEBUGFUNC("fm10k_configure_dglort_map_vf");
541
542
543 if (!dglort)
544 return FM10K_ERR_PARAM;
545
546
547
548 return FM10K_SUCCESS;
549}
550
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560
561
562STATIC s32 fm10k_adjust_systime_vf(struct fm10k_hw *hw, s32 ppb)
563{
564 UNREFERENCED_1PARAMETER(hw);
565 DEBUGFUNC("fm10k_adjust_systime_vf");
566
567
568
569
570
571
572 return ppb ? FM10K_ERR_PARAM : FM10K_SUCCESS;
573}
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583
584
585static u64 fm10k_read_systime_vf(struct fm10k_hw *hw)
586{
587 u32 systime_l, systime_h, systime_tmp;
588
589 systime_h = fm10k_read_reg(hw, FM10K_VFSYSTIME + 1);
590
591 do {
592 systime_tmp = systime_h;
593 systime_l = fm10k_read_reg(hw, FM10K_VFSYSTIME);
594 systime_h = fm10k_read_reg(hw, FM10K_VFSYSTIME + 1);
595 } while (systime_tmp != systime_h);
596
597 return ((u64)systime_h << 32) | systime_l;
598}
599
600static const struct fm10k_msg_data fm10k_msg_data_vf[] = {
601 FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),
602 FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_msg_mac_vlan_vf),
603 FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_msg_lport_state_vf),
604 FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
605};
606
607
608
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611
612
613
614s32 fm10k_init_ops_vf(struct fm10k_hw *hw)
615{
616 struct fm10k_mac_info *mac = &hw->mac;
617
618 DEBUGFUNC("fm10k_init_ops_vf");
619
620 fm10k_init_ops_generic(hw);
621
622 mac->ops.reset_hw = &fm10k_reset_hw_vf;
623 mac->ops.init_hw = &fm10k_init_hw_vf;
624 mac->ops.start_hw = &fm10k_start_hw_generic;
625 mac->ops.stop_hw = &fm10k_stop_hw_vf;
626#ifndef NO_IS_SLOT_APPROPRIATE_CHECK
627 mac->ops.is_slot_appropriate = &fm10k_is_slot_appropriate_vf;
628#endif
629 mac->ops.update_vlan = &fm10k_update_vlan_vf;
630 mac->ops.read_mac_addr = &fm10k_read_mac_addr_vf;
631 mac->ops.update_uc_addr = &fm10k_update_uc_addr_vf;
632 mac->ops.update_mc_addr = &fm10k_update_mc_addr_vf;
633 mac->ops.update_xcast_mode = &fm10k_update_xcast_mode_vf;
634 mac->ops.update_int_moderator = &fm10k_update_int_moderator_vf;
635 mac->ops.update_lport_state = &fm10k_update_lport_state_vf;
636 mac->ops.update_hw_stats = &fm10k_update_hw_stats_vf;
637 mac->ops.rebind_hw_stats = &fm10k_rebind_hw_stats_vf;
638 mac->ops.configure_dglort_map = &fm10k_configure_dglort_map_vf;
639 mac->ops.get_host_state = &fm10k_get_host_state_generic;
640 mac->ops.adjust_systime = &fm10k_adjust_systime_vf;
641 mac->ops.read_systime = &fm10k_read_systime_vf;
642
643 mac->max_msix_vectors = fm10k_get_pcie_msix_count_generic(hw);
644
645 return fm10k_pfvf_mbx_init(hw, &hw->mbx, fm10k_msg_data_vf, 0);
646}
647