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5#ifndef _FM10K_H_
6#define _FM10K_H_
7
8#include <stdint.h>
9#include <rte_mbuf.h>
10#include <rte_mempool.h>
11#include <rte_malloc.h>
12#include <rte_spinlock.h>
13#include "fm10k_logs.h"
14#include "base/fm10k_type.h"
15
16
17#define FM10K_ALIGN_RX_DESC 128
18#define FM10K_ALIGN_TX_DESC 128
19
20
21#define FM10K_MAX_PKT_SIZE (15 * 1024)
22
23
24#define FM10K_MIN_RX_BUF_SIZE 256
25
26
27#define FM10K_MAX_VF_NUM 64
28
29
30#define FM10K_MULT_RX_DESC FM10K_REQ_RX_DESCRIPTOR_MULTIPLE
31#define FM10K_MULT_TX_DESC FM10K_REQ_TX_DESCRIPTOR_MULTIPLE
32
33
34#define FM10K_MAX_RX_RING_SZ (512 * 1024)
35#define FM10K_MAX_TX_RING_SZ (512 * 1024)
36
37
38#define FM10K_MIN_RX_DESC 32
39#define FM10K_MIN_TX_DESC 32
40#define FM10K_MAX_RX_DESC (FM10K_MAX_RX_RING_SZ / sizeof(union fm10k_rx_desc))
41#define FM10K_MAX_TX_DESC (FM10K_MAX_TX_RING_SZ / sizeof(struct fm10k_tx_desc))
42
43#define FM10K_TX_MAX_SEG UINT8_MAX
44#define FM10K_TX_MAX_MTU_SEG UINT8_MAX
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50
51
52#define FM10K_RX_DATABUF_ALIGN 512
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59
60#define FM10K_RX_FREE_THRESH_DEFAULT(rxq) 32
61#define FM10K_RX_FREE_THRESH_MIN(rxq) 1
62#define FM10K_RX_FREE_THRESH_MAX(rxq) ((rxq)->nb_desc - 1)
63#define FM10K_RX_FREE_THRESH_DIV(rxq) ((rxq)->nb_desc)
64
65#define FM10K_TX_FREE_THRESH_DEFAULT(txq) 32
66#define FM10K_TX_FREE_THRESH_MIN(txq) 1
67#define FM10K_TX_FREE_THRESH_MAX(txq) ((txq)->nb_desc - 3)
68#define FM10K_TX_FREE_THRESH_DIV(txq) 0
69
70#define FM10K_DEFAULT_RX_PTHRESH 8
71#define FM10K_DEFAULT_RX_HTHRESH 8
72#define FM10K_DEFAULT_RX_WTHRESH 0
73
74#define FM10K_DEFAULT_TX_PTHRESH 32
75#define FM10K_DEFAULT_TX_HTHRESH 0
76#define FM10K_DEFAULT_TX_WTHRESH 0
77
78#define FM10K_TX_RS_THRESH_DEFAULT(txq) 32
79#define FM10K_TX_RS_THRESH_MIN(txq) 1
80#define FM10K_TX_RS_THRESH_MAX(txq) \
81 RTE_MIN(((txq)->nb_desc - 2), (txq)->free_thresh)
82#define FM10K_TX_RS_THRESH_DIV(txq) ((txq)->nb_desc)
83
84
85#define FM10K_MAX_MACADDR_NUM 64
86
87#define FM10K_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
88#define FM10K_VFTA_SIZE (4096 / FM10K_UINT32_BIT_SIZE)
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94
95#define FM10K_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
96#define FM10K_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
97
98#define RTE_FM10K_RXQ_REARM_THRESH 32
99#define RTE_FM10K_VPMD_TX_BURST 32
100#define RTE_FM10K_MAX_RX_BURST RTE_FM10K_RXQ_REARM_THRESH
101#define RTE_FM10K_TX_MAX_FREE_BUF_SZ 64
102#define RTE_FM10K_DESCS_PER_LOOP 4
103
104#define FM10K_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
105#define FM10K_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
106
107struct fm10k_macvlan_filter_info {
108 uint16_t vlan_num;
109 uint16_t mac_num;
110 uint16_t nb_queue_pools;
111
112 uint8_t mac_vmdq_id[FM10K_MAX_MACADDR_NUM];
113 uint32_t vfta[FM10K_VFTA_SIZE];
114};
115
116struct fm10k_dev_info {
117 volatile uint32_t enable;
118 volatile uint32_t glort;
119
120 rte_spinlock_t mbx_lock;
121 struct fm10k_macvlan_filter_info macvlan;
122
123 bool rx_vec_allowed;
124 bool sm_down;
125};
126
127
128
129
130struct fm10k_adapter {
131 struct fm10k_hw hw;
132 struct fm10k_hw_stats stats;
133 struct fm10k_dev_info info;
134};
135
136#define FM10K_DEV_PRIVATE_TO_HW(adapter) \
137 (&((struct fm10k_adapter *)adapter)->hw)
138
139#define FM10K_DEV_PRIVATE_TO_STATS(adapter) \
140 (&((struct fm10k_adapter *)adapter)->stats)
141
142#define FM10K_DEV_PRIVATE_TO_INFO(adapter) \
143 (&((struct fm10k_adapter *)adapter)->info)
144
145#define FM10K_DEV_PRIVATE_TO_MBXLOCK(adapter) \
146 (&(((struct fm10k_adapter *)adapter)->info.mbx_lock))
147
148#define FM10K_DEV_PRIVATE_TO_MACVLAN(adapter) \
149 (&(((struct fm10k_adapter *)adapter)->info.macvlan))
150
151struct fm10k_rx_queue {
152 struct rte_mempool *mp;
153 struct rte_mbuf **sw_ring;
154 volatile union fm10k_rx_desc *hw_ring;
155 struct rte_mbuf *pkt_first_seg;
156 struct rte_mbuf *pkt_last_seg;
157 uint64_t hw_ring_phys_addr;
158 uint64_t mbuf_initializer;
159
160 struct rte_mbuf fake_mbuf;
161 uint16_t next_dd;
162 uint16_t next_alloc;
163 uint16_t next_trigger;
164 uint16_t alloc_thresh;
165 volatile uint32_t *tail_ptr;
166 uint16_t nb_desc;
167
168 uint16_t nb_fake_desc;
169 uint16_t queue_id;
170
171 uint16_t rxrearm_nb;
172 uint16_t rxrearm_start;
173 uint16_t rx_using_sse;
174 uint16_t port_id;
175 uint8_t drop_en;
176 uint8_t rx_deferred_start;
177 uint16_t rx_ftag_en;
178 uint64_t offloads;
179};
180
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184
185struct fifo {
186 uint16_t *list;
187 uint16_t *head;
188 uint16_t *tail;
189 uint16_t *endp;
190};
191
192struct fm10k_txq_ops;
193
194struct fm10k_tx_queue {
195 struct rte_mbuf **sw_ring;
196 struct fm10k_tx_desc *hw_ring;
197 uint64_t hw_ring_phys_addr;
198 struct fifo rs_tracker;
199 const struct fm10k_txq_ops *ops;
200 uint16_t last_free;
201 uint16_t next_free;
202 uint16_t nb_free;
203 uint16_t nb_used;
204 uint16_t free_thresh;
205 uint16_t rs_thresh;
206
207 uint16_t next_rs;
208 uint16_t next_dd;
209 volatile uint32_t *tail_ptr;
210 uint64_t offloads;
211 uint16_t nb_desc;
212 uint16_t port_id;
213 uint8_t tx_deferred_start;
214 uint16_t queue_id;
215 uint16_t tx_ftag_en;
216};
217
218struct fm10k_txq_ops {
219 void (*reset)(struct fm10k_tx_queue *txq);
220};
221
222#define MBUF_DMA_ADDR(mb) \
223 ((uint64_t) ((mb)->buf_iova + (mb)->data_off))
224
225
226#define MBUF_DMA_ADDR_DEFAULT(mb) \
227 ((uint64_t) RTE_ALIGN(((mb)->buf_iova + RTE_PKTMBUF_HEADROOM),\
228 FM10K_RX_DATABUF_ALIGN))
229
230static inline void fifo_reset(struct fifo *fifo, uint32_t len)
231{
232 fifo->head = fifo->tail = fifo->list;
233 fifo->endp = fifo->list + len;
234}
235
236static inline void fifo_insert(struct fifo *fifo, uint16_t val)
237{
238 *fifo->head = val;
239 if (++fifo->head == fifo->endp)
240 fifo->head = fifo->list;
241}
242
243
244
245static inline uint16_t fifo_peek(struct fifo *fifo)
246{
247 return *fifo->tail;
248}
249
250static inline uint16_t fifo_remove(struct fifo *fifo)
251{
252 uint16_t val;
253 val = *fifo->tail;
254 if (++fifo->tail == fifo->endp)
255 fifo->tail = fifo->list;
256 return val;
257}
258
259static inline void
260fm10k_pktmbuf_reset(struct rte_mbuf *mb, uint16_t in_port)
261{
262 rte_mbuf_refcnt_set(mb, 1);
263 mb->next = NULL;
264 mb->nb_segs = 1;
265
266
267 mb->data_off = (uint16_t)(RTE_PTR_ALIGN((char *)mb->buf_addr +
268 RTE_PKTMBUF_HEADROOM, FM10K_RX_DATABUF_ALIGN)
269 - (char *)mb->buf_addr);
270 mb->port = in_port;
271}
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293static inline int
294fm10k_addr_alignment_valid(struct rte_mbuf *mb)
295{
296 uint64_t addr = MBUF_DMA_ADDR_DEFAULT(mb);
297 uint64_t boundary1, boundary2;
298
299
300 if (RTE_ALIGN(addr, FM10K_RX_DATABUF_ALIGN) == addr)
301 return 1;
302
303
304 if (RTE_ALIGN(addr, 8) == addr) {
305 boundary1 = RTE_ALIGN_FLOOR(addr, 4096);
306 boundary2 = RTE_ALIGN_FLOOR(addr + RTE_ETHER_MAX_VLAN_FRAME_LEN,
307 4096);
308 if (boundary1 == boundary2)
309 return 1;
310 }
311
312 PMD_INIT_LOG(ERR, "Error: Invalid buffer alignment!");
313
314 return 0;
315}
316
317
318uint16_t fm10k_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
319 uint16_t nb_pkts);
320
321uint16_t fm10k_recv_scattered_pkts(void *rx_queue,
322 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
323
324uint32_t
325fm10k_dev_rx_queue_count(void *rx_queue);
326
327int
328fm10k_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
329
330int
331fm10k_dev_tx_descriptor_status(void *rx_queue, uint16_t offset);
332
333
334uint16_t fm10k_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
335 uint16_t nb_pkts);
336
337uint16_t fm10k_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
338 uint16_t nb_pkts);
339
340int fm10k_rxq_vec_setup(struct fm10k_rx_queue *rxq);
341int fm10k_rx_vec_condition_check(struct rte_eth_dev *);
342void fm10k_rx_queue_release_mbufs_vec(struct fm10k_rx_queue *rxq);
343uint16_t fm10k_recv_pkts_vec(void *, struct rte_mbuf **, uint16_t);
344uint16_t fm10k_recv_scattered_pkts_vec(void *, struct rte_mbuf **,
345 uint16_t);
346uint16_t fm10k_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
347 uint16_t nb_pkts);
348void fm10k_txq_vec_setup(struct fm10k_tx_queue *txq);
349int fm10k_tx_vec_condition_check(struct fm10k_tx_queue *txq);
350
351#endif
352