1/* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Intel Corporation 3 */ 4 5/** 6 * @file Header file containing DPDK compilation parameters 7 * 8 * Header file containing DPDK compilation parameters. Also include the 9 * meson-generated header file containing the detected parameters that 10 * are variable across builds or build environments. 11 */ 12#ifndef _RTE_CONFIG_H_ 13#define _RTE_CONFIG_H_ 14 15#include <rte_build_config.h> 16 17/* legacy defines */ 18#ifdef RTE_EXEC_ENV_LINUX 19#define RTE_EXEC_ENV_LINUXAPP 1 20#endif 21#ifdef RTE_EXEC_ENV_FREEBSD 22#define RTE_EXEC_ENV_BSDAPP 1 23#endif 24 25/* String that appears before the version number */ 26#define RTE_VER_PREFIX "DPDK" 27 28/****** library defines ********/ 29 30/* EAL defines */ 31#define RTE_MAX_HEAPS 32 32#define RTE_MAX_MEMSEG_LISTS 128 33#define RTE_MAX_MEMSEG_PER_LIST 8192 34#define RTE_MAX_MEM_MB_PER_LIST 32768 35#define RTE_MAX_MEMSEG_PER_TYPE 32768 36#define RTE_MAX_MEM_MB_PER_TYPE 65536 37#define RTE_MAX_MEMZONE 2560 38#define RTE_MAX_TAILQ 32 39#define RTE_LOG_DP_LEVEL RTE_LOG_INFO 40#define RTE_BACKTRACE 1 41#define RTE_MAX_VFIO_CONTAINERS 64 42 43/* bsd module defines */ 44#define RTE_CONTIGMEM_MAX_NUM_BUFS 64 45#define RTE_CONTIGMEM_DEFAULT_NUM_BUFS 1 46#define RTE_CONTIGMEM_DEFAULT_BUF_SIZE (512*1024*1024) 47 48/* mempool defines */ 49#define RTE_MEMPOOL_CACHE_MAX_SIZE 512 50 51/* mbuf defines */ 52#define RTE_MBUF_DEFAULT_MEMPOOL_OPS "ring_mp_mc" 53#define RTE_PKTMBUF_HEADROOM 128 54 55/* ether defines */ 56#define RTE_MAX_QUEUES_PER_PORT 1024 57#define RTE_ETHDEV_QUEUE_STAT_CNTRS 16 /* max 256 */ 58#define RTE_ETHDEV_RXTX_CALLBACKS 1 59#define RTE_MAX_MULTI_HOST_CTRLS 4 60 61/* cryptodev defines */ 62#define RTE_CRYPTO_MAX_DEVS 64 63#define RTE_CRYPTODEV_NAME_LEN 64 64#define RTE_CRYPTO_CALLBACKS 1 65 66/* compressdev defines */ 67#define RTE_COMPRESS_MAX_DEVS 64 68 69/* regexdev defines */ 70#define RTE_MAX_REGEXDEV_DEVS 32 71 72/* eventdev defines */ 73#define RTE_EVENT_MAX_DEVS 16 74#define RTE_EVENT_MAX_PORTS_PER_DEV 255 75#define RTE_EVENT_MAX_QUEUES_PER_DEV 255 76#define RTE_EVENT_TIMER_ADAPTER_NUM_MAX 32 77#define RTE_EVENT_ETH_INTR_RING_SIZE 1024 78#define RTE_EVENT_CRYPTO_ADAPTER_MAX_INSTANCE 32 79#define RTE_EVENT_ETH_TX_ADAPTER_MAX_INSTANCE 32 80 81/* rawdev defines */ 82#define RTE_RAWDEV_MAX_DEVS 64 83 84/* ip_fragmentation defines */ 85#define RTE_LIBRTE_IP_FRAG_MAX_FRAG 8 86// RTE_LIBRTE_IP_FRAG_TBL_STAT is not set 87 88/* rte_power defines */ 89#define RTE_MAX_LCORE_FREQS 64 90 91/* rte_sched defines */ 92// RTE_SCHED_CMAN is not set 93 94/* rte_graph defines */ 95#define RTE_GRAPH_BURST_SIZE 256 96#define RTE_LIBRTE_GRAPH_STATS 1 97 98/****** driver defines ********/ 99 100/* Packet prefetching in PMDs */ 101#define RTE_PMD_PACKET_PREFETCH 1 102 103/* QuickAssist device */ 104/* Max. number of QuickAssist devices which can be attached */ 105#define RTE_PMD_QAT_MAX_PCI_DEVICES 48 106#define RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS 16 107#define RTE_PMD_QAT_COMP_IM_BUFFER_SIZE 65536 108 109/* virtio crypto defines */ 110#define RTE_MAX_VIRTIO_CRYPTO 32 111 112/* DPAA SEC max cryptodev devices*/ 113#define RTE_LIBRTE_DPAA_MAX_CRYPTODEV 4 114 115/* fm10k defines */ 116#define RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE 1 117 118/* hns3 defines */ 119#define RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF 256 120 121/* i40e defines */ 122#define RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC 1 123// RTE_LIBRTE_I40E_16BYTE_RX_DESC is not set 124#define RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF 64 125#define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4 126#define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM 4 127 128/* Ring net PMD settings */ 129#define RTE_PMD_RING_MAX_RX_RINGS 16 130#define RTE_PMD_RING_MAX_TX_RINGS 16 131 132/* QEDE PMD defines */ 133#define RTE_LIBRTE_QEDE_FW "" 134 135/* DLB2 defines */ 136// RTE_LIBRTE_PMD_DLB2_QUELL_STATS is not set 137 138#endif /* _RTE_CONFIG_H_ */ 139