LXR dpdk/drivers/baseband/acc100/acc100

   1/* SPDX-License-Identifier: BSD-3-Clause
   2 * Copyright(c) 2020 Intel Corporation
   3 */
   4
   5#ifndef _RTE_ACC100_PMD_H_
   6#define _RTE_ACC100_PMD_H_
   7
   8#include "acc100_pf_enum.h"
   9#include "acc100_vf_enum.h"
  10#include "rte_acc100_cfg.h"
  11
  12/* Helper macro for logging */
  13#define rte_bbdev_log(level, fmt, ...) \
  14        rte_log(RTE_LOG_ ## level, acc100_logtype, fmt "\n", \
  15                ##__VA_ARGS__)
  16
  17#ifdef RTE_LIBRTE_BBDEV_DEBUG
  18#define rte_bbdev_log_debug(fmt, ...) \
  19                rte_bbdev_log(DEBUG, "acc100_pmd: " fmt, \
  20                ##__VA_ARGS__)
  21#else
  22#define rte_bbdev_log_debug(fmt, ...)
  23#endif
  24
  25#define ACC100_VARIANT 0
  26#define ACC101_VARIANT 1
  27
  28/* ACC100 PF and VF driver names */
  29#define ACC100PF_DRIVER_NAME           intel_acc100_pf
  30#define ACC100VF_DRIVER_NAME           intel_acc100_vf
  31
  32/* ACC100 PCI vendor & device IDs */
  33#define ACC100_VENDOR_ID           (0x8086)
  34#define ACC100_PF_DEVICE_ID        (0x0d5c)
  35#define ACC100_VF_DEVICE_ID        (0x0d5d)
  36
  37/* Values used in filling in descriptors */
  38#define ACC100_DMA_DESC_TYPE           2
  39#define ACC100_DMA_CODE_BLK_MODE       0
  40#define ACC100_DMA_BLKID_FCW           1
  41#define ACC100_DMA_BLKID_IN            2
  42#define ACC100_DMA_BLKID_OUT_ENC       1
  43#define ACC100_DMA_BLKID_OUT_HARD      1
  44#define ACC100_DMA_BLKID_OUT_SOFT      2
  45#define ACC100_DMA_BLKID_OUT_HARQ      3
  46#define ACC100_DMA_BLKID_IN_HARQ       3
  47
  48/* Values used in filling in decode FCWs */
  49#define ACC100_FCW_TD_VER              1
  50#define ACC100_FCW_TD_EXT_COLD_REG_EN  1
  51#define ACC100_FCW_TD_AUTOMAP          0x0f
  52#define ACC100_FCW_TD_RVIDX_0          2
  53#define ACC100_FCW_TD_RVIDX_1          26
  54#define ACC100_FCW_TD_RVIDX_2          50
  55#define ACC100_FCW_TD_RVIDX_3          74
  56
  57/* Values used in writing to the registers */
  58#define ACC100_REG_IRQ_EN_ALL          0x1FF83FF  /* Enable all interrupts */
  59
  60/* ACC100 Specific Dimensioning */
  61#define ACC100_SIZE_64MBYTE            (64*1024*1024)
  62/* Number of elements in an Info Ring */
  63#define ACC100_INFO_RING_NUM_ENTRIES   1024
  64/* Number of elements in HARQ layout memory */
  65#define ACC100_HARQ_LAYOUT             (64*1024*1024)
  66/* Assume offset for HARQ in memory */
  67#define ACC100_HARQ_OFFSET             (32*1024)
  68#define ACC100_HARQ_OFFSET_SHIFT       15
  69#define ACC100_HARQ_OFFSET_MASK        0x7ffffff
  70/* Mask used to calculate an index in an Info Ring array (not a byte offset) */
  71#define ACC100_INFO_RING_MASK          (ACC100_INFO_RING_NUM_ENTRIES-1)
  72/* Number of Virtual Functions ACC100 supports */
  73#define ACC100_NUM_VFS                  16
  74#define ACC100_NUM_QGRPS                8
  75#define ACC100_NUM_QGRPS_PER_WORD       8
  76#define ACC100_NUM_AQS                  16
  77#define MAX_ENQ_BATCH_SIZE              255
  78/* All ACC100 Registers alignment are 32bits = 4B */
  79#define ACC100_BYTES_IN_WORD                 4
  80#define ACC100_MAX_E_MBUF                64000
  81
  82#define ACC100_GRP_ID_SHIFT    10 /* Queue Index Hierarchy */
  83#define ACC100_VF_ID_SHIFT     4  /* Queue Index Hierarchy */
  84#define ACC100_VF_OFFSET_QOS   16 /* offset in Memory specific to QoS Mon */
  85#define ACC100_TMPL_PRI_0      0x03020100
  86#define ACC100_TMPL_PRI_1      0x07060504
  87#define ACC100_TMPL_PRI_2      0x0b0a0908
  88#define ACC100_TMPL_PRI_3      0x0f0e0d0c
  89#define ACC100_QUEUE_ENABLE    0x80000000  /* Bit to mark Queue as Enabled */
  90#define ACC100_WORDS_IN_ARAM_SIZE (128 * 1024 / 4)
  91#define ACC100_FDONE    0x80000000
  92#define ACC100_SDONE    0x40000000
  93
  94#define ACC100_NUM_TMPL       32
  95/* Mapping of signals for the available engines */
  96#define ACC100_SIG_UL_5G      0
  97#define ACC100_SIG_UL_5G_LAST 7
  98#define ACC100_SIG_DL_5G      13
  99#define ACC100_SIG_DL_5G_LAST 15
 100#define ACC100_SIG_UL_4G      16
 101#define ACC100_SIG_UL_4G_LAST 21
 102#define ACC100_SIG_DL_4G      27
 103#define ACC100_SIG_DL_4G_LAST 31
 104#define ACC100_NUM_ACCS       5
 105#define ACC100_ACCMAP_0       0
 106#define ACC100_ACCMAP_1       2
 107#define ACC100_ACCMAP_2       1
 108#define ACC100_ACCMAP_3       3
 109#define ACC100_ACCMAP_4       4
 110#define ACC100_PF_VAL         2
 111
 112/* max number of iterations to allocate memory block for all rings */
 113#define ACC100_SW_RING_MEM_ALLOC_ATTEMPTS 5
 114#define ACC100_MAX_QUEUE_DEPTH            1024
 115#define ACC100_DMA_MAX_NUM_POINTERS       14
 116#define ACC100_DMA_MAX_NUM_POINTERS_IN    7
 117#define ACC100_DMA_DESC_PADDING           8
 118#define ACC100_FCW_PADDING                12
 119#define ACC100_DESC_FCW_OFFSET            192
 120#define ACC100_DESC_SIZE                  256
 121#define ACC100_DESC_OFFSET                (ACC100_DESC_SIZE / 64)
 122#define ACC100_FCW_TE_BLEN                32
 123#define ACC100_FCW_TD_BLEN                24
 124#define ACC100_FCW_LE_BLEN                32
 125#define ACC100_FCW_LD_BLEN                36
 126#define ACC100_5GUL_SIZE_0                16
 127#define ACC100_5GUL_SIZE_1                40
 128#define ACC100_5GUL_OFFSET_0              36
 129
 130#define ACC100_FCW_VER         2
 131#define ACC100_MUX_5GDL_DESC   6
 132#define ACC100_CMP_ENC_SIZE    20
 133#define ACC100_CMP_DEC_SIZE    24
 134#define ACC100_ENC_OFFSET     (32)
 135#define ACC100_DEC_OFFSET     (80)
 136#define ACC100_EXT_MEM /* Default option with memory external to CPU */
 137#define ACC100_HARQ_OFFSET_THRESHOLD 1024
 138
 139/* Constants from K0 computation from 3GPP 38.212 Table 5.4.2.1-2 */
 140#define ACC100_N_ZC_1 66 /* N = 66 Zc for BG 1 */
 141#define ACC100_N_ZC_2 50 /* N = 50 Zc for BG 2 */
 142#define ACC100_K0_1_1 17 /* K0 fraction numerator for rv 1 and BG 1 */
 143#define ACC100_K0_1_2 13 /* K0 fraction numerator for rv 1 and BG 2 */
 144#define ACC100_K0_2_1 33 /* K0 fraction numerator for rv 2 and BG 1 */
 145#define ACC100_K0_2_2 25 /* K0 fraction numerator for rv 2 and BG 2 */
 146#define ACC100_K0_3_1 56 /* K0 fraction numerator for rv 3 and BG 1 */
 147#define ACC100_K0_3_2 43 /* K0 fraction numerator for rv 3 and BG 2 */
 148
 149/* ACC100 Configuration */
 150#define ACC100_DDR_ECC_ENABLE
 151#define ACC100_CFG_DMA_ERROR    0x3D7
 152#define ACC100_CFG_AXI_CACHE    0x11
 153#define ACC100_CFG_QMGR_HI_P    0x0F0F
 154#define ACC100_CFG_PCI_AXI      0xC003
 155#define ACC100_CFG_PCI_BRIDGE   0x40006033
 156#define ACC100_QUAD_NUMS        4
 157#define ACC100_LANES_PER_QUAD   4
 158#define ACC100_PCIE_LANE_OFFSET 0x200
 159#define ACC100_PCIE_QUAD_OFFSET 0x2000
 160#define ACC100_PCS_EQ           0x6007
 161#define ACC100_ADAPT            0x8400
 162#define ACC100_ENGINE_OFFSET    0x1000
 163#define ACC100_RESET_HI         0x20100
 164#define ACC100_RESET_LO         0x20000
 165#define ACC100_RESET_HARD       0x1FF
 166#define ACC100_ENGINES_MAX      9
 167#define ACC100_LONG_WAIT        1000
 168#define ACC100_GPEX_AXIMAP_NUM  17
 169#define ACC100_CLOCK_GATING_EN  0x30000
 170#define ACC100_FABRIC_MODE      0xB
 171/* DDR Size per VF - 512MB by default
 172 * Can be increased up to 4 GB with single PF/VF
 173 */
 174#define ACC100_HARQ_DDR         (512 * 1)
 175#define ACC100_PRQ_DDR_VER       0x10092020
 176#define ACC100_MS_IN_US         (1000)
 177#define ACC100_DDR_TRAINING_MAX (5000)
 178
 179/* ACC100 DMA Descriptor triplet */
 180struct acc100_dma_triplet {
 181        uint64_t address;
 182        uint32_t blen:20,
 183                res0:4,
 184                last:1,
 185                dma_ext:1,
 186                res1:2,
 187                blkid:4;
 188} __rte_packed;
 189
 190/* ACC100 DMA Response Descriptor */
 191union acc100_dma_rsp_desc {
 192        uint32_t val;
 193        struct {
 194                uint32_t crc_status:1,
 195                        synd_ok:1,
 196                        dma_err:1,
 197                        neg_stop:1,
 198                        fcw_err:1,
 199                        output_err:1,
 200                        input_err:1,
 201                        timestampEn:1,
 202                        iterCountFrac:8,
 203                        iter_cnt:8,
 204                        rsrvd3:6,
 205                        sdone:1,
 206                        fdone:1;
 207                uint32_t add_info_0;
 208                uint32_t add_info_1;
 209        };
 210};
 211
 212
 213/* ACC100 Queue Manager Enqueue PCI Register */
 214union acc100_enqueue_reg_fmt {
 215        uint32_t val;
 216        struct {
 217                uint32_t num_elem:8,
 218                        addr_offset:3,
 219                        rsrvd:1,
 220                        req_elem_addr:20;
 221        };
 222};
 223
 224/* FEC 4G Uplink Frame Control Word */
 225struct __rte_packed acc100_fcw_td {
 226        uint8_t fcw_ver:4,
 227                num_maps:4; /* Unused */
 228        uint8_t filler:6, /* Unused */
 229                rsrvd0:1,
 230                bypass_sb_deint:1;
 231        uint16_t k_pos;
 232        uint16_t k_neg; /* Unused */
 233        uint8_t c_neg; /* Unused */
 234        uint8_t c; /* Unused */
 235        uint32_t ea; /* Unused */
 236        uint32_t eb; /* Unused */
 237        uint8_t cab; /* Unused */
 238        uint8_t k0_start_col; /* Unused */
 239        uint8_t rsrvd1;
 240        uint8_t code_block_mode:1, /* Unused */
 241                turbo_crc_type:1,
 242                rsrvd2:3,
 243                bypass_teq:1, /* Unused */
 244                soft_output_en:1, /* Unused */
 245                ext_td_cold_reg_en:1;
 246        union { /* External Cold register */
 247                uint32_t ext_td_cold_reg;
 248                struct {
 249                        uint32_t min_iter:4, /* Unused */
 250                                max_iter:4,
 251                                ext_scale:5, /* Unused */
 252                                rsrvd3:3,
 253                                early_stop_en:1, /* Unused */
 254                                sw_soft_out_dis:1, /* Unused */
 255                                sw_et_cont:1, /* Unused */
 256                                sw_soft_out_saturation:1, /* Unused */
 257                                half_iter_on:1, /* Unused */
 258                                raw_decoder_input_on:1, /* Unused */
 259                                rsrvd4:10;
 260                };
 261        };
 262};
 263
 264/* FEC 5GNR Uplink Frame Control Word */
 265struct __rte_packed acc100_fcw_ld {
 266        uint32_t FCWversion:4,
 267                qm:4,
 268                nfiller:11,
 269                BG:1,
 270                Zc:9,
 271                res0:1,
 272                synd_precoder:1,
 273                synd_post:1;
 274        uint32_t ncb:16,
 275                k0:16;
 276        uint32_t rm_e:24,
 277                hcin_en:1,
 278                hcout_en:1,
 279                crc_select:1,
 280                bypass_dec:1,
 281                bypass_intlv:1,
 282                so_en:1,
 283                so_bypass_rm:1,
 284                so_bypass_intlv:1;
 285        uint32_t hcin_offset:16,
 286                hcin_size0:16;
 287        uint32_t hcin_size1:16,
 288                hcin_decomp_mode:3,
 289                llr_pack_mode:1,
 290                hcout_comp_mode:3,
 291                res2:1,
 292                dec_convllr:4,
 293                hcout_convllr:4;
 294        uint32_t itmax:7,
 295                itstop:1,
 296                so_it:7,
 297                res3:1,
 298                hcout_offset:16;
 299        uint32_t hcout_size0:16,
 300                hcout_size1:16;
 301        uint32_t gain_i:8,
 302                gain_h:8,
 303                negstop_th:16;
 304        uint32_t negstop_it:7,
 305                negstop_en:1,
 306                res4:24;
 307};
 308
 309/* FEC 4G Downlink Frame Control Word */
 310struct __rte_packed acc100_fcw_te {
 311        uint16_t k_neg;
 312        uint16_t k_pos;
 313        uint8_t c_neg;
 314        uint8_t c;
 315        uint8_t filler;
 316        uint8_t cab;
 317        uint32_t ea:17,
 318                rsrvd0:15;
 319        uint32_t eb:17,
 320                rsrvd1:15;
 321        uint16_t ncb_neg;
 322        uint16_t ncb_pos;
 323        uint8_t rv_idx0:2,
 324                rsrvd2:2,
 325                rv_idx1:2,
 326                rsrvd3:2;
 327        uint8_t bypass_rv_idx0:1,
 328                bypass_rv_idx1:1,
 329                bypass_rm:1,
 330                rsrvd4:5;
 331        uint8_t rsrvd5:1,
 332                rsrvd6:3,
 333                code_block_crc:1,
 334                rsrvd7:3;
 335        uint8_t code_block_mode:1,
 336                rsrvd8:7;
 337        uint64_t rsrvd9;
 338};
 339
 340/* FEC 5GNR Downlink Frame Control Word */
 341struct __rte_packed acc100_fcw_le {
 342        uint32_t FCWversion:4,
 343                qm:4,
 344                nfiller:11,
 345                BG:1,
 346                Zc:9,
 347                res0:3;
 348        uint32_t ncb:16,
 349                k0:16;
 350        uint32_t rm_e:24,
 351                res1:2,
 352                crc_select:1,
 353                res2:1,
 354                bypass_intlv:1,
 355                res3:3;
 356        uint32_t res4_a:12,
 357                mcb_count:3,
 358                res4_b:17;
 359        uint32_t res5;
 360        uint32_t res6;
 361        uint32_t res7;
 362        uint32_t res8;
 363};
 364
 365/* ACC100 DMA Request Descriptor */
 366struct __rte_packed acc100_dma_req_desc {
 367        union {
 368                struct{
 369                        uint32_t type:4,
 370                                rsrvd0:26,
 371                                sdone:1,
 372                                fdone:1;
 373                        uint32_t rsrvd1;
 374                        uint32_t rsrvd2;
 375                        uint32_t pass_param:8,
 376                                sdone_enable:1,
 377                                irq_enable:1,
 378                                timeStampEn:1,
 379                                res0:5,
 380                                numCBs:4,
 381                                res1:4,
 382                                m2dlen:4,
 383                                d2mlen:4;
 384                };
 385                struct{
 386                        uint32_t word0;
 387                        uint32_t word1;
 388                        uint32_t word2;
 389                        uint32_t word3;
 390                };
 391        };
 392        struct acc100_dma_triplet data_ptrs[ACC100_DMA_MAX_NUM_POINTERS];
 393
 394        /* Virtual addresses used to retrieve SW context info */
 395        union {
 396                void *op_addr;
 397                uint64_t pad1;  /* pad to 64 bits */
 398        };
 399        /*
 400         * Stores additional information needed for driver processing:
 401         * - last_desc_in_batch - flag used to mark last descriptor (CB)
 402         *                        in batch
 403         * - cbs_in_tb - stores information about total number of Code Blocks
 404         *               in currently processed Transport Block
 405         */
 406        union {
 407                struct {
 408                        union {
 409                                struct acc100_fcw_ld fcw_ld;
 410                                struct acc100_fcw_td fcw_td;
 411                                struct acc100_fcw_le fcw_le;
 412                                struct acc100_fcw_te fcw_te;
 413                                uint32_t pad2[ACC100_FCW_PADDING];
 414                        };
 415                        uint32_t last_desc_in_batch :8,
 416                                cbs_in_tb:8,
 417                                pad4 : 16;
 418                };
 419                uint64_t pad3[ACC100_DMA_DESC_PADDING]; /* pad to 64 bits */
 420        };
 421};
 422
 423/* ACC100 DMA Descriptor */
 424union acc100_dma_desc {
 425        struct acc100_dma_req_desc req;
 426        union acc100_dma_rsp_desc rsp;
 427        uint64_t atom_hdr;
 428};
 429
 430
 431/* Union describing Info Ring entry */
 432union acc100_harq_layout_data {
 433        uint32_t val;
 434        struct {
 435                uint16_t offset;
 436                uint16_t size0;
 437        };
 438} __rte_packed;
 439
 440
 441/* Union describing Info Ring entry */
 442union acc100_info_ring_data {
 443        uint32_t val;
 444        struct {
 445                union {
 446                        uint16_t detailed_info;
 447                        struct {
 448                                uint16_t aq_id: 4;
 449                                uint16_t qg_id: 4;
 450                                uint16_t vf_id: 6;
 451                                uint16_t reserved: 2;
 452                        };
 453                };
 454                uint16_t int_nb: 7;
 455                uint16_t msi_0: 1;
 456                uint16_t vf2pf: 6;
 457                uint16_t loop: 1;
 458                uint16_t valid: 1;
 459        };
 460} __rte_packed;
 461
 462struct acc100_registry_addr {
 463        unsigned int dma_ring_dl5g_hi;
 464        unsigned int dma_ring_dl5g_lo;
 465        unsigned int dma_ring_ul5g_hi;
 466        unsigned int dma_ring_ul5g_lo;
 467        unsigned int dma_ring_dl4g_hi;
 468        unsigned int dma_ring_dl4g_lo;
 469        unsigned int dma_ring_ul4g_hi;
 470        unsigned int dma_ring_ul4g_lo;
 471        unsigned int ring_size;
 472        unsigned int info_ring_hi;
 473        unsigned int info_ring_lo;
 474        unsigned int info_ring_en;
 475        unsigned int info_ring_ptr;
 476        unsigned int tail_ptrs_dl5g_hi;
 477        unsigned int tail_ptrs_dl5g_lo;
 478        unsigned int tail_ptrs_ul5g_hi;
 479        unsigned int tail_ptrs_ul5g_lo;
 480        unsigned int tail_ptrs_dl4g_hi;
 481        unsigned int tail_ptrs_dl4g_lo;
 482        unsigned int tail_ptrs_ul4g_hi;
 483        unsigned int tail_ptrs_ul4g_lo;
 484        unsigned int depth_log0_offset;
 485        unsigned int depth_log1_offset;
 486        unsigned int qman_group_func;
 487        unsigned int ddr_range;
 488};
 489
 490/* Structure holding registry addresses for PF */
 491static const struct acc100_registry_addr pf_reg_addr = {
 492        .dma_ring_dl5g_hi = HWPfDmaFec5GdlDescBaseHiRegVf,
 493        .dma_ring_dl5g_lo = HWPfDmaFec5GdlDescBaseLoRegVf,
 494        .dma_ring_ul5g_hi = HWPfDmaFec5GulDescBaseHiRegVf,
 495        .dma_ring_ul5g_lo = HWPfDmaFec5GulDescBaseLoRegVf,
 496        .dma_ring_dl4g_hi = HWPfDmaFec4GdlDescBaseHiRegVf,
 497        .dma_ring_dl4g_lo = HWPfDmaFec4GdlDescBaseLoRegVf,
 498        .dma_ring_ul4g_hi = HWPfDmaFec4GulDescBaseHiRegVf,
 499        .dma_ring_ul4g_lo = HWPfDmaFec4GulDescBaseLoRegVf,
 500        .ring_size = HWPfQmgrRingSizeVf,
 501        .info_ring_hi = HWPfHiInfoRingBaseHiRegPf,
 502        .info_ring_lo = HWPfHiInfoRingBaseLoRegPf,
 503        .info_ring_en = HWPfHiInfoRingIntWrEnRegPf,
 504        .info_ring_ptr = HWPfHiInfoRingPointerRegPf,
 505        .tail_ptrs_dl5g_hi = HWPfDmaFec5GdlRespPtrHiRegVf,
 506        .tail_ptrs_dl5g_lo = HWPfDmaFec5GdlRespPtrLoRegVf,
 507        .tail_ptrs_ul5g_hi = HWPfDmaFec5GulRespPtrHiRegVf,
 508        .tail_ptrs_ul5g_lo = HWPfDmaFec5GulRespPtrLoRegVf,
 509        .tail_ptrs_dl4g_hi = HWPfDmaFec4GdlRespPtrHiRegVf,
 510        .tail_ptrs_dl4g_lo = HWPfDmaFec4GdlRespPtrLoRegVf,
 511        .tail_ptrs_ul4g_hi = HWPfDmaFec4GulRespPtrHiRegVf,
 512        .tail_ptrs_ul4g_lo = HWPfDmaFec4GulRespPtrLoRegVf,
 513        .depth_log0_offset = HWPfQmgrGrpDepthLog20Vf,
 514        .depth_log1_offset = HWPfQmgrGrpDepthLog21Vf,
 515        .qman_group_func = HWPfQmgrGrpFunction0,
 516        .ddr_range = HWPfDmaVfDdrBaseRw,
 517};
 518
 519/* Structure holding registry addresses for VF */
 520static const struct acc100_registry_addr vf_reg_addr = {
 521        .dma_ring_dl5g_hi = HWVfDmaFec5GdlDescBaseHiRegVf,
 522        .dma_ring_dl5g_lo = HWVfDmaFec5GdlDescBaseLoRegVf,
 523        .dma_ring_ul5g_hi = HWVfDmaFec5GulDescBaseHiRegVf,
 524        .dma_ring_ul5g_lo = HWVfDmaFec5GulDescBaseLoRegVf,
 525        .dma_ring_dl4g_hi = HWVfDmaFec4GdlDescBaseHiRegVf,
 526        .dma_ring_dl4g_lo = HWVfDmaFec4GdlDescBaseLoRegVf,
 527        .dma_ring_ul4g_hi = HWVfDmaFec4GulDescBaseHiRegVf,
 528        .dma_ring_ul4g_lo = HWVfDmaFec4GulDescBaseLoRegVf,
 529        .ring_size = HWVfQmgrRingSizeVf,
 530        .info_ring_hi = HWVfHiInfoRingBaseHiVf,
 531        .info_ring_lo = HWVfHiInfoRingBaseLoVf,
 532        .info_ring_en = HWVfHiInfoRingIntWrEnVf,
 533        .info_ring_ptr = HWVfHiInfoRingPointerVf,
 534        .tail_ptrs_dl5g_hi = HWVfDmaFec5GdlRespPtrHiRegVf,
 535        .tail_ptrs_dl5g_lo = HWVfDmaFec5GdlRespPtrLoRegVf,
 536        .tail_ptrs_ul5g_hi = HWVfDmaFec5GulRespPtrHiRegVf,
 537        .tail_ptrs_ul5g_lo = HWVfDmaFec5GulRespPtrLoRegVf,
 538        .tail_ptrs_dl4g_hi = HWVfDmaFec4GdlRespPtrHiRegVf,
 539        .tail_ptrs_dl4g_lo = HWVfDmaFec4GdlRespPtrLoRegVf,
 540        .tail_ptrs_ul4g_hi = HWVfDmaFec4GulRespPtrHiRegVf,
 541        .tail_ptrs_ul4g_lo = HWVfDmaFec4GulRespPtrLoRegVf,
 542        .depth_log0_offset = HWVfQmgrGrpDepthLog20Vf,
 543        .depth_log1_offset = HWVfQmgrGrpDepthLog21Vf,
 544        .qman_group_func = HWVfQmgrGrpFunction0Vf,
 545        .ddr_range = HWVfDmaDdrBaseRangeRoVf,
 546};
 547
 548/* Structure associated with each queue. */
 549struct __rte_cache_aligned acc100_queue {
 550        union acc100_dma_desc *ring_addr;  /* Virtual address of sw ring */
 551        rte_iova_t ring_addr_iova;  /* IOVA address of software ring */
 552        uint32_t sw_ring_head;  /* software ring head */
 553        uint32_t sw_ring_tail;  /* software ring tail */
 554        /* software ring size (descriptors, not bytes) */
 555        uint32_t sw_ring_depth;
 556        /* mask used to wrap enqueued descriptors on the sw ring */
 557        uint32_t sw_ring_wrap_mask;
 558        /* MMIO register used to enqueue descriptors */
 559        void *mmio_reg_enqueue;
 560        uint8_t vf_id;  /* VF ID (max = 63) */
 561        uint8_t qgrp_id;  /* Queue Group ID */
 562        uint16_t aq_id;  /* Atomic Queue ID */
 563        uint16_t aq_depth;  /* Depth of atomic queue */
 564        uint32_t aq_enqueued;  /* Count how many "batches" have been enqueued */
 565        uint32_t aq_dequeued;  /* Count how many "batches" have been dequeued */
 566        uint32_t irq_enable;  /* Enable ops dequeue interrupts if set to 1 */
 567        struct rte_mempool *fcw_mempool;  /* FCW mempool */
 568        enum rte_bbdev_op_type op_type;  /* Type of this Queue: TE or TD */
 569        /* Internal Buffers for loopback input */
 570        uint8_t *lb_in;
 571        uint8_t *lb_out;
 572        rte_iova_t lb_in_addr_iova;
 573        rte_iova_t lb_out_addr_iova;
 574        struct acc100_device *d;
 575};
 576
 577typedef void (*acc10x_fcw_ld_fill_fun_t)(struct rte_bbdev_dec_op *op,
 578                struct acc100_fcw_ld *fcw,
 579                union acc100_harq_layout_data *harq_layout);
 580
 581/* Private data structure for each ACC100 device */
 582struct acc100_device {
 583        void *mmio_base;  /**< Base address of MMIO registers (BAR0) */
 584        void *sw_rings_base;  /* Base addr of un-aligned memory for sw rings */
 585        void *sw_rings;  /* 64MBs of 64MB aligned memory for sw rings */
 586        rte_iova_t sw_rings_iova;  /* IOVA address of sw_rings */
 587        /* Virtual address of the info memory routed to the this function under
 588         * operation, whether it is PF or VF.
 589         * HW may DMA information data at this location asynchronously
 590         */
 591        union acc100_info_ring_data *info_ring;
 592
 593        union acc100_harq_layout_data *harq_layout;
 594        /* Virtual Info Ring head */
 595        uint16_t info_ring_head;
 596        /* Number of bytes available for each queue in device, depending on
 597         * how many queues are enabled with configure()
 598         */
 599        uint32_t sw_ring_size;
 600        uint32_t ddr_size; /* Size in kB */
 601        uint32_t *tail_ptrs; /* Base address of response tail pointer buffer */
 602        rte_iova_t tail_ptr_iova; /* IOVA address of tail pointers */
 603        /* Max number of entries available for each queue in device, depending
 604         * on how many queues are enabled with configure()
 605         */
 606        uint32_t sw_ring_max_depth;
 607        struct rte_acc100_conf acc100_conf; /* ACC100 Initial configuration */
 608        /* Bitmap capturing which Queues have already been assigned */
 609        uint16_t q_assigned_bit_map[ACC100_NUM_QGRPS];
 610        bool pf_device; /**< True if this is a PF ACC100 device */
 611        bool configured; /**< True if this ACC100 device is configured */
 612        uint16_t device_variant;  /**< Device variant */
 613        acc10x_fcw_ld_fill_fun_t fcw_ld_fill;  /**< 5GUL FCW generation function */
 614};
 615
 616/**
 617 * Structure with details about RTE_BBDEV_EVENT_DEQUEUE event. It's passed to
 618 * the callback function.
 619 */
 620struct acc100_deq_intr_details {
 621        uint16_t queue_id;
 622};
 623
 624#endif /* _RTE_ACC100_PMD_H_ */
 625