dpdk/drivers/common/cnxk/roc_cpt.h
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   1/* SPDX-License-Identifier: BSD-3-Clause
   2 * Copyright(C) 2021 Marvell.
   3 */
   4
   5#ifndef _ROC_CPT_H_
   6#define _ROC_CPT_H_
   7
   8#include "roc_api.h"
   9
  10#define ROC_AE_CPT_BLOCK_TYPE1 0
  11#define ROC_AE_CPT_BLOCK_TYPE2 1
  12
  13/* Default engine groups */
  14#define ROC_CPT_DFLT_ENG_GRP_SE    0UL
  15#define ROC_CPT_DFLT_ENG_GRP_SE_IE 1UL
  16#define ROC_CPT_DFLT_ENG_GRP_AE    2UL
  17
  18#define ROC_CPT_MAX_LFS 64
  19#define ROC_CPT_MAX_BLKS 2
  20#define ROC_CN10K_CPT_INST_DW_M1                                               \
  21        ((uint64_t)(((sizeof(struct cpt_inst_s) / 16) - 1) & 0x7))
  22#define ROC_CN10K_TWO_CPT_INST_DW_M1                                           \
  23        ((uint64_t)(((sizeof(struct cpt_inst_s) * 2 / 16) - 1) & 0x7))
  24
  25/* Vector of sizes in the burst of 16 CPT inst except first in 63:19 of
  26 * APT_LMT_ARG_S
  27 */
  28#define ROC_CN10K_CPT_LMT_ARG                                                  \
  29        (ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 0) |                            \
  30         ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 1) |                            \
  31         ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 2) |                            \
  32         ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 3) |                            \
  33         ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 4) |                            \
  34         ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 5) |                            \
  35         ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 6) |                            \
  36         ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 7) |                            \
  37         ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 8) |                            \
  38         ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 9) |                            \
  39         ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 10) |                           \
  40         ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 11) |                           \
  41         ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 12) |                           \
  42         ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 13) |                           \
  43         ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 14))
  44
  45/* CPT helper macros */
  46#define ROC_CPT_AH_HDR_LEN       12
  47#define ROC_CPT_AES_GCM_IV_LEN   8
  48#define ROC_CPT_AES_GCM_MAC_LEN  16
  49#define ROC_CPT_AES_CBC_IV_LEN   16
  50#define ROC_CPT_SHA1_HMAC_LEN    12
  51#define ROC_CPT_SHA2_HMAC_LEN    16
  52
  53#define ROC_CPT_DES3_KEY_LEN        24
  54#define ROC_CPT_AES128_KEY_LEN      16
  55#define ROC_CPT_AES192_KEY_LEN      24
  56#define ROC_CPT_AES256_KEY_LEN      32
  57#define ROC_CPT_MD5_KEY_LENGTH      16
  58#define ROC_CPT_SHA1_KEY_LENGTH     20
  59#define ROC_CPT_SHA256_KEY_LENGTH   32
  60#define ROC_CPT_SHA384_KEY_LENGTH   48
  61#define ROC_CPT_SHA512_KEY_LENGTH   64
  62#define ROC_CPT_AES_XCBC_KEY_LENGTH 16
  63#define ROC_CPT_AUTH_KEY_LEN_MAX    64
  64
  65#define ROC_CPT_DES_BLOCK_LENGTH 8
  66#define ROC_CPT_AES_BLOCK_LENGTH 16
  67
  68#define ROC_CPT_AES_GCM_ROUNDUP_BYTE_LEN 4
  69#define ROC_CPT_AES_CBC_ROUNDUP_BYTE_LEN 16
  70
  71/* Salt length for AES-CTR/GCM/CCM and AES-GMAC */
  72#define ROC_CPT_SALT_LEN 4
  73
  74#define ROC_CPT_ESP_HDR_LEN         8
  75#define ROC_CPT_ESP_TRL_LEN         2
  76#define ROC_CPT_AH_HDR_LEN          12
  77#define ROC_CPT_TUNNEL_IPV4_HDR_LEN 20
  78#define ROC_CPT_TUNNEL_IPV6_HDR_LEN 40
  79
  80#define ROC_CPT_CCM_AAD_DATA 1
  81#define ROC_CPT_CCM_MSG_LEN  4
  82#define ROC_CPT_CCM_ICV_LEN  16
  83#define ROC_CPT_CCM_FLAGS                                                      \
  84        ((ROC_CPT_CCM_AAD_DATA << 6) |                                         \
  85         (((ROC_CPT_CCM_ICV_LEN - 2) / 2) << 3) | (ROC_CPT_CCM_MSG_LEN - 1))
  86#define ROC_CPT_CCM_SALT_LEN 3
  87
  88#define ROC_CPT_RES_ALIGN 16
  89
  90enum {
  91        ROC_CPT_REVISION_ID_83XX = 0,
  92        ROC_CPT_REVISION_ID_96XX_B0 = 1,
  93        ROC_CPT_REVISION_ID_96XX_C0 = 2,
  94        ROC_CPT_REVISION_ID_98XX = 3,
  95        ROC_CPT_REVISION_ID_106XX = 4,
  96};
  97
  98struct roc_cpt_lmtline {
  99        uint64_t io_addr;
 100        uint64_t *fc_addr;
 101        uintptr_t lmt_base;
 102        uint32_t fc_thresh;
 103};
 104
 105struct roc_cpt_lf {
 106        /* Input parameters */
 107        uint16_t lf_id;
 108        uint32_t nb_desc;
 109        /* End of Input parameters */
 110        struct plt_pci_device *pci_dev;
 111        struct dev *dev;
 112        struct roc_cpt *roc_cpt;
 113        uintptr_t rbase;
 114        uintptr_t lmt_base;
 115        uint16_t msixoff;
 116        uint16_t pf_func;
 117        uint64_t *fc_addr;
 118        uint64_t io_addr;
 119        uint8_t *iq_vaddr;
 120        struct roc_nix *inl_outb_nix;
 121} __plt_cache_aligned;
 122
 123struct roc_cpt {
 124        struct plt_pci_device *pci_dev;
 125        struct roc_cpt_lf *lf[ROC_CPT_MAX_LFS];
 126        uint16_t nb_lf;
 127        uint16_t nb_lf_avail;
 128        uintptr_t lmt_base;
 129        /**< CPT device capabilities */
 130        union cpt_eng_caps hw_caps[CPT_MAX_ENG_TYPES];
 131        uint8_t eng_grp[CPT_MAX_ENG_TYPES];
 132        uint8_t cpt_revision;
 133
 134#define ROC_CPT_MEM_SZ (6 * 1024)
 135        uint8_t reserved[ROC_CPT_MEM_SZ] __plt_cache_aligned;
 136} __plt_cache_aligned;
 137
 138struct roc_cpt_rxc_time_cfg {
 139        uint32_t step;
 140        uint16_t active_limit;
 141        uint16_t active_thres;
 142        uint16_t zombie_limit;
 143        uint16_t zombie_thres;
 144};
 145
 146int __roc_api roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt,
 147                                   struct roc_cpt_rxc_time_cfg *cfg);
 148int __roc_api roc_cpt_dev_init(struct roc_cpt *roc_cpt);
 149int __roc_api roc_cpt_dev_fini(struct roc_cpt *roc_cpt);
 150int __roc_api roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt,
 151                                  enum cpt_eng_type eng_type);
 152int __roc_api roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf);
 153void __roc_api roc_cpt_dev_clear(struct roc_cpt *roc_cpt);
 154int __roc_api roc_cpt_lf_init(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf);
 155void __roc_api roc_cpt_lf_fini(struct roc_cpt_lf *lf);
 156int __roc_api roc_cpt_lf_ctx_flush(struct roc_cpt_lf *lf, void *cptr,
 157                                   bool inval);
 158int __roc_api roc_cpt_lf_ctx_reload(struct roc_cpt_lf *lf, void *cptr);
 159int __roc_api roc_cpt_inline_ipsec_cfg(struct dev *dev, uint8_t slot,
 160                                       struct roc_nix *nix);
 161int __roc_api roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt,
 162                                           uint16_t param1, uint16_t param2);
 163int __roc_api roc_cpt_afs_print(struct roc_cpt *roc_cpt);
 164int __roc_api roc_cpt_lfs_print(struct roc_cpt *roc_cpt);
 165void __roc_api roc_cpt_iq_disable(struct roc_cpt_lf *lf);
 166void __roc_api roc_cpt_iq_enable(struct roc_cpt_lf *lf);
 167int __roc_api roc_cpt_lmtline_init(struct roc_cpt *roc_cpt,
 168                                   struct roc_cpt_lmtline *lmtline, int lf_id);
 169
 170void __roc_api roc_cpt_parse_hdr_dump(const struct cpt_parse_hdr_s *cpth);
 171int __roc_api roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr,
 172                                void *sa_cptr, uint16_t sa_len);
 173
 174int __roc_api roc_on_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa,
 175                                   uint8_t opcode, uint16_t ctx_len,
 176                                   uint8_t egrp);
 177#endif /* _ROC_CPT_H_ */
 178