LXR dpdk/drivers/dma/idxd/idxd_hw

   1/* SPDX-License-Identifier: BSD-3-Clause
   2 * Copyright 2021 Intel Corporation
   3 */
   4
   5#ifndef _IDXD_HW_DEFS_H_
   6#define _IDXD_HW_DEFS_H_
   7
   8/*
   9 * Defines used in the data path for interacting with IDXD hardware.
  10 */
  11#define IDXD_CMD_OP_SHIFT 24
  12enum rte_idxd_ops {
  13        idxd_op_nop = 0,
  14        idxd_op_batch,
  15        idxd_op_drain,
  16        idxd_op_memmove,
  17        idxd_op_fill
  18};
  19
  20#define IDXD_FLAG_FENCE                 (1 << 0)
  21#define IDXD_FLAG_COMPLETION_ADDR_VALID (1 << 2)
  22#define IDXD_FLAG_REQUEST_COMPLETION    (1 << 3)
  23#define IDXD_FLAG_CACHE_CONTROL         (1 << 8)
  24
  25/**
  26 * Hardware descriptor used by DSA hardware, for both bursts and
  27 * for individual operations.
  28 */
  29struct idxd_hw_desc {
  30        uint32_t pasid;
  31        uint32_t op_flags;
  32        rte_iova_t completion;
  33
  34        RTE_STD_C11
  35        union {
  36                rte_iova_t src;      /* source address for copy ops etc. */
  37                rte_iova_t desc_addr; /* descriptor pointer for batch */
  38        };
  39        rte_iova_t dst;
  40
  41        uint32_t size;    /* length of data for op, or batch size */
  42
  43        uint16_t intr_handle; /* completion interrupt handle */
  44
  45        /* remaining 26 bytes are reserved */
  46        uint16_t reserved[13];
  47} __rte_aligned(64);
  48
  49#define IDXD_COMP_STATUS_INCOMPLETE        0
  50#define IDXD_COMP_STATUS_SUCCESS           1
  51#define IDXD_COMP_STATUS_INVALID_OPCODE 0x10
  52#define IDXD_COMP_STATUS_INVALID_SIZE   0x13
  53#define IDXD_COMP_STATUS_SKIPPED        0xFF /* not official IDXD error, needed as placeholder */
  54
  55/**
  56 * Completion record structure written back by DSA
  57 */
  58struct idxd_completion {
  59        uint8_t status;
  60        uint8_t result;
  61        /* 16-bits pad here */
  62        uint32_t completed_size; /* data length, or descriptors for batch */
  63
  64        rte_iova_t fault_address;
  65        uint32_t invalid_flags;
  66} __rte_aligned(32);
  67
  68/*** Definitions for Intel(R) Data Streaming Accelerator  ***/
  69
  70#define IDXD_CMD_SHIFT 20
  71enum rte_idxd_cmds {
  72        idxd_enable_dev = 1,
  73        idxd_disable_dev,
  74        idxd_drain_all,
  75        idxd_abort_all,
  76        idxd_reset_device,
  77        idxd_enable_wq,
  78        idxd_disable_wq,
  79        idxd_drain_wq,
  80        idxd_abort_wq,
  81        idxd_reset_wq,
  82};
  83
  84/* General bar0 registers */
  85struct rte_idxd_bar0 {
  86        uint32_t __rte_cache_aligned version;    /* offset 0x00 */
  87        uint64_t __rte_aligned(0x10) gencap;     /* offset 0x10 */
  88        uint64_t __rte_aligned(0x10) wqcap;      /* offset 0x20 */
  89        uint64_t __rte_aligned(0x10) grpcap;     /* offset 0x30 */
  90        uint64_t __rte_aligned(0x08) engcap;     /* offset 0x38 */
  91        uint64_t __rte_aligned(0x10) opcap;      /* offset 0x40 */
  92        uint64_t __rte_aligned(0x20) offsets[2]; /* offset 0x60 */
  93        uint32_t __rte_aligned(0x20) gencfg;     /* offset 0x80 */
  94        uint32_t __rte_aligned(0x08) genctrl;    /* offset 0x88 */
  95        uint32_t __rte_aligned(0x10) gensts;     /* offset 0x90 */
  96        uint32_t __rte_aligned(0x08) intcause;   /* offset 0x98 */
  97        uint32_t __rte_aligned(0x10) cmd;        /* offset 0xA0 */
  98        uint32_t __rte_aligned(0x08) cmdstatus;  /* offset 0xA8 */
  99        uint64_t __rte_aligned(0x20) swerror[4]; /* offset 0xC0 */
 100};
 101
 102/* workqueue config is provided by array of uint32_t. */
 103enum rte_idxd_wqcfg {
 104        wq_size_idx,       /* size is in first 32-bit value */
 105        wq_threshold_idx,  /* WQ threshold second 32-bits */
 106        wq_mode_idx,       /* WQ mode and other flags */
 107        wq_sizes_idx,      /* WQ transfer and batch sizes */
 108        wq_occ_int_idx,    /* WQ occupancy interrupt handle */
 109        wq_occ_limit_idx,  /* WQ occupancy limit */
 110        wq_state_idx,      /* WQ state and occupancy state */
 111};
 112
 113#define WQ_MODE_SHARED    0
 114#define WQ_MODE_DEDICATED 1
 115#define WQ_PRIORITY_SHIFT 4
 116#define WQ_BATCH_SZ_SHIFT 5
 117#define WQ_STATE_SHIFT 30
 118#define WQ_STATE_MASK 0x3
 119
 120struct rte_idxd_grpcfg {
 121        uint64_t grpwqcfg[4]  __rte_cache_aligned; /* 64-byte register set */
 122        uint64_t grpengcfg;  /* offset 32 */
 123        uint32_t grpflags;   /* offset 40 */
 124};
 125
 126#define GENSTS_DEV_STATE_MASK 0x03
 127#define CMDSTATUS_ACTIVE_SHIFT 31
 128#define CMDSTATUS_ACTIVE_MASK (1 << 31)
 129#define CMDSTATUS_ERR_MASK 0xFF
 130
 131#endif
 132