LXR dpdk/drivers/event/dpaa/dpaa

   1/*   SPDX-License-Identifier:        BSD-3-Clause
   2 *   Copyright 2017 NXP
   3 */
   4
   5#ifndef __DPAA_EVENTDEV_H__
   6#define __DPAA_EVENTDEV_H__
   7
   8#include <eventdev_pmd.h>
   9#include <eventdev_pmd_vdev.h>
  10#include <rte_atomic.h>
  11#include <rte_per_lcore.h>
  12
  13#define EVENTDEV_NAME_DPAA_PMD          event_dpaa1
  14
  15#define DPAA_EVENT_MAX_PORTS                    4
  16#define DPAA_EVENT_MAX_QUEUES                   8
  17#define DPAA_EVENT_MIN_DEQUEUE_TIMEOUT  1
  18#define DPAA_EVENT_MAX_DEQUEUE_TIMEOUT  (UINT32_MAX - 1)
  19#define DPAA_EVENT_MAX_QUEUE_FLOWS              2048
  20#define DPAA_EVENT_MAX_QUEUE_PRIORITY_LEVELS    8
  21#define DPAA_EVENT_MAX_EVENT_PRIORITY_LEVELS    0
  22#define DPAA_EVENT_MAX_EVENT_PORT               RTE_MIN(RTE_MAX_LCORE, INT8_MAX)
  23#define DPAA_EVENT_MAX_PORT_DEQUEUE_DEPTH       8
  24#define DPAA_EVENT_PORT_DEQUEUE_TIMEOUT_NS      100000UL
  25#define DPAA_EVENT_PORT_DEQUEUE_TIMEOUT_INVALID ((uint64_t)-1)
  26#define DPAA_EVENT_MAX_PORT_ENQUEUE_DEPTH       1
  27#define DPAA_EVENT_MAX_NUM_EVENTS               (INT32_MAX - 1)
  28
  29#define DPAA_EVENT_DEV_CAP                      \
  30do {                                            \
  31        RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |   \
  32        RTE_EVENT_DEV_CAP_BURST_MODE;           \
  33} while (0)
  34
  35#define DPAA_EVENT_QUEUE_ATOMIC_FLOWS           2048
  36#define DPAA_EVENT_QUEUE_ORDER_SEQUENCES        2048
  37
  38#define RTE_EVENT_ETH_RX_ADAPTER_DPAA_CAP \
  39                (RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT | \
  40                RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ | \
  41                RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID)
  42
  43#define RTE_EVENT_CRYPTO_ADAPTER_DPAA_CAP \
  44                (RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_NEW | \
  45                RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_QP_EV_BIND | \
  46                RTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA)
  47
  48struct dpaa_eventq {
  49        /* Channel Id */
  50        uint16_t ch_id;
  51        /* Configuration provided by the user */
  52        uint32_t event_queue_cfg;
  53        uint32_t event_queue_id;
  54        /* Event port */
  55        void *event_port;
  56};
  57
  58struct dpaa_port {
  59        struct dpaa_eventq evq_info[DPAA_EVENT_MAX_QUEUES];
  60        uint8_t num_linked_evq;
  61        uint8_t is_port_linked;
  62        uint64_t timeout_us;
  63};
  64
  65struct dpaa_eventdev {
  66        struct dpaa_eventq evq_info[DPAA_EVENT_MAX_QUEUES];
  67        struct dpaa_port ports[DPAA_EVENT_MAX_PORTS];
  68        uint32_t dequeue_timeout_ns;
  69        uint32_t nb_events_limit;
  70        uint8_t max_event_queues;
  71        uint8_t nb_event_queues;
  72        uint8_t nb_event_ports;
  73        uint8_t intr_mode;
  74        uint32_t nb_event_queue_flows;
  75        uint32_t nb_event_port_dequeue_depth;
  76        uint32_t nb_event_port_enqueue_depth;
  77        uint32_t event_dev_cfg;
  78};
  79
  80#define DPAA_EVENTDEV_LOG(level, fmt, args...) \
  81        rte_log(RTE_LOG_ ## level, dpaa_logtype_eventdev, "%s(): " fmt "\n", \
  82                __func__, ##args)
  83
  84#define EVENTDEV_INIT_FUNC_TRACE() DPAA_EVENTDEV_LOG(DEBUG, " >>")
  85
  86#define DPAA_EVENTDEV_DEBUG(fmt, args...) \
  87        DPAA_EVENTDEV_LOG(DEBUG, fmt, ## args)
  88#define DPAA_EVENTDEV_ERR(fmt, args...) \
  89        DPAA_EVENTDEV_LOG(ERR, fmt, ## args)
  90#define DPAA_EVENTDEV_INFO(fmt, args...) \
  91        DPAA_EVENTDEV_LOG(INFO, fmt, ## args)
  92#define DPAA_EVENTDEV_WARN(fmt, args...) \
  93        DPAA_EVENTDEV_LOG(WARNING, fmt, ## args)
  94
  95#endif /* __DPAA_EVENTDEV_H__ */
  96