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6#ifndef __CHELSIO_COMMON_H
7#define __CHELSIO_COMMON_H
8
9#include "../cxgbe_compat.h"
10#include "t4_hw.h"
11#include "t4vf_hw.h"
12#include "t4_chip_type.h"
13#include "t4fw_interface.h"
14
15#define CXGBE_PAGE_SIZE RTE_PGSIZE_4K
16
17#define T4_MEMORY_WRITE 0
18#define T4_MEMORY_READ 1
19
20enum {
21 MAX_NPORTS = 4,
22};
23
24enum {
25 T5_REGMAP_SIZE = (332 * 1024),
26};
27
28enum {
29 MEMWIN0_APERTURE = 2048,
30 MEMWIN0_BASE = 0x1b800,
31};
32
33enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST };
34
35enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR };
36
37enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
38
39struct port_stats {
40 u64 tx_octets;
41 u64 tx_frames;
42 u64 tx_bcast_frames;
43 u64 tx_mcast_frames;
44 u64 tx_ucast_frames;
45 u64 tx_error_frames;
46
47 u64 tx_frames_64;
48 u64 tx_frames_65_127;
49 u64 tx_frames_128_255;
50 u64 tx_frames_256_511;
51 u64 tx_frames_512_1023;
52 u64 tx_frames_1024_1518;
53 u64 tx_frames_1519_max;
54
55 u64 tx_drop;
56 u64 tx_pause;
57 u64 tx_ppp0;
58 u64 tx_ppp1;
59 u64 tx_ppp2;
60 u64 tx_ppp3;
61 u64 tx_ppp4;
62 u64 tx_ppp5;
63 u64 tx_ppp6;
64 u64 tx_ppp7;
65
66 u64 rx_octets;
67 u64 rx_frames;
68 u64 rx_bcast_frames;
69 u64 rx_mcast_frames;
70 u64 rx_ucast_frames;
71 u64 rx_too_long;
72 u64 rx_jabber;
73 u64 rx_fcs_err;
74 u64 rx_len_err;
75 u64 rx_symbol_err;
76 u64 rx_runt;
77
78 u64 rx_frames_64;
79 u64 rx_frames_65_127;
80 u64 rx_frames_128_255;
81 u64 rx_frames_256_511;
82 u64 rx_frames_512_1023;
83 u64 rx_frames_1024_1518;
84 u64 rx_frames_1519_max;
85
86 u64 rx_pause;
87 u64 rx_ppp0;
88 u64 rx_ppp1;
89 u64 rx_ppp2;
90 u64 rx_ppp3;
91 u64 rx_ppp4;
92 u64 rx_ppp5;
93 u64 rx_ppp6;
94 u64 rx_ppp7;
95
96 u64 rx_ovflow0;
97 u64 rx_ovflow1;
98 u64 rx_ovflow2;
99 u64 rx_ovflow3;
100 u64 rx_trunc0;
101 u64 rx_trunc1;
102 u64 rx_trunc2;
103 u64 rx_trunc3;
104
105 u64 rx_tp_tnl_cong_drops[NCHAN];
106};
107
108struct sge_params {
109 u32 hps;
110 u32 eq_qpp;
111 u32 iq_qpp;
112};
113
114struct tp_params {
115 unsigned int ntxchan;
116 unsigned int tre;
117 unsigned int dack_re;
118 unsigned int la_mask;
119 unsigned short tx_modq[NCHAN];
120
121 u32 vlan_pri_map;
122 u32 filter_mask;
123 u32 ingress_config;
124
125
126
127
128 int rx_pkt_encap;
129
130
131
132
133
134
135
136
137
138
139
140
141
142 int vlan_shift;
143 int vnic_shift;
144 int port_shift;
145 int protocol_shift;
146 int ethertype_shift;
147 int macmatch_shift;
148 int tos_shift;
149
150 u64 hash_filter_mask;
151};
152
153struct vpd_params {
154 unsigned int cclk;
155};
156
157struct pci_params {
158 uint16_t vendor_id;
159 uint16_t device_id;
160 uint32_t vpd_cap_addr;
161 uint16_t speed;
162 uint8_t width;
163};
164
165
166
167
168struct devlog_params {
169 u32 memtype;
170 u32 start;
171 u32 size;
172};
173
174struct arch_specific_params {
175 u8 nchan;
176 u8 cng_ch_bits_log;
177 u16 mps_rplc_size;
178 u16 vfcount;
179 u32 sge_fl_db;
180 u16 mps_tcam_size;
181};
182
183
184
185
186struct rss_params {
187 unsigned int mode;
188 union {
189 struct {
190 unsigned int synmapen:1;
191 unsigned int syn4tupenipv6:1;
192 unsigned int syn2tupenipv6:1;
193 unsigned int syn4tupenipv4:1;
194 unsigned int syn2tupenipv4:1;
195 unsigned int ofdmapen:1;
196 unsigned int tnlmapen:1;
197 unsigned int tnlalllookup:1;
198 unsigned int hashtoeplitz:1;
199 } basicvirtual;
200 } u;
201};
202
203
204
205
206struct pf_resources {
207 unsigned int neq;
208 unsigned int nethctrl;
209 unsigned int niqflint;
210};
211
212
213
214
215struct vf_resources {
216 unsigned int nvi;
217 unsigned int neq;
218 unsigned int nethctrl;
219 unsigned int niqflint;
220 unsigned int niq;
221 unsigned int tc;
222 unsigned int pmask;
223 unsigned int nexactf;
224 unsigned int r_caps;
225 unsigned int wx_caps;
226};
227
228struct adapter_params {
229 struct sge_params sge;
230 struct tp_params tp;
231 struct vpd_params vpd;
232 struct pci_params pci;
233 struct devlog_params devlog;
234 struct rss_params rss;
235 struct pf_resources pfres;
236 struct vf_resources vfres;
237 enum pcie_memwin drv_memwin;
238
239 unsigned int sf_size;
240 unsigned int sf_nsec;
241
242 unsigned int fw_vers;
243 unsigned int bs_vers;
244 unsigned int tp_vers;
245 unsigned int er_vers;
246
247 unsigned short mtus[NMTUS];
248 unsigned short a_wnd[NCCTRL_WIN];
249 unsigned short b_wnd[NCCTRL_WIN];
250
251 unsigned int mc_size;
252 unsigned int cim_la_size;
253
254 unsigned char nports;
255 unsigned char portvec;
256
257 unsigned char hash_filter;
258
259 enum chip_type chip;
260 struct arch_specific_params arch;
261
262 bool ulptx_memwrite_dsgl;
263 u8 filter2_wr_support;
264 u32 viid_smt_extn_support:1;
265 u32 max_tx_coalesce_num;
266 u8 vi_enable_rx;
267
268 u16 rawf_start;
269 u16 rawf_size;
270};
271
272
273
274struct link_config {
275 u32 pcaps;
276 u32 acaps;
277
278 u32 link_caps;
279 u32 admin_caps;
280
281 u8 mdio_addr;
282 u8 port_type;
283 u8 mod_type;
284
285 u8 link_ok;
286 u8 link_down_rc;
287};
288
289#include "adapter.h"
290
291void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
292 u32 val);
293int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
294 int polarity,
295 int attempts, int delay, u32 *valp);
296
297static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
298 int polarity, int attempts, int delay)
299{
300 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
301 delay, NULL);
302}
303
304static inline int is_pf4(struct adapter *adap)
305{
306 return adap->pf == 4;
307}
308
309#define for_each_port(adapter, iter) \
310 for (iter = 0; iter < (adapter)->params.nports; ++iter)
311
312static inline int is_hashfilter(const struct adapter *adap)
313{
314 return adap->params.hash_filter;
315}
316
317void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
318void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
319 unsigned int mask, unsigned int val);
320void t4_intr_enable(struct adapter *adapter);
321void t4_intr_disable(struct adapter *adapter);
322int t4_link_l1cfg_core(struct port_info *pi, u32 caps, u8 sleep_ok);
323static inline int t4_link_l1cfg(struct port_info *pi, u32 caps)
324{
325 return t4_link_l1cfg_core(pi, caps, true);
326}
327
328static inline int t4_link_l1cfg_ns(struct port_info *pi, u32 caps)
329{
330 return t4_link_l1cfg_core(pi, caps, false);
331}
332
333int t4_set_link_speed(struct port_info *pi, u32 speed, u32 *new_caps);
334int t4_set_link_pause(struct port_info *pi, u8 autoneg, u8 pause_tx,
335 u8 pause_rx, u32 *new_caps);
336int t4_set_link_fec(struct port_info *pi, u8 fec_rs, u8 fec_baser,
337 u8 fec_none, u32 *new_caps);
338unsigned int t4_fwcap_to_speed(u32 caps);
339void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
340 const unsigned short *alpha, const unsigned short *beta);
341int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
342 enum dev_master master, enum dev_state *state);
343int t4_fw_bye(struct adapter *adap, unsigned int mbox);
344int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
345int t4vf_fw_reset(struct adapter *adap);
346int t4_fw_halt(struct adapter *adap, unsigned int mbox, int reset);
347int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset);
348int t4vf_get_vfres(struct adapter *adap);
349int t4_fixup_host_params_compat(struct adapter *adap, unsigned int page_size,
350 unsigned int cache_line_size,
351 enum chip_type chip_compat);
352int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
353 unsigned int cache_line_size);
354int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
355int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
356 unsigned int vf, unsigned int nparams, const u32 *params,
357 u32 *val);
358int t4vf_query_params(struct adapter *adap, unsigned int nparams,
359 const u32 *params, u32 *vals);
360int t4vf_get_dev_params(struct adapter *adap);
361int t4vf_get_vpd_params(struct adapter *adap);
362int t4vf_get_rss_glb_config(struct adapter *adap);
363int t4vf_set_params(struct adapter *adapter, unsigned int nparams,
364 const u32 *params, const u32 *vals);
365int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
366 unsigned int pf, unsigned int vf,
367 unsigned int nparams, const u32 *params,
368 const u32 *val, int timeout);
369int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
370 unsigned int vf, unsigned int nparams, const u32 *params,
371 const u32 *val);
372int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
373 unsigned int port, unsigned int pf, unsigned int vf,
374 unsigned int nmac, u8 *mac, unsigned int *rss_size,
375 unsigned int portfunc, unsigned int idstype,
376 u8 *vivld, u8 *vin);
377int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
378 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
379 unsigned int *rss_size, u8 *vivild, u8 *vin);
380int t4_free_vi(struct adapter *adap, unsigned int mbox,
381 unsigned int pf, unsigned int vf,
382 unsigned int viid);
383int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
384 int mtu, int promisc, int all_multi, int bcast, int vlanex,
385 bool sleep_ok);
386int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
387 const u8 *addr, const u8 *mask, unsigned int idx,
388 u8 lookup_type, u8 port_id, bool sleep_ok);
389int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
390 const u8 *addr, const u8 *mask, unsigned int idx,
391 u8 lookup_type, u8 port_id, bool sleep_ok);
392int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
393 int idx, const u8 *addr, bool persist, bool add_smt);
394int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
395 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
396int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
397 bool rx_en, bool tx_en);
398int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
399 unsigned int pf, unsigned int vf, unsigned int iqid,
400 unsigned int fl0id, unsigned int fl1id);
401int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
402 unsigned int vf, unsigned int iqtype, unsigned int iqid,
403 unsigned int fl0id, unsigned int fl1id);
404int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
405 unsigned int vf, unsigned int eqid);
406int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
407 unsigned int vf, unsigned int eqid);
408
409static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
410{
411 return adap->params.vpd.cclk / 1000;
412}
413
414static inline unsigned int us_to_core_ticks(const struct adapter *adap,
415 unsigned int us)
416{
417 return (us * adap->params.vpd.cclk) / 1000;
418}
419
420static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
421 unsigned int ticks)
422{
423
424 return ((ticks * 1000 + adapter->params.vpd.cclk / 2) /
425 adapter->params.vpd.cclk);
426}
427
428int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
429 int size, void *rpl, bool sleep_ok, int timeout);
430int t4_wr_mbox_meat(struct adapter *adap, int mbox,
431 const void __attribute__((__may_alias__)) *cmd, int size,
432 void *rpl, bool sleep_ok);
433
434static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
435 const void *cmd, int size, void *rpl,
436 int timeout)
437{
438 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
439 timeout);
440}
441
442int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p);
443
444static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
445 int size, void *rpl)
446{
447 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
448}
449
450static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
451 int size, void *rpl)
452{
453 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
454}
455
456int t4vf_wr_mbox_core(struct adapter *, const void *, int, void *, bool);
457
458static inline int t4vf_wr_mbox(struct adapter *adapter, const void *cmd,
459 int size, void *rpl)
460{
461 return t4vf_wr_mbox_core(adapter, cmd, size, rpl, true);
462}
463
464static inline int t4vf_wr_mbox_ns(struct adapter *adapter, const void *cmd,
465 int size, void *rpl)
466{
467 return t4vf_wr_mbox_core(adapter, cmd, size, rpl, false);
468}
469
470
471void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
472 unsigned int data_reg, u32 *vals, unsigned int nregs,
473 unsigned int start_idx);
474void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
475 unsigned int data_reg, const u32 *vals,
476 unsigned int nregs, unsigned int start_idx);
477
478int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
479int t4_get_pfres(struct adapter *adapter);
480int t4_read_flash(struct adapter *adapter, unsigned int addr,
481 unsigned int nwords, u32 *data, int byte_oriented);
482int t4_flash_cfg_addr(struct adapter *adapter);
483unsigned int t4_get_mps_bg_map(struct adapter *adapter, unsigned int pidx);
484unsigned int t4_get_tp_ch_map(struct adapter *adapter, unsigned int pidx);
485const char *t4_get_port_type_description(enum fw_port_type port_type);
486void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
487void t4vf_get_port_stats(struct adapter *adapter, int pidx,
488 struct port_stats *p);
489void t4_get_port_stats_offset(struct adapter *adap, int idx,
490 struct port_stats *stats,
491 struct port_stats *offset);
492void t4_clr_port_stats(struct adapter *adap, int idx);
493void t4_init_link_config(struct port_info *pi, u32 pcaps, u32 acaps,
494 u8 mdio_addr, u8 port_type, u8 mod_type);
495void t4_reset_link_config(struct adapter *adap, int idx);
496int t4_get_version_info(struct adapter *adapter);
497void t4_dump_version_info(struct adapter *adapter);
498int t4_get_flash_params(struct adapter *adapter);
499int t4_get_chip_type(struct adapter *adap, int ver);
500int t4_prep_adapter(struct adapter *adapter);
501int t4vf_prep_adapter(struct adapter *adapter);
502int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
503int t4vf_port_init(struct adapter *adap);
504int t4_init_rss_mode(struct adapter *adap, int mbox);
505int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
506 int start, int n, const u16 *rspq, unsigned int nrspq);
507int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
508 unsigned int flags, unsigned int defq);
509int t4_read_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
510 u64 *flags, unsigned int *defq);
511void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
512 unsigned int start_index, unsigned int rw);
513void t4_write_rss_key(struct adapter *adap, u32 *key, int idx);
514void t4_read_rss_key(struct adapter *adap, u32 *key);
515
516enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
517int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
518 enum t4_bar2_qtype qtype, u64 *pbar2_qoffset,
519 unsigned int *pbar2_qid);
520
521int t4_init_sge_params(struct adapter *adapter);
522int t4_init_tp_params(struct adapter *adap);
523int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel);
524int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
525unsigned int t4_get_regs_len(struct adapter *adap);
526unsigned int t4vf_get_pf_from_vf(struct adapter *adap);
527void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
528int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data);
529int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data);
530int t4_seeprom_wp(struct adapter *adapter, int enable);
531int t4_memory_rw_addr(struct adapter *adap, int win,
532 u32 addr, u32 len, void *hbuf, int dir);
533int t4_memory_rw_mtype(struct adapter *adap, int win, int mtype, u32 maddr,
534 u32 len, void *hbuf, int dir);
535static inline int t4_memory_rw(struct adapter *adap, int win,
536 int mtype, u32 maddr, u32 len,
537 void *hbuf, int dir)
538{
539 return t4_memory_rw_mtype(adap, win, mtype, maddr, len, hbuf, dir);
540}
541#endif
542