LXR dpdk/drivers/net/e1000/base/e1000

   1/* SPDX-License-Identifier: BSD-3-Clause
   2 * Copyright(c) 2001-2020 Intel Corporation
   3 */
   4
   5/*
   6 * 82542 Gigabit Ethernet Controller
   7 */
   8
   9#include "e1000_api.h"
  10
  11STATIC s32  e1000_init_phy_params_82542(struct e1000_hw *hw);
  12STATIC s32  e1000_init_nvm_params_82542(struct e1000_hw *hw);
  13STATIC s32  e1000_init_mac_params_82542(struct e1000_hw *hw);
  14STATIC s32  e1000_get_bus_info_82542(struct e1000_hw *hw);
  15STATIC s32  e1000_reset_hw_82542(struct e1000_hw *hw);
  16STATIC s32  e1000_init_hw_82542(struct e1000_hw *hw);
  17STATIC s32  e1000_setup_link_82542(struct e1000_hw *hw);
  18STATIC s32  e1000_led_on_82542(struct e1000_hw *hw);
  19STATIC s32  e1000_led_off_82542(struct e1000_hw *hw);
  20STATIC int  e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index);
  21STATIC void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw);
  22STATIC s32  e1000_read_mac_addr_82542(struct e1000_hw *hw);
  23
  24/**
  25 *  e1000_init_phy_params_82542 - Init PHY func ptrs.
  26 *  @hw: pointer to the HW structure
  27 **/
  28STATIC s32 e1000_init_phy_params_82542(struct e1000_hw *hw)
  29{
  30        struct e1000_phy_info *phy = &hw->phy;
  31        s32 ret_val = E1000_SUCCESS;
  32
  33        DEBUGFUNC("e1000_init_phy_params_82542");
  34
  35        phy->type = e1000_phy_none;
  36
  37        return ret_val;
  38}
  39
  40/**
  41 *  e1000_init_nvm_params_82542 - Init NVM func ptrs.
  42 *  @hw: pointer to the HW structure
  43 **/
  44STATIC s32 e1000_init_nvm_params_82542(struct e1000_hw *hw)
  45{
  46        struct e1000_nvm_info *nvm = &hw->nvm;
  47
  48        DEBUGFUNC("e1000_init_nvm_params_82542");
  49
  50        nvm->address_bits       =  6;
  51        nvm->delay_usec         = 50;
  52        nvm->opcode_bits        =  3;
  53        nvm->type               = e1000_nvm_eeprom_microwire;
  54        nvm->word_size          = 64;
  55
  56        /* Function Pointers */
  57        nvm->ops.read           = e1000_read_nvm_microwire;
  58        nvm->ops.release        = e1000_stop_nvm;
  59        nvm->ops.write          = e1000_write_nvm_microwire;
  60        nvm->ops.update         = e1000_update_nvm_checksum_generic;
  61        nvm->ops.validate       = e1000_validate_nvm_checksum_generic;
  62
  63        return E1000_SUCCESS;
  64}
  65
  66/**
  67 *  e1000_init_mac_params_82542 - Init MAC func ptrs.
  68 *  @hw: pointer to the HW structure
  69 **/
  70STATIC s32 e1000_init_mac_params_82542(struct e1000_hw *hw)
  71{
  72        struct e1000_mac_info *mac = &hw->mac;
  73
  74        DEBUGFUNC("e1000_init_mac_params_82542");
  75
  76        /* Set media type */
  77        hw->phy.media_type = e1000_media_type_fiber;
  78
  79        /* Set mta register count */
  80        mac->mta_reg_count = 128;
  81        /* Set rar entry count */
  82        mac->rar_entry_count = E1000_RAR_ENTRIES;
  83
  84        /* Function pointers */
  85
  86        /* bus type/speed/width */
  87        mac->ops.get_bus_info = e1000_get_bus_info_82542;
  88        /* function id */
  89        mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
  90        /* reset */
  91        mac->ops.reset_hw = e1000_reset_hw_82542;
  92        /* hw initialization */
  93        mac->ops.init_hw = e1000_init_hw_82542;
  94        /* link setup */
  95        mac->ops.setup_link = e1000_setup_link_82542;
  96        /* phy/fiber/serdes setup */
  97        mac->ops.setup_physical_interface =
  98                                        e1000_setup_fiber_serdes_link_generic;
  99        /* check for link */
 100        mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
 101        /* multicast address update */
 102        mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 103        /* writing VFTA */
 104        mac->ops.write_vfta = e1000_write_vfta_generic;
 105        /* clearing VFTA */
 106        mac->ops.clear_vfta = e1000_clear_vfta_generic;
 107        /* read mac address */
 108        mac->ops.read_mac_addr = e1000_read_mac_addr_82542;
 109        /* set RAR */
 110        mac->ops.rar_set = e1000_rar_set_82542;
 111        /* turn on/off LED */
 112        mac->ops.led_on = e1000_led_on_82542;
 113        mac->ops.led_off = e1000_led_off_82542;
 114        /* clear hardware counters */
 115        mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82542;
 116        /* link info */
 117        mac->ops.get_link_up_info =
 118                                e1000_get_speed_and_duplex_fiber_serdes_generic;
 119
 120        return E1000_SUCCESS;
 121}
 122
 123/**
 124 *  e1000_init_function_pointers_82542 - Init func ptrs.
 125 *  @hw: pointer to the HW structure
 126 *
 127 *  Called to initialize all function pointers and parameters.
 128 **/
 129void e1000_init_function_pointers_82542(struct e1000_hw *hw)
 130{
 131        DEBUGFUNC("e1000_init_function_pointers_82542");
 132
 133        hw->mac.ops.init_params = e1000_init_mac_params_82542;
 134        hw->nvm.ops.init_params = e1000_init_nvm_params_82542;
 135        hw->phy.ops.init_params = e1000_init_phy_params_82542;
 136}
 137
 138/**
 139 *  e1000_get_bus_info_82542 - Obtain bus information for adapter
 140 *  @hw: pointer to the HW structure
 141 *
 142 *  This will obtain information about the HW bus for which the
 143 *  adapter is attached and stores it in the hw structure.
 144 **/
 145STATIC s32 e1000_get_bus_info_82542(struct e1000_hw *hw)
 146{
 147        DEBUGFUNC("e1000_get_bus_info_82542");
 148
 149        hw->bus.type = e1000_bus_type_pci;
 150        hw->bus.speed = e1000_bus_speed_unknown;
 151        hw->bus.width = e1000_bus_width_unknown;
 152
 153        return E1000_SUCCESS;
 154}
 155
 156/**
 157 *  e1000_reset_hw_82542 - Reset hardware
 158 *  @hw: pointer to the HW structure
 159 *
 160 *  This resets the hardware into a known state.
 161 **/
 162STATIC s32 e1000_reset_hw_82542(struct e1000_hw *hw)
 163{
 164        struct e1000_bus_info *bus = &hw->bus;
 165        s32 ret_val = E1000_SUCCESS;
 166        u32 ctrl;
 167
 168        DEBUGFUNC("e1000_reset_hw_82542");
 169
 170        if (hw->revision_id == E1000_REVISION_2) {
 171                DEBUGOUT("Disabling MWI on 82542 rev 2\n");
 172                e1000_pci_clear_mwi(hw);
 173        }
 174
 175        DEBUGOUT("Masking off all interrupts\n");
 176        E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
 177
 178        E1000_WRITE_REG(hw, E1000_RCTL, 0);
 179        E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
 180        E1000_WRITE_FLUSH(hw);
 181
 182        /*
 183         * Delay to allow any outstanding PCI transactions to complete before
 184         * resetting the device
 185         */
 186        msec_delay(10);
 187
 188        ctrl = E1000_READ_REG(hw, E1000_CTRL);
 189
 190        DEBUGOUT("Issuing a global reset to 82542/82543 MAC\n");
 191        E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
 192
 193        hw->nvm.ops.reload(hw);
 194        msec_delay(2);
 195
 196        E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
 197        E1000_READ_REG(hw, E1000_ICR);
 198
 199        if (hw->revision_id == E1000_REVISION_2) {
 200                if (bus->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
 201                        e1000_pci_set_mwi(hw);
 202        }
 203
 204        return ret_val;
 205}
 206
 207/**
 208 *  e1000_init_hw_82542 - Initialize hardware
 209 *  @hw: pointer to the HW structure
 210 *
 211 *  This inits the hardware readying it for operation.
 212 **/
 213STATIC s32 e1000_init_hw_82542(struct e1000_hw *hw)
 214{
 215        struct e1000_mac_info *mac = &hw->mac;
 216        struct e1000_dev_spec_82542 *dev_spec = &hw->dev_spec._82542;
 217        s32 ret_val = E1000_SUCCESS;
 218        u32 ctrl;
 219        u16 i;
 220
 221        DEBUGFUNC("e1000_init_hw_82542");
 222
 223        /* Disabling VLAN filtering */
 224        E1000_WRITE_REG(hw, E1000_VET, 0);
 225        mac->ops.clear_vfta(hw);
 226
 227        /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
 228        if (hw->revision_id == E1000_REVISION_2) {
 229                DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
 230                e1000_pci_clear_mwi(hw);
 231                E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST);
 232                E1000_WRITE_FLUSH(hw);
 233                msec_delay(5);
 234        }
 235
 236        /* Setup the receive address. */
 237        e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
 238
 239        /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
 240        if (hw->revision_id == E1000_REVISION_2) {
 241                E1000_WRITE_REG(hw, E1000_RCTL, 0);
 242                E1000_WRITE_FLUSH(hw);
 243                msec_delay(1);
 244                if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
 245                        e1000_pci_set_mwi(hw);
 246        }
 247
 248        /* Zero out the Multicast HASH table */
 249        DEBUGOUT("Zeroing the MTA\n");
 250        for (i = 0; i < mac->mta_reg_count; i++)
 251                E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 252
 253        /*
 254         * Set the PCI priority bit correctly in the CTRL register.  This
 255         * determines if the adapter gives priority to receives, or if it
 256         * gives equal priority to transmits and receives.
 257         */
 258        if (dev_spec->dma_fairness) {
 259                ctrl = E1000_READ_REG(hw, E1000_CTRL);
 260                E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);
 261        }
 262
 263        /* Setup link and flow control */
 264        ret_val = e1000_setup_link_82542(hw);
 265
 266        /*
 267         * Clear all of the statistics registers (clear on read).  It is
 268         * important that we do this after we have tried to establish link
 269         * because the symbol error count will increment wildly if there
 270         * is no link.
 271         */
 272        e1000_clear_hw_cntrs_82542(hw);
 273
 274        return ret_val;
 275}
 276
 277/**
 278 *  e1000_setup_link_82542 - Setup flow control and link settings
 279 *  @hw: pointer to the HW structure
 280 *
 281 *  Determines which flow control settings to use, then configures flow
 282 *  control.  Calls the appropriate media-specific link configuration
 283 *  function.  Assuming the adapter has a valid link partner, a valid link
 284 *  should be established.  Assumes the hardware has previously been reset
 285 *  and the transmitter and receiver are not enabled.
 286 **/
 287STATIC s32 e1000_setup_link_82542(struct e1000_hw *hw)
 288{
 289        struct e1000_mac_info *mac = &hw->mac;
 290        s32 ret_val;
 291
 292        DEBUGFUNC("e1000_setup_link_82542");
 293
 294        ret_val = e1000_set_default_fc_generic(hw);
 295        if (ret_val)
 296                goto out;
 297
 298        hw->fc.requested_mode &= ~e1000_fc_tx_pause;
 299
 300        if (mac->report_tx_early)
 301                hw->fc.requested_mode &= ~e1000_fc_rx_pause;
 302
 303        /*
 304         * Save off the requested flow control mode for use later.  Depending
 305         * on the link partner's capabilities, we may or may not use this mode.
 306         */
 307        hw->fc.current_mode = hw->fc.requested_mode;
 308
 309        DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
 310                  hw->fc.current_mode);
 311
 312        /* Call the necessary subroutine to configure the link. */
 313        ret_val = mac->ops.setup_physical_interface(hw);
 314        if (ret_val)
 315                goto out;
 316
 317        /*
 318         * Initialize the flow control address, type, and PAUSE timer
 319         * registers to their default values.  This is done even if flow
 320         * control is disabled, because it does not hurt anything to
 321         * initialize these registers.
 322         */
 323        DEBUGOUT("Initializing Flow Control address, type and timer regs\n");
 324
 325        E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
 326        E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
 327        E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
 328
 329        E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
 330
 331        ret_val = e1000_set_fc_watermarks_generic(hw);
 332
 333out:
 334        return ret_val;
 335}
 336
 337/**
 338 *  e1000_led_on_82542 - Turn on SW controllable LED
 339 *  @hw: pointer to the HW structure
 340 *
 341 *  Turns the SW defined LED on.
 342 **/
 343STATIC s32 e1000_led_on_82542(struct e1000_hw *hw)
 344{
 345        u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
 346
 347        DEBUGFUNC("e1000_led_on_82542");
 348
 349        ctrl |= E1000_CTRL_SWDPIN0;
 350        ctrl |= E1000_CTRL_SWDPIO0;
 351        E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
 352
 353        return E1000_SUCCESS;
 354}
 355
 356/**
 357 *  e1000_led_off_82542 - Turn off SW controllable LED
 358 *  @hw: pointer to the HW structure
 359 *
 360 *  Turns the SW defined LED off.
 361 **/
 362STATIC s32 e1000_led_off_82542(struct e1000_hw *hw)
 363{
 364        u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
 365
 366        DEBUGFUNC("e1000_led_off_82542");
 367
 368        ctrl &= ~E1000_CTRL_SWDPIN0;
 369        ctrl |= E1000_CTRL_SWDPIO0;
 370        E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
 371
 372        return E1000_SUCCESS;
 373}
 374
 375/**
 376 *  e1000_rar_set_82542 - Set receive address register
 377 *  @hw: pointer to the HW structure
 378 *  @addr: pointer to the receive address
 379 *  @index: receive address array register
 380 *
 381 *  Sets the receive address array register at index to the address passed
 382 *  in by addr.
 383 **/
 384STATIC int e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index)
 385{
 386        u32 rar_low, rar_high;
 387
 388        DEBUGFUNC("e1000_rar_set_82542");
 389
 390        /*
 391         * HW expects these in little endian so we reverse the byte order
 392         * from network order (big endian) to little endian
 393         */
 394        rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
 395                   ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
 396
 397        rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
 398
 399        /* If MAC address zero, no need to set the AV bit */
 400        if (rar_low || rar_high)
 401                rar_high |= E1000_RAH_AV;
 402
 403        E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low);
 404        E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high);
 405
 406        return E1000_SUCCESS;
 407}
 408
 409/**
 410 *  e1000_translate_register_82542 - Translate the proper register offset
 411 *  @reg: e1000 register to be read
 412 *
 413 *  Registers in 82542 are located in different offsets than other adapters
 414 *  even though they function in the same manner.  This function takes in
 415 *  the name of the register to read and returns the correct offset for
 416 *  82542 silicon.
 417 **/
 418u32 e1000_translate_register_82542(u32 reg)
 419{
 420        /*
 421         * Some of the 82542 registers are located at different
 422         * offsets than they are in newer adapters.
 423         * Despite the difference in location, the registers
 424         * function in the same manner.
 425         */
 426        switch (reg) {
 427        case E1000_RA:
 428                reg = 0x00040;
 429                break;
 430        case E1000_RDTR:
 431                reg = 0x00108;
 432                break;
 433        case E1000_RDBAL(0):
 434                reg = 0x00110;
 435                break;
 436        case E1000_RDBAH(0):
 437                reg = 0x00114;
 438                break;
 439        case E1000_RDLEN(0):
 440                reg = 0x00118;
 441                break;
 442        case E1000_RDH(0):
 443                reg = 0x00120;
 444                break;
 445        case E1000_RDT(0):
 446                reg = 0x00128;
 447                break;
 448        case E1000_RDBAL(1):
 449                reg = 0x00138;
 450                break;
 451        case E1000_RDBAH(1):
 452                reg = 0x0013C;
 453                break;
 454        case E1000_RDLEN(1):
 455                reg = 0x00140;
 456                break;
 457        case E1000_RDH(1):
 458                reg = 0x00148;
 459                break;
 460        case E1000_RDT(1):
 461                reg = 0x00150;
 462                break;
 463        case E1000_FCRTH:
 464                reg = 0x00160;
 465                break;
 466        case E1000_FCRTL:
 467                reg = 0x00168;
 468                break;
 469        case E1000_MTA:
 470                reg = 0x00200;
 471                break;
 472        case E1000_TDBAL(0):
 473                reg = 0x00420;
 474                break;
 475        case E1000_TDBAH(0):
 476                reg = 0x00424;
 477                break;
 478        case E1000_TDLEN(0):
 479                reg = 0x00428;
 480                break;
 481        case E1000_TDH(0):
 482                reg = 0x00430;
 483                break;
 484        case E1000_TDT(0):
 485                reg = 0x00438;
 486                break;
 487        case E1000_TIDV:
 488                reg = 0x00440;
 489                break;
 490        case E1000_VFTA:
 491                reg = 0x00600;
 492                break;
 493        case E1000_TDFH:
 494                reg = 0x08010;
 495                break;
 496        case E1000_TDFT:
 497                reg = 0x08018;
 498                break;
 499        default:
 500                break;
 501        }
 502
 503        return reg;
 504}
 505
 506/**
 507 *  e1000_clear_hw_cntrs_82542 - Clear device specific hardware counters
 508 *  @hw: pointer to the HW structure
 509 *
 510 *  Clears the hardware counters by reading the counter registers.
 511 **/
 512STATIC void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw)
 513{
 514        DEBUGFUNC("e1000_clear_hw_cntrs_82542");
 515
 516        e1000_clear_hw_cntrs_base_generic(hw);
 517
 518        E1000_READ_REG(hw, E1000_PRC64);
 519        E1000_READ_REG(hw, E1000_PRC127);
 520        E1000_READ_REG(hw, E1000_PRC255);
 521        E1000_READ_REG(hw, E1000_PRC511);
 522        E1000_READ_REG(hw, E1000_PRC1023);
 523        E1000_READ_REG(hw, E1000_PRC1522);
 524        E1000_READ_REG(hw, E1000_PTC64);
 525        E1000_READ_REG(hw, E1000_PTC127);
 526        E1000_READ_REG(hw, E1000_PTC255);
 527        E1000_READ_REG(hw, E1000_PTC511);
 528        E1000_READ_REG(hw, E1000_PTC1023);
 529        E1000_READ_REG(hw, E1000_PTC1522);
 530}
 531
 532/**
 533 *  e1000_read_mac_addr_82542 - Read device MAC address
 534 *  @hw: pointer to the HW structure
 535 *
 536 *  Reads the device MAC address from the EEPROM and stores the value.
 537 **/
 538s32 e1000_read_mac_addr_82542(struct e1000_hw *hw)
 539{
 540        s32  ret_val = E1000_SUCCESS;
 541        u16 offset, nvm_data, i;
 542
 543        DEBUGFUNC("e1000_read_mac_addr");
 544
 545        for (i = 0; i < ETH_ADDR_LEN; i += 2) {
 546                offset = i >> 1;
 547                ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
 548                if (ret_val) {
 549                        DEBUGOUT("NVM Read Error\n");
 550                        goto out;
 551                }
 552                hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
 553                hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
 554        }
 555
 556        for (i = 0; i < ETH_ADDR_LEN; i++)
 557                hw->mac.addr[i] = hw->mac.perm_addr[i];
 558
 559out:
 560        return ret_val;
 561}
 562