1
2
3
4
5#ifndef _ENA_ADMIN_H_
6#define _ENA_ADMIN_H_
7
8#define ENA_ADMIN_RSS_KEY_PARTS 10
9
10enum ena_admin_aq_opcode {
11 ENA_ADMIN_CREATE_SQ = 1,
12 ENA_ADMIN_DESTROY_SQ = 2,
13 ENA_ADMIN_CREATE_CQ = 3,
14 ENA_ADMIN_DESTROY_CQ = 4,
15 ENA_ADMIN_GET_FEATURE = 8,
16 ENA_ADMIN_SET_FEATURE = 9,
17 ENA_ADMIN_GET_STATS = 11,
18};
19
20enum ena_admin_aq_completion_status {
21 ENA_ADMIN_SUCCESS = 0,
22 ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1,
23 ENA_ADMIN_BAD_OPCODE = 2,
24 ENA_ADMIN_UNSUPPORTED_OPCODE = 3,
25 ENA_ADMIN_MALFORMED_REQUEST = 4,
26
27 ENA_ADMIN_ILLEGAL_PARAMETER = 5,
28 ENA_ADMIN_UNKNOWN_ERROR = 6,
29 ENA_ADMIN_RESOURCE_BUSY = 7,
30};
31
32
33enum ena_admin_aq_feature_id {
34 ENA_ADMIN_DEVICE_ATTRIBUTES = 1,
35 ENA_ADMIN_MAX_QUEUES_NUM = 2,
36 ENA_ADMIN_HW_HINTS = 3,
37 ENA_ADMIN_LLQ = 4,
38 ENA_ADMIN_EXTRA_PROPERTIES_STRINGS = 5,
39 ENA_ADMIN_EXTRA_PROPERTIES_FLAGS = 6,
40 ENA_ADMIN_MAX_QUEUES_EXT = 7,
41 ENA_ADMIN_RSS_HASH_FUNCTION = 10,
42 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11,
43 ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG = 12,
44 ENA_ADMIN_MTU = 14,
45 ENA_ADMIN_RSS_HASH_INPUT = 18,
46 ENA_ADMIN_INTERRUPT_MODERATION = 20,
47 ENA_ADMIN_AENQ_CONFIG = 26,
48 ENA_ADMIN_LINK_CONFIG = 27,
49 ENA_ADMIN_HOST_ATTR_CONFIG = 28,
50 ENA_ADMIN_FEATURES_OPCODE_NUM = 32,
51};
52
53enum ena_admin_placement_policy_type {
54
55 ENA_ADMIN_PLACEMENT_POLICY_HOST = 1,
56
57
58
59 ENA_ADMIN_PLACEMENT_POLICY_DEV = 3,
60};
61
62enum ena_admin_link_types {
63 ENA_ADMIN_LINK_SPEED_1G = 0x1,
64 ENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2,
65 ENA_ADMIN_LINK_SPEED_5G = 0x4,
66 ENA_ADMIN_LINK_SPEED_10G = 0x8,
67 ENA_ADMIN_LINK_SPEED_25G = 0x10,
68 ENA_ADMIN_LINK_SPEED_40G = 0x20,
69 ENA_ADMIN_LINK_SPEED_50G = 0x40,
70 ENA_ADMIN_LINK_SPEED_100G = 0x80,
71 ENA_ADMIN_LINK_SPEED_200G = 0x100,
72 ENA_ADMIN_LINK_SPEED_400G = 0x200,
73};
74
75enum ena_admin_completion_policy_type {
76
77 ENA_ADMIN_COMPLETION_POLICY_DESC = 0,
78
79 ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1,
80
81
82
83 ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2,
84
85
86
87 ENA_ADMIN_COMPLETION_POLICY_HEAD = 3,
88};
89
90
91
92
93
94enum ena_admin_get_stats_type {
95 ENA_ADMIN_GET_STATS_TYPE_BASIC = 0,
96 ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1,
97
98 ENA_ADMIN_GET_STATS_TYPE_ENI = 2,
99};
100
101enum ena_admin_get_stats_scope {
102 ENA_ADMIN_SPECIFIC_QUEUE = 0,
103 ENA_ADMIN_ETH_TRAFFIC = 1,
104};
105
106struct ena_admin_aq_common_desc {
107
108
109
110 uint16_t command_id;
111
112
113 uint8_t opcode;
114
115
116
117
118
119
120
121
122 uint8_t flags;
123};
124
125
126
127
128
129struct ena_admin_ctrl_buff_info {
130 uint32_t length;
131
132 struct ena_common_mem_addr address;
133};
134
135struct ena_admin_sq {
136 uint16_t sq_idx;
137
138
139
140
141 uint8_t sq_identity;
142
143 uint8_t reserved1;
144};
145
146struct ena_admin_aq_entry {
147 struct ena_admin_aq_common_desc aq_common_descriptor;
148
149 union {
150 uint32_t inline_data_w1[3];
151
152 struct ena_admin_ctrl_buff_info control_buffer;
153 } u;
154
155 uint32_t inline_data_w4[12];
156};
157
158struct ena_admin_acq_common_desc {
159
160
161
162
163 uint16_t command;
164
165 uint8_t status;
166
167
168
169
170 uint8_t flags;
171
172 uint16_t extended_status;
173
174
175
176
177 uint16_t sq_head_indx;
178};
179
180struct ena_admin_acq_entry {
181 struct ena_admin_acq_common_desc acq_common_descriptor;
182
183 uint32_t response_specific_data[14];
184};
185
186struct ena_admin_aq_create_sq_cmd {
187 struct ena_admin_aq_common_desc aq_common_descriptor;
188
189
190
191
192 uint8_t sq_identity;
193
194 uint8_t reserved8_w1;
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211 uint8_t sq_caps_2;
212
213
214
215
216
217
218 uint8_t sq_caps_3;
219
220
221
222
223 uint16_t cq_idx;
224
225
226 uint16_t sq_depth;
227
228
229
230
231 struct ena_common_mem_addr sq_ba;
232
233
234
235
236
237 struct ena_common_mem_addr sq_head_writeback;
238
239 uint32_t reserved0_w7;
240
241 uint32_t reserved0_w8;
242};
243
244enum ena_admin_sq_direction {
245 ENA_ADMIN_SQ_DIRECTION_TX = 1,
246 ENA_ADMIN_SQ_DIRECTION_RX = 2,
247};
248
249struct ena_admin_acq_create_sq_resp_desc {
250 struct ena_admin_acq_common_desc acq_common_desc;
251
252 uint16_t sq_idx;
253
254 uint16_t reserved;
255
256
257 uint32_t sq_doorbell_offset;
258
259
260
261
262 uint32_t llq_descriptors_offset;
263
264
265
266
267 uint32_t llq_headers_offset;
268};
269
270struct ena_admin_aq_destroy_sq_cmd {
271 struct ena_admin_aq_common_desc aq_common_descriptor;
272
273 struct ena_admin_sq sq;
274};
275
276struct ena_admin_acq_destroy_sq_resp_desc {
277 struct ena_admin_acq_common_desc acq_common_desc;
278};
279
280struct ena_admin_aq_create_cq_cmd {
281 struct ena_admin_aq_common_desc aq_common_descriptor;
282
283
284
285
286
287
288 uint8_t cq_caps_1;
289
290
291
292
293
294 uint8_t cq_caps_2;
295
296
297 uint16_t cq_depth;
298
299
300 uint32_t msix_vector;
301
302
303
304
305 struct ena_common_mem_addr cq_ba;
306};
307
308struct ena_admin_acq_create_cq_resp_desc {
309 struct ena_admin_acq_common_desc acq_common_desc;
310
311 uint16_t cq_idx;
312
313
314 uint16_t cq_actual_depth;
315
316 uint32_t numa_node_register_offset;
317
318 uint32_t cq_head_db_register_offset;
319
320 uint32_t cq_interrupt_unmask_register_offset;
321};
322
323struct ena_admin_aq_destroy_cq_cmd {
324 struct ena_admin_aq_common_desc aq_common_descriptor;
325
326 uint16_t cq_idx;
327
328 uint16_t reserved1;
329};
330
331struct ena_admin_acq_destroy_cq_resp_desc {
332 struct ena_admin_acq_common_desc acq_common_desc;
333};
334
335
336
337
338struct ena_admin_aq_get_stats_cmd {
339 struct ena_admin_aq_common_desc aq_common_descriptor;
340
341 union {
342
343 uint32_t inline_data_w1[3];
344
345 struct ena_admin_ctrl_buff_info control_buffer;
346 } u;
347
348
349 uint8_t type;
350
351
352 uint8_t scope;
353
354 uint16_t reserved3;
355
356
357 uint16_t queue_idx;
358
359
360
361
362 uint16_t device_id;
363};
364
365
366struct ena_admin_basic_stats {
367 uint32_t tx_bytes_low;
368
369 uint32_t tx_bytes_high;
370
371 uint32_t tx_pkts_low;
372
373 uint32_t tx_pkts_high;
374
375 uint32_t rx_bytes_low;
376
377 uint32_t rx_bytes_high;
378
379 uint32_t rx_pkts_low;
380
381 uint32_t rx_pkts_high;
382
383 uint32_t rx_drops_low;
384
385 uint32_t rx_drops_high;
386
387 uint32_t tx_drops_low;
388
389 uint32_t tx_drops_high;
390};
391
392
393struct ena_admin_eni_stats {
394
395
396
397 uint64_t bw_in_allowance_exceeded;
398
399
400
401
402 uint64_t bw_out_allowance_exceeded;
403
404
405 uint64_t pps_allowance_exceeded;
406
407
408
409
410
411 uint64_t conntrack_allowance_exceeded;
412
413
414
415
416 uint64_t linklocal_allowance_exceeded;
417};
418
419struct ena_admin_acq_get_stats_resp {
420 struct ena_admin_acq_common_desc acq_common_desc;
421
422 union {
423 uint64_t raw[7];
424
425 struct ena_admin_basic_stats basic_stats;
426
427 struct ena_admin_eni_stats eni_stats;
428 } u;
429};
430
431struct ena_admin_get_set_feature_common_desc {
432
433
434
435
436 uint8_t flags;
437
438
439 uint8_t feature_id;
440
441
442
443
444
445 uint8_t feature_version;
446
447 uint8_t reserved8;
448};
449
450struct ena_admin_device_attr_feature_desc {
451 uint32_t impl_id;
452
453 uint32_t device_version;
454
455
456
457
458 uint32_t supported_features;
459
460 uint32_t reserved3;
461
462
463 uint32_t phys_addr_width;
464
465
466 uint32_t virt_addr_width;
467
468
469 uint8_t mac_addr[6];
470
471 uint8_t reserved7[2];
472
473 uint32_t max_mtu;
474};
475
476enum ena_admin_llq_header_location {
477
478 ENA_ADMIN_INLINE_HEADER = 1,
479
480 ENA_ADMIN_HEADER_RING = 2,
481};
482
483enum ena_admin_llq_ring_entry_size {
484 ENA_ADMIN_LIST_ENTRY_SIZE_128B = 1,
485 ENA_ADMIN_LIST_ENTRY_SIZE_192B = 2,
486 ENA_ADMIN_LIST_ENTRY_SIZE_256B = 4,
487};
488
489enum ena_admin_llq_num_descs_before_header {
490 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0 = 0,
491 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1 = 1,
492 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2 = 2,
493 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4 = 4,
494 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8 = 8,
495};
496
497
498
499
500
501
502
503enum ena_admin_llq_stride_ctrl {
504 ENA_ADMIN_SINGLE_DESC_PER_ENTRY = 1,
505 ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY = 2,
506};
507
508enum ena_admin_accel_mode_feat {
509 ENA_ADMIN_DISABLE_META_CACHING = 0,
510 ENA_ADMIN_LIMIT_TX_BURST = 1,
511};
512
513struct ena_admin_accel_mode_get {
514
515 uint16_t supported_flags;
516
517
518 uint16_t max_tx_burst_size;
519};
520
521struct ena_admin_accel_mode_set {
522
523 uint16_t enabled_flags;
524
525 uint16_t reserved;
526};
527
528struct ena_admin_accel_mode_req {
529 union {
530 uint32_t raw[2];
531
532 struct ena_admin_accel_mode_get get;
533
534 struct ena_admin_accel_mode_set set;
535 } u;
536};
537
538struct ena_admin_feature_llq_desc {
539 uint32_t max_llq_num;
540
541 uint32_t max_llq_depth;
542
543
544
545
546 uint16_t header_location_ctrl_supported;
547
548
549 uint16_t header_location_ctrl_enabled;
550
551
552
553
554
555
556 uint16_t entry_size_ctrl_supported;
557
558
559 uint16_t entry_size_ctrl_enabled;
560
561
562
563
564
565
566
567
568 uint16_t desc_num_before_header_supported;
569
570
571 uint16_t desc_num_before_header_enabled;
572
573
574
575
576 uint16_t descriptors_stride_ctrl_supported;
577
578
579 uint16_t descriptors_stride_ctrl_enabled;
580
581
582 uint32_t reserved1;
583
584
585
586
587 struct ena_admin_accel_mode_req accel_mode;
588};
589
590struct ena_admin_queue_ext_feature_fields {
591 uint32_t max_tx_sq_num;
592
593 uint32_t max_tx_cq_num;
594
595 uint32_t max_rx_sq_num;
596
597 uint32_t max_rx_cq_num;
598
599 uint32_t max_tx_sq_depth;
600
601 uint32_t max_tx_cq_depth;
602
603 uint32_t max_rx_sq_depth;
604
605 uint32_t max_rx_cq_depth;
606
607 uint32_t max_tx_header_size;
608
609
610
611
612 uint16_t max_per_packet_tx_descs;
613
614
615 uint16_t max_per_packet_rx_descs;
616};
617
618struct ena_admin_queue_feature_desc {
619 uint32_t max_sq_num;
620
621 uint32_t max_sq_depth;
622
623 uint32_t max_cq_num;
624
625 uint32_t max_cq_depth;
626
627 uint32_t max_legacy_llq_num;
628
629 uint32_t max_legacy_llq_depth;
630
631 uint32_t max_header_size;
632
633
634
635
636 uint16_t max_packet_tx_descs;
637
638
639 uint16_t max_packet_rx_descs;
640};
641
642struct ena_admin_set_feature_mtu_desc {
643
644 uint32_t mtu;
645};
646
647struct ena_admin_get_extra_properties_strings_desc {
648 uint32_t count;
649};
650
651struct ena_admin_get_extra_properties_flags_desc {
652 uint32_t flags;
653};
654
655struct ena_admin_set_feature_host_attr_desc {
656
657
658
659 struct ena_common_mem_addr os_info_ba;
660
661
662
663
664 struct ena_common_mem_addr debug_ba;
665
666
667 uint32_t debug_area_size;
668};
669
670struct ena_admin_feature_intr_moder_desc {
671
672 uint16_t intr_delay_resolution;
673
674 uint16_t reserved;
675};
676
677struct ena_admin_get_feature_link_desc {
678
679 uint32_t speed;
680
681
682 uint32_t supported;
683
684
685
686
687
688 uint32_t flags;
689};
690
691struct ena_admin_feature_aenq_desc {
692
693 uint32_t supported_groups;
694
695
696 uint32_t enabled_groups;
697};
698
699struct ena_admin_feature_offload_desc {
700
701
702
703
704
705
706
707
708
709
710
711 uint32_t tx;
712
713
714
715
716
717
718
719 uint32_t rx_supported;
720
721 uint32_t rx_enabled;
722};
723
724enum ena_admin_hash_functions {
725 ENA_ADMIN_TOEPLITZ = 1,
726 ENA_ADMIN_CRC32 = 2,
727};
728
729struct ena_admin_feature_rss_flow_hash_control {
730 uint32_t key_parts;
731
732 uint32_t reserved;
733
734 uint32_t key[ENA_ADMIN_RSS_KEY_PARTS];
735};
736
737struct ena_admin_feature_rss_flow_hash_function {
738
739 uint32_t supported_func;
740
741
742
743
744 uint32_t selected_func;
745
746
747 uint32_t init_val;
748};
749
750
751enum ena_admin_flow_hash_proto {
752 ENA_ADMIN_RSS_TCP4 = 0,
753 ENA_ADMIN_RSS_UDP4 = 1,
754 ENA_ADMIN_RSS_TCP6 = 2,
755 ENA_ADMIN_RSS_UDP6 = 3,
756 ENA_ADMIN_RSS_IP4 = 4,
757 ENA_ADMIN_RSS_IP6 = 5,
758 ENA_ADMIN_RSS_IP4_FRAG = 6,
759 ENA_ADMIN_RSS_NOT_IP = 7,
760
761 ENA_ADMIN_RSS_TCP6_EX = 8,
762
763 ENA_ADMIN_RSS_IP6_EX = 9,
764 ENA_ADMIN_RSS_PROTO_NUM = 16,
765};
766
767
768enum ena_admin_flow_hash_fields {
769
770 ENA_ADMIN_RSS_L2_DA = BIT(0),
771
772 ENA_ADMIN_RSS_L2_SA = BIT(1),
773
774 ENA_ADMIN_RSS_L3_DA = BIT(2),
775
776 ENA_ADMIN_RSS_L3_SA = BIT(3),
777
778 ENA_ADMIN_RSS_L4_DP = BIT(4),
779
780 ENA_ADMIN_RSS_L4_SP = BIT(5),
781};
782
783struct ena_admin_proto_input {
784
785 uint16_t fields;
786
787 uint16_t reserved2;
788};
789
790struct ena_admin_feature_rss_hash_control {
791 struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM];
792
793 struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM];
794
795 struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM];
796
797 struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM];
798};
799
800struct ena_admin_feature_rss_flow_hash_input {
801
802
803
804
805
806
807 uint16_t supported_input_sort;
808
809
810
811
812
813
814
815 uint16_t enabled_input_sort;
816};
817
818enum ena_admin_os_type {
819 ENA_ADMIN_OS_LINUX = 1,
820 ENA_ADMIN_OS_WIN = 2,
821 ENA_ADMIN_OS_DPDK = 3,
822 ENA_ADMIN_OS_FREEBSD = 4,
823 ENA_ADMIN_OS_IPXE = 5,
824 ENA_ADMIN_OS_ESXI = 6,
825 ENA_ADMIN_OS_GROUPS_NUM = 6,
826};
827
828struct ena_admin_host_info {
829
830 uint32_t os_type;
831
832
833 uint8_t os_dist_str[128];
834
835
836 uint32_t os_dist;
837
838
839 uint8_t kernel_ver_str[32];
840
841
842 uint32_t kernel_ver;
843
844
845
846
847
848
849 uint32_t driver_version;
850
851
852 uint32_t supported_network_features[2];
853
854
855 uint16_t ena_spec_version;
856
857
858
859
860
861
862 uint16_t bdf;
863
864
865 uint16_t num_cpus;
866
867 uint16_t reserved;
868
869
870
871
872
873
874
875
876 uint32_t driver_supported_features;
877};
878
879struct ena_admin_rss_ind_table_entry {
880 uint16_t cq_idx;
881
882 uint16_t reserved;
883};
884
885struct ena_admin_feature_rss_ind_table {
886
887 uint16_t min_size;
888
889
890 uint16_t max_size;
891
892
893 uint16_t size;
894
895
896
897
898 uint8_t flags;
899
900 uint8_t reserved;
901
902
903 uint32_t inline_index;
904
905
906
907
908 struct ena_admin_rss_ind_table_entry inline_entry;
909};
910
911
912struct ena_admin_ena_hw_hints {
913
914 uint16_t mmio_read_timeout;
915
916
917 uint16_t driver_watchdog_timeout;
918
919
920 uint16_t missing_tx_completion_timeout;
921
922 uint16_t missed_tx_completion_count_threshold_to_reset;
923
924
925 uint16_t admin_completion_tx_timeout;
926
927 uint16_t netdev_wd_timeout;
928
929 uint16_t max_tx_sgl_size;
930
931 uint16_t max_rx_sgl_size;
932
933 uint16_t reserved[8];
934};
935
936struct ena_admin_get_feat_cmd {
937 struct ena_admin_aq_common_desc aq_common_descriptor;
938
939 struct ena_admin_ctrl_buff_info control_buffer;
940
941 struct ena_admin_get_set_feature_common_desc feat_common;
942
943 uint32_t raw[11];
944};
945
946struct ena_admin_queue_ext_feature_desc {
947
948 uint8_t version;
949
950 uint8_t reserved1[3];
951
952 union {
953 struct ena_admin_queue_ext_feature_fields max_queue_ext;
954
955 uint32_t raw[10];
956 };
957};
958
959struct ena_admin_get_feat_resp {
960 struct ena_admin_acq_common_desc acq_common_desc;
961
962 union {
963 uint32_t raw[14];
964
965 struct ena_admin_device_attr_feature_desc dev_attr;
966
967 struct ena_admin_feature_llq_desc llq;
968
969 struct ena_admin_queue_feature_desc max_queue;
970
971 struct ena_admin_queue_ext_feature_desc max_queue_ext;
972
973 struct ena_admin_feature_aenq_desc aenq;
974
975 struct ena_admin_get_feature_link_desc link;
976
977 struct ena_admin_feature_offload_desc offload;
978
979 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
980
981 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
982
983 struct ena_admin_feature_rss_ind_table ind_table;
984
985 struct ena_admin_feature_intr_moder_desc intr_moderation;
986
987 struct ena_admin_ena_hw_hints hw_hints;
988
989 struct ena_admin_get_extra_properties_strings_desc extra_properties_strings;
990
991 struct ena_admin_get_extra_properties_flags_desc extra_properties_flags;
992 } u;
993};
994
995struct ena_admin_set_feat_cmd {
996 struct ena_admin_aq_common_desc aq_common_descriptor;
997
998 struct ena_admin_ctrl_buff_info control_buffer;
999
1000 struct ena_admin_get_set_feature_common_desc feat_common;
1001
1002 union {
1003 uint32_t raw[11];
1004
1005
1006 struct ena_admin_set_feature_mtu_desc mtu;
1007
1008
1009 struct ena_admin_set_feature_host_attr_desc host_attr;
1010
1011
1012 struct ena_admin_feature_aenq_desc aenq;
1013
1014
1015 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
1016
1017
1018 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
1019
1020
1021 struct ena_admin_feature_rss_ind_table ind_table;
1022
1023
1024 struct ena_admin_feature_llq_desc llq;
1025 } u;
1026};
1027
1028struct ena_admin_set_feat_resp {
1029 struct ena_admin_acq_common_desc acq_common_desc;
1030
1031 union {
1032 uint32_t raw[14];
1033 } u;
1034};
1035
1036struct ena_admin_aenq_common_desc {
1037 uint16_t group;
1038
1039 uint16_t syndrome;
1040
1041
1042
1043
1044 uint8_t flags;
1045
1046 uint8_t reserved1[3];
1047
1048 uint32_t timestamp_low;
1049
1050 uint32_t timestamp_high;
1051};
1052
1053
1054enum ena_admin_aenq_group {
1055 ENA_ADMIN_LINK_CHANGE = 0,
1056 ENA_ADMIN_FATAL_ERROR = 1,
1057 ENA_ADMIN_WARNING = 2,
1058 ENA_ADMIN_NOTIFICATION = 3,
1059 ENA_ADMIN_KEEP_ALIVE = 4,
1060 ENA_ADMIN_AENQ_GROUPS_NUM = 5,
1061};
1062
1063enum ena_admin_aenq_notification_syndrome {
1064 ENA_ADMIN_SUSPEND = 0,
1065 ENA_ADMIN_RESUME = 1,
1066 ENA_ADMIN_UPDATE_HINTS = 2,
1067};
1068
1069struct ena_admin_aenq_entry {
1070 struct ena_admin_aenq_common_desc aenq_common_desc;
1071
1072
1073 uint32_t inline_data_w4[12];
1074};
1075
1076struct ena_admin_aenq_link_change_desc {
1077 struct ena_admin_aenq_common_desc aenq_common_desc;
1078
1079
1080 uint32_t flags;
1081};
1082
1083struct ena_admin_aenq_keep_alive_desc {
1084 struct ena_admin_aenq_common_desc aenq_common_desc;
1085
1086 uint32_t rx_drops_low;
1087
1088 uint32_t rx_drops_high;
1089
1090 uint32_t tx_drops_low;
1091
1092 uint32_t tx_drops_high;
1093};
1094
1095struct ena_admin_ena_mmio_req_read_less_resp {
1096 uint16_t req_id;
1097
1098 uint16_t reg_off;
1099
1100
1101 uint32_t reg_val;
1102};
1103
1104
1105#define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
1106#define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0)
1107#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1
1108#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1)
1109#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2
1110#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2)
1111
1112
1113#define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5
1114#define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5)
1115
1116
1117#define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
1118#define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0)
1119
1120
1121#define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5
1122#define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5)
1123#define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0)
1124#define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4
1125#define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4)
1126#define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0)
1127
1128
1129#define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5
1130#define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5)
1131#define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
1132
1133
1134#define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0)
1135
1136
1137#define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0)
1138#define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1
1139#define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1)
1140
1141
1142#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0)
1143#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1
1144#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1)
1145#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2
1146#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2)
1147#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3
1148#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3)
1149#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4
1150#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4)
1151#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5
1152#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5)
1153#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6
1154#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6)
1155#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7
1156#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7)
1157#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0)
1158#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1
1159#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1)
1160#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2
1161#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2)
1162#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3
1163#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3)
1164
1165
1166#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)
1167#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0)
1168
1169
1170#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1
1171#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1)
1172#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2
1173#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2)
1174#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1
1175#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1)
1176#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2
1177#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2)
1178
1179
1180#define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0)
1181#define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8
1182#define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8)
1183#define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16
1184#define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16)
1185#define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT 24
1186#define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24)
1187#define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0)
1188#define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT 3
1189#define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3)
1190#define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8
1191#define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8)
1192#define ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT 1
1193#define ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK BIT(1)
1194#define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT 2
1195#define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK BIT(2)
1196#define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT 3
1197#define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK BIT(3)
1198#define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT 4
1199#define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK BIT(4)
1200
1201
1202#define ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK BIT(0)
1203
1204
1205#define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0)
1206
1207
1208#define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0)
1209
1210#if !defined(DEFS_LINUX_MAINLINE)
1211static inline uint16_t get_ena_admin_aq_common_desc_command_id(const struct ena_admin_aq_common_desc *p)
1212{
1213 return p->command_id & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
1214}
1215
1216static inline void set_ena_admin_aq_common_desc_command_id(struct ena_admin_aq_common_desc *p, uint16_t val)
1217{
1218 p->command_id |= val & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
1219}
1220
1221static inline uint8_t get_ena_admin_aq_common_desc_phase(const struct ena_admin_aq_common_desc *p)
1222{
1223 return p->flags & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
1224}
1225
1226static inline void set_ena_admin_aq_common_desc_phase(struct ena_admin_aq_common_desc *p, uint8_t val)
1227{
1228 p->flags |= val & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
1229}
1230
1231static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data(const struct ena_admin_aq_common_desc *p)
1232{
1233 return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT;
1234}
1235
1236static inline void set_ena_admin_aq_common_desc_ctrl_data(struct ena_admin_aq_common_desc *p, uint8_t val)
1237{
1238 p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK;
1239}
1240
1241static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data_indirect(const struct ena_admin_aq_common_desc *p)
1242{
1243 return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT;
1244}
1245
1246static inline void set_ena_admin_aq_common_desc_ctrl_data_indirect(struct ena_admin_aq_common_desc *p, uint8_t val)
1247{
1248 p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
1249}
1250
1251static inline uint8_t get_ena_admin_sq_sq_direction(const struct ena_admin_sq *p)
1252{
1253 return (p->sq_identity & ENA_ADMIN_SQ_SQ_DIRECTION_MASK) >> ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT;
1254}
1255
1256static inline void set_ena_admin_sq_sq_direction(struct ena_admin_sq *p, uint8_t val)
1257{
1258 p->sq_identity |= (val << ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) & ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
1259}
1260
1261static inline uint16_t get_ena_admin_acq_common_desc_command_id(const struct ena_admin_acq_common_desc *p)
1262{
1263 return p->command & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
1264}
1265
1266static inline void set_ena_admin_acq_common_desc_command_id(struct ena_admin_acq_common_desc *p, uint16_t val)
1267{
1268 p->command |= val & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
1269}
1270
1271static inline uint8_t get_ena_admin_acq_common_desc_phase(const struct ena_admin_acq_common_desc *p)
1272{
1273 return p->flags & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK;
1274}
1275
1276static inline void set_ena_admin_acq_common_desc_phase(struct ena_admin_acq_common_desc *p, uint8_t val)
1277{
1278 p->flags |= val & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK;
1279}
1280
1281static inline uint8_t get_ena_admin_aq_create_sq_cmd_sq_direction(const struct ena_admin_aq_create_sq_cmd *p)
1282{
1283 return (p->sq_identity & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT;
1284}
1285
1286static inline void set_ena_admin_aq_create_sq_cmd_sq_direction(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1287{
1288 p->sq_identity |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1289}
1290
1291static inline uint8_t get_ena_admin_aq_create_sq_cmd_placement_policy(const struct ena_admin_aq_create_sq_cmd *p)
1292{
1293 return p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1294}
1295
1296static inline void set_ena_admin_aq_create_sq_cmd_placement_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1297{
1298 p->sq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1299}
1300
1301static inline uint8_t get_ena_admin_aq_create_sq_cmd_completion_policy(const struct ena_admin_aq_create_sq_cmd *p)
1302{
1303 return (p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT;
1304}
1305
1306static inline void set_ena_admin_aq_create_sq_cmd_completion_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1307{
1308 p->sq_caps_2 |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1309}
1310
1311static inline uint8_t get_ena_admin_aq_create_sq_cmd_is_physically_contiguous(const struct ena_admin_aq_create_sq_cmd *p)
1312{
1313 return p->sq_caps_3 & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1314}
1315
1316static inline void set_ena_admin_aq_create_sq_cmd_is_physically_contiguous(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1317{
1318 p->sq_caps_3 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1319}
1320
1321static inline uint8_t get_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(const struct ena_admin_aq_create_cq_cmd *p)
1322{
1323 return (p->cq_caps_1 & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK) >> ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT;
1324}
1325
1326static inline void set_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(struct ena_admin_aq_create_cq_cmd *p, uint8_t val)
1327{
1328 p->cq_caps_1 |= (val << ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT) & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1329}
1330
1331static inline uint8_t get_ena_admin_aq_create_cq_cmd_cq_entry_size_words(const struct ena_admin_aq_create_cq_cmd *p)
1332{
1333 return p->cq_caps_2 & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1334}
1335
1336static inline void set_ena_admin_aq_create_cq_cmd_cq_entry_size_words(struct ena_admin_aq_create_cq_cmd *p, uint8_t val)
1337{
1338 p->cq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1339}
1340
1341static inline uint8_t get_ena_admin_get_set_feature_common_desc_select(const struct ena_admin_get_set_feature_common_desc *p)
1342{
1343 return p->flags & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK;
1344}
1345
1346static inline void set_ena_admin_get_set_feature_common_desc_select(struct ena_admin_get_set_feature_common_desc *p, uint8_t val)
1347{
1348 p->flags |= val & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK;
1349}
1350
1351static inline uint32_t get_ena_admin_get_feature_link_desc_autoneg(const struct ena_admin_get_feature_link_desc *p)
1352{
1353 return p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK;
1354}
1355
1356static inline void set_ena_admin_get_feature_link_desc_autoneg(struct ena_admin_get_feature_link_desc *p, uint32_t val)
1357{
1358 p->flags |= val & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK;
1359}
1360
1361static inline uint32_t get_ena_admin_get_feature_link_desc_duplex(const struct ena_admin_get_feature_link_desc *p)
1362{
1363 return (p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK) >> ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT;
1364}
1365
1366static inline void set_ena_admin_get_feature_link_desc_duplex(struct ena_admin_get_feature_link_desc *p, uint32_t val)
1367{
1368 p->flags |= (val << ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT) & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK;
1369}
1370
1371static inline uint32_t get_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p)
1372{
1373 return p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK;
1374}
1375
1376static inline void set_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1377{
1378 p->tx |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK;
1379}
1380
1381static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(const struct ena_admin_feature_offload_desc *p)
1382{
1383 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT;
1384}
1385
1386static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val)
1387{
1388 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK;
1389}
1390
1391static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(const struct ena_admin_feature_offload_desc *p)
1392{
1393 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT;
1394}
1395
1396static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val)
1397{
1398 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK;
1399}
1400
1401static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(const struct ena_admin_feature_offload_desc *p)
1402{
1403 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT;
1404}
1405
1406static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val)
1407{
1408 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK;
1409}
1410
1411static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(const struct ena_admin_feature_offload_desc *p)
1412{
1413 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT;
1414}
1415
1416static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val)
1417{
1418 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK;
1419}
1420
1421static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv4(const struct ena_admin_feature_offload_desc *p)
1422{
1423 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT;
1424}
1425
1426static inline void set_ena_admin_feature_offload_desc_tso_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1427{
1428 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1429}
1430
1431static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv6(const struct ena_admin_feature_offload_desc *p)
1432{
1433 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT;
1434}
1435
1436static inline void set_ena_admin_feature_offload_desc_tso_ipv6(struct ena_admin_feature_offload_desc *p, uint32_t val)
1437{
1438 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK;
1439}
1440
1441static inline uint32_t get_ena_admin_feature_offload_desc_tso_ecn(const struct ena_admin_feature_offload_desc *p)
1442{
1443 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT;
1444}
1445
1446static inline void set_ena_admin_feature_offload_desc_tso_ecn(struct ena_admin_feature_offload_desc *p, uint32_t val)
1447{
1448 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK;
1449}
1450
1451static inline uint32_t get_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p)
1452{
1453 return p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;
1454}
1455
1456static inline void set_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1457{
1458 p->rx_supported |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;
1459}
1460
1461static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(const struct ena_admin_feature_offload_desc *p)
1462{
1463 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT;
1464}
1465
1466static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(struct ena_admin_feature_offload_desc *p, uint32_t val)
1467{
1468 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK;
1469}
1470
1471static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(const struct ena_admin_feature_offload_desc *p)
1472{
1473 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT;
1474}
1475
1476static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(struct ena_admin_feature_offload_desc *p, uint32_t val)
1477{
1478 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK;
1479}
1480
1481static inline uint32_t get_ena_admin_feature_offload_desc_RX_hash(const struct ena_admin_feature_offload_desc *p)
1482{
1483 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT;
1484}
1485
1486static inline void set_ena_admin_feature_offload_desc_RX_hash(struct ena_admin_feature_offload_desc *p, uint32_t val)
1487{
1488 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK;
1489}
1490
1491static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_funcs(const struct ena_admin_feature_rss_flow_hash_function *p)
1492{
1493 return p->supported_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;
1494}
1495
1496static inline void set_ena_admin_feature_rss_flow_hash_function_funcs(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val)
1497{
1498 p->supported_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;
1499}
1500
1501static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_selected_func(const struct ena_admin_feature_rss_flow_hash_function *p)
1502{
1503 return p->selected_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;
1504}
1505
1506static inline void set_ena_admin_feature_rss_flow_hash_function_selected_func(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val)
1507{
1508 p->selected_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;
1509}
1510
1511static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1512{
1513 return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT;
1514}
1515
1516static inline void set_ena_admin_feature_rss_flow_hash_input_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1517{
1518 p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK;
1519}
1520
1521static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1522{
1523 return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT;
1524}
1525
1526static inline void set_ena_admin_feature_rss_flow_hash_input_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1527{
1528 p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
1529}
1530
1531static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1532{
1533 return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT;
1534}
1535
1536static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1537{
1538 p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK;
1539}
1540
1541static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1542{
1543 return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT;
1544}
1545
1546static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1547{
1548 p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK;
1549}
1550
1551static inline uint32_t get_ena_admin_host_info_major(const struct ena_admin_host_info *p)
1552{
1553 return p->driver_version & ENA_ADMIN_HOST_INFO_MAJOR_MASK;
1554}
1555
1556static inline void set_ena_admin_host_info_major(struct ena_admin_host_info *p, uint32_t val)
1557{
1558 p->driver_version |= val & ENA_ADMIN_HOST_INFO_MAJOR_MASK;
1559}
1560
1561static inline uint32_t get_ena_admin_host_info_minor(const struct ena_admin_host_info *p)
1562{
1563 return (p->driver_version & ENA_ADMIN_HOST_INFO_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_MINOR_SHIFT;
1564}
1565
1566static inline void set_ena_admin_host_info_minor(struct ena_admin_host_info *p, uint32_t val)
1567{
1568 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_MINOR_MASK;
1569}
1570
1571static inline uint32_t get_ena_admin_host_info_sub_minor(const struct ena_admin_host_info *p)
1572{
1573 return (p->driver_version & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT;
1574}
1575
1576static inline void set_ena_admin_host_info_sub_minor(struct ena_admin_host_info *p, uint32_t val)
1577{
1578 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK;
1579}
1580
1581static inline uint32_t get_ena_admin_host_info_module_type(const struct ena_admin_host_info *p)
1582{
1583 return (p->driver_version & ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK) >> ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT;
1584}
1585
1586static inline void set_ena_admin_host_info_module_type(struct ena_admin_host_info *p, uint32_t val)
1587{
1588 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT) & ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK;
1589}
1590
1591static inline uint16_t get_ena_admin_host_info_function(const struct ena_admin_host_info *p)
1592{
1593 return p->bdf & ENA_ADMIN_HOST_INFO_FUNCTION_MASK;
1594}
1595
1596static inline void set_ena_admin_host_info_function(struct ena_admin_host_info *p, uint16_t val)
1597{
1598 p->bdf |= val & ENA_ADMIN_HOST_INFO_FUNCTION_MASK;
1599}
1600
1601static inline uint16_t get_ena_admin_host_info_device(const struct ena_admin_host_info *p)
1602{
1603 return (p->bdf & ENA_ADMIN_HOST_INFO_DEVICE_MASK) >> ENA_ADMIN_HOST_INFO_DEVICE_SHIFT;
1604}
1605
1606static inline void set_ena_admin_host_info_device(struct ena_admin_host_info *p, uint16_t val)
1607{
1608 p->bdf |= (val << ENA_ADMIN_HOST_INFO_DEVICE_SHIFT) & ENA_ADMIN_HOST_INFO_DEVICE_MASK;
1609}
1610
1611static inline uint16_t get_ena_admin_host_info_bus(const struct ena_admin_host_info *p)
1612{
1613 return (p->bdf & ENA_ADMIN_HOST_INFO_BUS_MASK) >> ENA_ADMIN_HOST_INFO_BUS_SHIFT;
1614}
1615
1616static inline void set_ena_admin_host_info_bus(struct ena_admin_host_info *p, uint16_t val)
1617{
1618 p->bdf |= (val << ENA_ADMIN_HOST_INFO_BUS_SHIFT) & ENA_ADMIN_HOST_INFO_BUS_MASK;
1619}
1620
1621static inline uint32_t get_ena_admin_host_info_rx_offset(const struct ena_admin_host_info *p)
1622{
1623 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK) >> ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT;
1624}
1625
1626static inline void set_ena_admin_host_info_rx_offset(struct ena_admin_host_info *p, uint32_t val)
1627{
1628 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT) & ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK;
1629}
1630
1631static inline uint32_t get_ena_admin_host_info_interrupt_moderation(const struct ena_admin_host_info *p)
1632{
1633 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK) >> ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT;
1634}
1635
1636static inline void set_ena_admin_host_info_interrupt_moderation(struct ena_admin_host_info *p, uint32_t val)
1637{
1638 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT) & ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK;
1639}
1640
1641static inline uint32_t get_ena_admin_host_info_rx_buf_mirroring(const struct ena_admin_host_info *p)
1642{
1643 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK) >> ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT;
1644}
1645
1646static inline void set_ena_admin_host_info_rx_buf_mirroring(struct ena_admin_host_info *p, uint32_t val)
1647{
1648 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT) & ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK;
1649}
1650
1651static inline uint32_t get_ena_admin_host_info_rss_configurable_function_key(const struct ena_admin_host_info *p)
1652{
1653 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK) >> ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT;
1654}
1655
1656static inline void set_ena_admin_host_info_rss_configurable_function_key(struct ena_admin_host_info *p, uint32_t val)
1657{
1658 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT) & ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK;
1659}
1660
1661static inline uint8_t get_ena_admin_feature_rss_ind_table_one_entry_update(const struct ena_admin_feature_rss_ind_table *p)
1662{
1663 return p->flags & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK;
1664}
1665
1666static inline void set_ena_admin_feature_rss_ind_table_one_entry_update(struct ena_admin_feature_rss_ind_table *p, uint8_t val)
1667{
1668 p->flags |= val & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK;
1669}
1670
1671static inline uint8_t get_ena_admin_aenq_common_desc_phase(const struct ena_admin_aenq_common_desc *p)
1672{
1673 return p->flags & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK;
1674}
1675
1676static inline void set_ena_admin_aenq_common_desc_phase(struct ena_admin_aenq_common_desc *p, uint8_t val)
1677{
1678 p->flags |= val & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK;
1679}
1680
1681static inline uint32_t get_ena_admin_aenq_link_change_desc_link_status(const struct ena_admin_aenq_link_change_desc *p)
1682{
1683 return p->flags & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
1684}
1685
1686static inline void set_ena_admin_aenq_link_change_desc_link_status(struct ena_admin_aenq_link_change_desc *p, uint32_t val)
1687{
1688 p->flags |= val & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
1689}
1690
1691#endif
1692#endif
1693