LXR dpdk/drivers/raw/ifpga/afu_pmd_he

   1/* SPDX-License-Identifier: BSD-3-Clause
   2 * Copyright(c) 2022 Intel Corporation
   3 */
   4
   5#ifndef AFU_PMD_HE_LPBK_H
   6#define AFU_PMD_HE_LPBK_H
   7
   8#ifdef __cplusplus
   9extern "C" {
  10#endif
  11
  12#include "afu_pmd_core.h"
  13#include "rte_pmd_afu.h"
  14
  15#define HE_LPBK_UUID_L     0xb94b12284c31e02b
  16#define HE_LPBK_UUID_H     0x56e203e9864f49a7
  17#define HE_MEM_LPBK_UUID_L 0xbb652a578330a8eb
  18#define HE_MEM_LPBK_UUID_H 0x8568ab4e6ba54616
  19
  20/* HE-LBK & HE-MEM-LBK registers definition */
  21#define CSR_SCRATCHPAD0    0x100
  22#define CSR_SCRATCHPAD1    0x108
  23#define CSR_AFU_DSM_BASEL  0x110
  24#define CSR_AFU_DSM_BASEH  0x114
  25#define CSR_SRC_ADDR       0x120
  26#define CSR_DST_ADDR       0x128
  27#define CSR_NUM_LINES      0x130
  28#define CSR_CTL            0x138
  29#define CSR_CFG            0x140
  30#define CSR_INACT_THRESH   0x148
  31#define CSR_INTERRUPT0     0x150
  32#define CSR_SWTEST_MSG     0x158
  33#define CSR_STATUS0        0x160
  34#define CSR_STATUS1        0x168
  35#define CSR_ERROR          0x170
  36#define CSR_STRIDE         0x178
  37#define CSR_HE_INFO0       0x180
  38
  39#define DSM_SIZE           0x200000
  40#define DSM_POLL_INTERVAL  5  /* ms */
  41#define DSM_TIMEOUT        1000  /* ms */
  42
  43#define NLB_BUF_SIZE  0x400000
  44#define TEST_MEM_ALIGN  1024
  45
  46struct he_lpbk_csr_ctl {
  47        union {
  48                uint32_t csr;
  49                struct {
  50                        uint32_t reset:1;
  51                        uint32_t start:1;
  52                        uint32_t force_completion:1;
  53                        uint32_t reserved:29;
  54                };
  55        };
  56};
  57
  58struct he_lpbk_csr_cfg {
  59        union {
  60                uint32_t csr;
  61                struct {
  62                        uint32_t rsvd1:1;
  63                        uint32_t cont:1;
  64                        uint32_t mode:3;
  65                        uint32_t multicl_len:2;
  66                        uint32_t rsvd2:13;
  67                        uint32_t trput_interleave:3;
  68                        uint32_t test_cfg:5;
  69                        uint32_t interrupt_on_error:1;
  70                        uint32_t interrupt_testmode:1;
  71                        uint32_t rsvd3:2;
  72                };
  73        };
  74};
  75
  76struct he_lpbk_status0 {
  77        union {
  78                uint64_t csr;
  79                struct {
  80                        uint32_t num_writes;
  81                        uint32_t num_reads;
  82                };
  83        };
  84};
  85
  86struct he_lpbk_status1 {
  87        union {
  88                uint64_t csr;
  89                struct {
  90                        uint32_t num_pend_writes;
  91                        uint32_t num_pend_reads;
  92                };
  93        };
  94};
  95
  96struct he_lpbk_dsm_status {
  97        uint32_t test_complete;
  98        uint32_t test_error;
  99        uint64_t num_clocks;
 100        uint32_t num_reads;
 101        uint32_t num_writes;
 102        uint32_t start_overhead;
 103        uint32_t end_overhead;
 104};
 105
 106struct he_lpbk_ctx {
 107        uint8_t *addr;
 108        uint8_t *dsm_ptr;
 109        uint64_t dsm_iova;
 110        uint8_t *src_ptr;
 111        uint64_t src_iova;
 112        uint8_t *dest_ptr;
 113        uint64_t dest_iova;
 114        struct he_lpbk_dsm_status *status_ptr;
 115};
 116
 117struct he_lpbk_priv {
 118        struct rte_pmd_afu_he_lpbk_cfg he_lpbk_cfg;
 119        struct he_lpbk_ctx he_lpbk_ctx;
 120};
 121
 122#ifdef __cplusplus
 123}
 124#endif
 125
 126#endif /* AFU_PMD_HE_LPBK_H */
 127