1
2#ifndef __LINUX_PKT_SCHED_H
3#define __LINUX_PKT_SCHED_H
4
5#include <linux/const.h>
6#include <linux/types.h>
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21#define TC_PRIO_BESTEFFORT 0
22#define TC_PRIO_FILLER 1
23#define TC_PRIO_BULK 2
24#define TC_PRIO_INTERACTIVE_BULK 4
25#define TC_PRIO_INTERACTIVE 6
26#define TC_PRIO_CONTROL 7
27
28#define TC_PRIO_MAX 15
29
30
31
32
33
34struct tc_stats {
35 __u64 bytes;
36 __u32 packets;
37 __u32 drops;
38 __u32 overlimits;
39
40 __u32 bps;
41 __u32 pps;
42 __u32 qlen;
43 __u32 backlog;
44};
45
46struct tc_estimator {
47 signed char interval;
48 unsigned char ewma_log;
49};
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68#define TC_H_MAJ_MASK (0xFFFF0000U)
69#define TC_H_MIN_MASK (0x0000FFFFU)
70#define TC_H_MAJ(h) ((h)&TC_H_MAJ_MASK)
71#define TC_H_MIN(h) ((h)&TC_H_MIN_MASK)
72#define TC_H_MAKE(maj,min) (((maj)&TC_H_MAJ_MASK)|((min)&TC_H_MIN_MASK))
73
74#define TC_H_UNSPEC (0U)
75#define TC_H_ROOT (0xFFFFFFFFU)
76#define TC_H_INGRESS (0xFFFFFFF1U)
77#define TC_H_CLSACT TC_H_INGRESS
78
79#define TC_H_MIN_PRIORITY 0xFFE0U
80#define TC_H_MIN_INGRESS 0xFFF2U
81#define TC_H_MIN_EGRESS 0xFFF3U
82
83
84enum tc_link_layer {
85 TC_LINKLAYER_UNAWARE,
86 TC_LINKLAYER_ETHERNET,
87 TC_LINKLAYER_ATM,
88};
89#define TC_LINKLAYER_MASK 0x0F
90
91struct tc_ratespec {
92 unsigned char cell_log;
93 __u8 linklayer;
94 unsigned short overhead;
95 short cell_align;
96 unsigned short mpu;
97 __u32 rate;
98};
99
100#define TC_RTAB_SIZE 1024
101
102struct tc_sizespec {
103 unsigned char cell_log;
104 unsigned char size_log;
105 short cell_align;
106 int overhead;
107 unsigned int linklayer;
108 unsigned int mpu;
109 unsigned int mtu;
110 unsigned int tsize;
111};
112
113enum {
114 TCA_STAB_UNSPEC,
115 TCA_STAB_BASE,
116 TCA_STAB_DATA,
117 __TCA_STAB_MAX
118};
119
120#define TCA_STAB_MAX (__TCA_STAB_MAX - 1)
121
122
123
124struct tc_fifo_qopt {
125 __u32 limit;
126};
127
128
129
130
131
132
133
134
135
136
137#define SKBPRIO_MAX_PRIORITY 64
138
139struct tc_skbprio_qopt {
140 __u32 limit;
141};
142
143
144
145#define TCQ_PRIO_BANDS 16
146#define TCQ_MIN_PRIO_BANDS 2
147
148struct tc_prio_qopt {
149 int bands;
150 __u8 priomap[TC_PRIO_MAX+1];
151};
152
153
154
155struct tc_multiq_qopt {
156 __u16 bands;
157 __u16 max_bands;
158};
159
160
161
162#define TCQ_PLUG_BUFFER 0
163#define TCQ_PLUG_RELEASE_ONE 1
164#define TCQ_PLUG_RELEASE_INDEFINITE 2
165#define TCQ_PLUG_LIMIT 3
166
167struct tc_plug_qopt {
168
169
170
171
172
173
174
175
176
177 int action;
178 __u32 limit;
179};
180
181
182
183struct tc_tbf_qopt {
184 struct tc_ratespec rate;
185 struct tc_ratespec peakrate;
186 __u32 limit;
187 __u32 buffer;
188 __u32 mtu;
189};
190
191enum {
192 TCA_TBF_UNSPEC,
193 TCA_TBF_PARMS,
194 TCA_TBF_RTAB,
195 TCA_TBF_PTAB,
196 TCA_TBF_RATE64,
197 TCA_TBF_PRATE64,
198 TCA_TBF_BURST,
199 TCA_TBF_PBURST,
200 TCA_TBF_PAD,
201 __TCA_TBF_MAX,
202};
203
204#define TCA_TBF_MAX (__TCA_TBF_MAX - 1)
205
206
207
208
209
210
211
212
213struct tc_sfq_qopt {
214 unsigned quantum;
215 int perturb_period;
216 __u32 limit;
217 unsigned divisor;
218 unsigned flows;
219};
220
221struct tc_sfqred_stats {
222 __u32 prob_drop;
223 __u32 forced_drop;
224 __u32 prob_mark;
225 __u32 forced_mark;
226 __u32 prob_mark_head;
227 __u32 forced_mark_head;
228};
229
230struct tc_sfq_qopt_v1 {
231 struct tc_sfq_qopt v0;
232 unsigned int depth;
233 unsigned int headdrop;
234
235 __u32 limit;
236 __u32 qth_min;
237 __u32 qth_max;
238 unsigned char Wlog;
239 unsigned char Plog;
240 unsigned char Scell_log;
241 unsigned char flags;
242 __u32 max_P;
243
244 struct tc_sfqred_stats stats;
245};
246
247
248struct tc_sfq_xstats {
249 __s32 allot;
250};
251
252
253
254enum {
255 TCA_RED_UNSPEC,
256 TCA_RED_PARMS,
257 TCA_RED_STAB,
258 TCA_RED_MAX_P,
259 TCA_RED_FLAGS,
260 TCA_RED_EARLY_DROP_BLOCK,
261 TCA_RED_MARK_BLOCK,
262 __TCA_RED_MAX,
263};
264
265#define TCA_RED_MAX (__TCA_RED_MAX - 1)
266
267struct tc_red_qopt {
268 __u32 limit;
269 __u32 qth_min;
270 __u32 qth_max;
271 unsigned char Wlog;
272 unsigned char Plog;
273 unsigned char Scell_log;
274
275
276
277
278
279
280
281
282
283
284
285
286
287 unsigned char flags;
288#define TC_RED_ECN 1
289#define TC_RED_HARDDROP 2
290#define TC_RED_ADAPTATIVE 4
291#define TC_RED_NODROP 8
292};
293
294#define TC_RED_HISTORIC_FLAGS (TC_RED_ECN | TC_RED_HARDDROP | TC_RED_ADAPTATIVE)
295
296struct tc_red_xstats {
297 __u32 early;
298 __u32 pdrop;
299 __u32 other;
300 __u32 marked;
301};
302
303
304
305#define MAX_DPs 16
306
307enum {
308 TCA_GRED_UNSPEC,
309 TCA_GRED_PARMS,
310 TCA_GRED_STAB,
311 TCA_GRED_DPS,
312 TCA_GRED_MAX_P,
313 TCA_GRED_LIMIT,
314 TCA_GRED_VQ_LIST,
315 __TCA_GRED_MAX,
316};
317
318#define TCA_GRED_MAX (__TCA_GRED_MAX - 1)
319
320enum {
321 TCA_GRED_VQ_ENTRY_UNSPEC,
322 TCA_GRED_VQ_ENTRY,
323 __TCA_GRED_VQ_ENTRY_MAX,
324};
325#define TCA_GRED_VQ_ENTRY_MAX (__TCA_GRED_VQ_ENTRY_MAX - 1)
326
327enum {
328 TCA_GRED_VQ_UNSPEC,
329 TCA_GRED_VQ_PAD,
330 TCA_GRED_VQ_DP,
331 TCA_GRED_VQ_STAT_BYTES,
332 TCA_GRED_VQ_STAT_PACKETS,
333 TCA_GRED_VQ_STAT_BACKLOG,
334 TCA_GRED_VQ_STAT_PROB_DROP,
335 TCA_GRED_VQ_STAT_PROB_MARK,
336 TCA_GRED_VQ_STAT_FORCED_DROP,
337 TCA_GRED_VQ_STAT_FORCED_MARK,
338 TCA_GRED_VQ_STAT_PDROP,
339 TCA_GRED_VQ_STAT_OTHER,
340 TCA_GRED_VQ_FLAGS,
341 __TCA_GRED_VQ_MAX
342};
343
344#define TCA_GRED_VQ_MAX (__TCA_GRED_VQ_MAX - 1)
345
346struct tc_gred_qopt {
347 __u32 limit;
348 __u32 qth_min;
349 __u32 qth_max;
350 __u32 DP;
351 __u32 backlog;
352 __u32 qave;
353 __u32 forced;
354 __u32 early;
355 __u32 other;
356 __u32 pdrop;
357 __u8 Wlog;
358 __u8 Plog;
359 __u8 Scell_log;
360 __u8 prio;
361 __u32 packets;
362 __u32 bytesin;
363};
364
365
366struct tc_gred_sopt {
367 __u32 DPs;
368 __u32 def_DP;
369 __u8 grio;
370 __u8 flags;
371 __u16 pad1;
372};
373
374
375
376enum {
377 TCA_CHOKE_UNSPEC,
378 TCA_CHOKE_PARMS,
379 TCA_CHOKE_STAB,
380 TCA_CHOKE_MAX_P,
381 __TCA_CHOKE_MAX,
382};
383
384#define TCA_CHOKE_MAX (__TCA_CHOKE_MAX - 1)
385
386struct tc_choke_qopt {
387 __u32 limit;
388 __u32 qth_min;
389 __u32 qth_max;
390 unsigned char Wlog;
391 unsigned char Plog;
392 unsigned char Scell_log;
393 unsigned char flags;
394};
395
396struct tc_choke_xstats {
397 __u32 early;
398 __u32 pdrop;
399 __u32 other;
400 __u32 marked;
401 __u32 matched;
402};
403
404
405#define TC_HTB_NUMPRIO 8
406#define TC_HTB_MAXDEPTH 8
407#define TC_HTB_PROTOVER 3
408
409struct tc_htb_opt {
410 struct tc_ratespec rate;
411 struct tc_ratespec ceil;
412 __u32 buffer;
413 __u32 cbuffer;
414 __u32 quantum;
415 __u32 level;
416 __u32 prio;
417};
418struct tc_htb_glob {
419 __u32 version;
420 __u32 rate2quantum;
421 __u32 defcls;
422 __u32 debug;
423
424
425 __u32 direct_pkts;
426};
427enum {
428 TCA_HTB_UNSPEC,
429 TCA_HTB_PARMS,
430 TCA_HTB_INIT,
431 TCA_HTB_CTAB,
432 TCA_HTB_RTAB,
433 TCA_HTB_DIRECT_QLEN,
434 TCA_HTB_RATE64,
435 TCA_HTB_CEIL64,
436 TCA_HTB_PAD,
437 TCA_HTB_OFFLOAD,
438 __TCA_HTB_MAX,
439};
440
441#define TCA_HTB_MAX (__TCA_HTB_MAX - 1)
442
443struct tc_htb_xstats {
444 __u32 lends;
445 __u32 borrows;
446 __u32 giants;
447 __s32 tokens;
448 __s32 ctokens;
449};
450
451
452
453struct tc_hfsc_qopt {
454 __u16 defcls;
455};
456
457struct tc_service_curve {
458 __u32 m1;
459 __u32 d;
460 __u32 m2;
461};
462
463struct tc_hfsc_stats {
464 __u64 work;
465 __u64 rtwork;
466 __u32 period;
467 __u32 level;
468};
469
470enum {
471 TCA_HFSC_UNSPEC,
472 TCA_HFSC_RSC,
473 TCA_HFSC_FSC,
474 TCA_HFSC_USC,
475 __TCA_HFSC_MAX,
476};
477
478#define TCA_HFSC_MAX (__TCA_HFSC_MAX - 1)
479
480
481
482enum {
483 TCA_NETEM_UNSPEC,
484 TCA_NETEM_CORR,
485 TCA_NETEM_DELAY_DIST,
486 TCA_NETEM_REORDER,
487 TCA_NETEM_CORRUPT,
488 TCA_NETEM_LOSS,
489 TCA_NETEM_RATE,
490 TCA_NETEM_ECN,
491 TCA_NETEM_RATE64,
492 TCA_NETEM_PAD,
493 TCA_NETEM_LATENCY64,
494 TCA_NETEM_JITTER64,
495 TCA_NETEM_SLOT,
496 TCA_NETEM_SLOT_DIST,
497 TCA_NETEM_PRNG_SEED,
498 __TCA_NETEM_MAX,
499};
500
501#define TCA_NETEM_MAX (__TCA_NETEM_MAX - 1)
502
503struct tc_netem_qopt {
504 __u32 latency;
505 __u32 limit;
506 __u32 loss;
507 __u32 gap;
508 __u32 duplicate;
509 __u32 jitter;
510};
511
512struct tc_netem_corr {
513 __u32 delay_corr;
514 __u32 loss_corr;
515 __u32 dup_corr;
516};
517
518struct tc_netem_reorder {
519 __u32 probability;
520 __u32 correlation;
521};
522
523struct tc_netem_corrupt {
524 __u32 probability;
525 __u32 correlation;
526};
527
528struct tc_netem_rate {
529 __u32 rate;
530 __s32 packet_overhead;
531 __u32 cell_size;
532 __s32 cell_overhead;
533};
534
535struct tc_netem_slot {
536 __s64 min_delay;
537 __s64 max_delay;
538 __s32 max_packets;
539 __s32 max_bytes;
540 __s64 dist_delay;
541 __s64 dist_jitter;
542};
543
544enum {
545 NETEM_LOSS_UNSPEC,
546 NETEM_LOSS_GI,
547 NETEM_LOSS_GE,
548 __NETEM_LOSS_MAX
549};
550#define NETEM_LOSS_MAX (__NETEM_LOSS_MAX - 1)
551
552
553struct tc_netem_gimodel {
554 __u32 p13;
555 __u32 p31;
556 __u32 p32;
557 __u32 p14;
558 __u32 p23;
559};
560
561
562struct tc_netem_gemodel {
563 __u32 p;
564 __u32 r;
565 __u32 h;
566 __u32 k1;
567};
568
569#define NETEM_DIST_SCALE 8192
570#define NETEM_DIST_MAX 16384
571
572
573
574enum {
575 TCA_DRR_UNSPEC,
576 TCA_DRR_QUANTUM,
577 __TCA_DRR_MAX
578};
579
580#define TCA_DRR_MAX (__TCA_DRR_MAX - 1)
581
582struct tc_drr_stats {
583 __u32 deficit;
584};
585
586
587#define TC_QOPT_BITMASK 15
588#define TC_QOPT_MAX_QUEUE 16
589
590enum {
591 TC_MQPRIO_HW_OFFLOAD_NONE,
592 TC_MQPRIO_HW_OFFLOAD_TCS,
593 __TC_MQPRIO_HW_OFFLOAD_MAX
594};
595
596#define TC_MQPRIO_HW_OFFLOAD_MAX (__TC_MQPRIO_HW_OFFLOAD_MAX - 1)
597
598enum {
599 TC_MQPRIO_MODE_DCB,
600 TC_MQPRIO_MODE_CHANNEL,
601 __TC_MQPRIO_MODE_MAX
602};
603
604#define __TC_MQPRIO_MODE_MAX (__TC_MQPRIO_MODE_MAX - 1)
605
606enum {
607 TC_MQPRIO_SHAPER_DCB,
608 TC_MQPRIO_SHAPER_BW_RATE,
609 __TC_MQPRIO_SHAPER_MAX
610};
611
612#define __TC_MQPRIO_SHAPER_MAX (__TC_MQPRIO_SHAPER_MAX - 1)
613
614enum {
615 TC_FP_EXPRESS = 1,
616 TC_FP_PREEMPTIBLE = 2,
617};
618
619struct tc_mqprio_qopt {
620 __u8 num_tc;
621 __u8 prio_tc_map[TC_QOPT_BITMASK + 1];
622 __u8 hw;
623 __u16 count[TC_QOPT_MAX_QUEUE];
624 __u16 offset[TC_QOPT_MAX_QUEUE];
625};
626
627#define TC_MQPRIO_F_MODE 0x1
628#define TC_MQPRIO_F_SHAPER 0x2
629#define TC_MQPRIO_F_MIN_RATE 0x4
630#define TC_MQPRIO_F_MAX_RATE 0x8
631
632enum {
633 TCA_MQPRIO_TC_ENTRY_UNSPEC,
634 TCA_MQPRIO_TC_ENTRY_INDEX,
635 TCA_MQPRIO_TC_ENTRY_FP,
636
637
638 __TCA_MQPRIO_TC_ENTRY_CNT,
639 TCA_MQPRIO_TC_ENTRY_MAX = (__TCA_MQPRIO_TC_ENTRY_CNT - 1)
640};
641
642enum {
643 TCA_MQPRIO_UNSPEC,
644 TCA_MQPRIO_MODE,
645 TCA_MQPRIO_SHAPER,
646 TCA_MQPRIO_MIN_RATE64,
647 TCA_MQPRIO_MAX_RATE64,
648 TCA_MQPRIO_TC_ENTRY,
649 __TCA_MQPRIO_MAX,
650};
651
652#define TCA_MQPRIO_MAX (__TCA_MQPRIO_MAX - 1)
653
654
655
656enum {
657 TCA_SFB_UNSPEC,
658 TCA_SFB_PARMS,
659 __TCA_SFB_MAX,
660};
661
662#define TCA_SFB_MAX (__TCA_SFB_MAX - 1)
663
664
665
666
667struct tc_sfb_qopt {
668 __u32 rehash_interval;
669 __u32 warmup_time;
670 __u32 max;
671 __u32 bin_size;
672 __u32 increment;
673 __u32 decrement;
674 __u32 limit;
675 __u32 penalty_rate;
676 __u32 penalty_burst;
677};
678
679struct tc_sfb_xstats {
680 __u32 earlydrop;
681 __u32 penaltydrop;
682 __u32 bucketdrop;
683 __u32 queuedrop;
684 __u32 childdrop;
685 __u32 marked;
686 __u32 maxqlen;
687 __u32 maxprob;
688 __u32 avgprob;
689};
690
691#define SFB_MAX_PROB 0xFFFF
692
693
694enum {
695 TCA_QFQ_UNSPEC,
696 TCA_QFQ_WEIGHT,
697 TCA_QFQ_LMAX,
698 __TCA_QFQ_MAX
699};
700
701#define TCA_QFQ_MAX (__TCA_QFQ_MAX - 1)
702
703struct tc_qfq_stats {
704 __u32 weight;
705 __u32 lmax;
706};
707
708
709
710enum {
711 TCA_CODEL_UNSPEC,
712 TCA_CODEL_TARGET,
713 TCA_CODEL_LIMIT,
714 TCA_CODEL_INTERVAL,
715 TCA_CODEL_ECN,
716 TCA_CODEL_CE_THRESHOLD,
717 __TCA_CODEL_MAX
718};
719
720#define TCA_CODEL_MAX (__TCA_CODEL_MAX - 1)
721
722struct tc_codel_xstats {
723 __u32 maxpacket;
724 __u32 count;
725
726
727 __u32 lastcount;
728 __u32 ldelay;
729 __s32 drop_next;
730 __u32 drop_overlimit;
731 __u32 ecn_mark;
732 __u32 dropping;
733 __u32 ce_mark;
734};
735
736
737
738#define FQ_CODEL_QUANTUM_MAX (1 << 20)
739
740enum {
741 TCA_FQ_CODEL_UNSPEC,
742 TCA_FQ_CODEL_TARGET,
743 TCA_FQ_CODEL_LIMIT,
744 TCA_FQ_CODEL_INTERVAL,
745 TCA_FQ_CODEL_ECN,
746 TCA_FQ_CODEL_FLOWS,
747 TCA_FQ_CODEL_QUANTUM,
748 TCA_FQ_CODEL_CE_THRESHOLD,
749 TCA_FQ_CODEL_DROP_BATCH_SIZE,
750 TCA_FQ_CODEL_MEMORY_LIMIT,
751 TCA_FQ_CODEL_CE_THRESHOLD_SELECTOR,
752 TCA_FQ_CODEL_CE_THRESHOLD_MASK,
753 __TCA_FQ_CODEL_MAX
754};
755
756#define TCA_FQ_CODEL_MAX (__TCA_FQ_CODEL_MAX - 1)
757
758enum {
759 TCA_FQ_CODEL_XSTATS_QDISC,
760 TCA_FQ_CODEL_XSTATS_CLASS,
761};
762
763struct tc_fq_codel_qd_stats {
764 __u32 maxpacket;
765 __u32 drop_overlimit;
766
767
768 __u32 ecn_mark;
769
770
771 __u32 new_flow_count;
772
773
774 __u32 new_flows_len;
775 __u32 old_flows_len;
776 __u32 ce_mark;
777 __u32 memory_usage;
778 __u32 drop_overmemory;
779};
780
781struct tc_fq_codel_cl_stats {
782 __s32 deficit;
783 __u32 ldelay;
784
785
786 __u32 count;
787 __u32 lastcount;
788 __u32 dropping;
789 __s32 drop_next;
790};
791
792struct tc_fq_codel_xstats {
793 __u32 type;
794 union {
795 struct tc_fq_codel_qd_stats qdisc_stats;
796 struct tc_fq_codel_cl_stats class_stats;
797 };
798};
799
800
801
802enum {
803 TCA_FQ_UNSPEC,
804
805 TCA_FQ_PLIMIT,
806
807 TCA_FQ_FLOW_PLIMIT,
808
809 TCA_FQ_QUANTUM,
810
811 TCA_FQ_INITIAL_QUANTUM,
812
813 TCA_FQ_RATE_ENABLE,
814
815 TCA_FQ_FLOW_DEFAULT_RATE,
816
817 TCA_FQ_FLOW_MAX_RATE,
818
819 TCA_FQ_BUCKETS_LOG,
820
821 TCA_FQ_FLOW_REFILL_DELAY,
822
823 TCA_FQ_ORPHAN_MASK,
824
825 TCA_FQ_LOW_RATE_THRESHOLD,
826
827 TCA_FQ_CE_THRESHOLD,
828
829 TCA_FQ_TIMER_SLACK,
830
831 TCA_FQ_HORIZON,
832
833 TCA_FQ_HORIZON_DROP,
834
835 TCA_FQ_PRIOMAP,
836
837 TCA_FQ_WEIGHTS,
838
839 TCA_FQ_OFFLOAD_HORIZON,
840
841 __TCA_FQ_MAX
842};
843
844#define TCA_FQ_MAX (__TCA_FQ_MAX - 1)
845
846#define FQ_BANDS 3
847#define FQ_MIN_WEIGHT 16384
848
849struct tc_fq_qd_stats {
850 __u64 gc_flows;
851 __u64 highprio_packets;
852 __u64 tcp_retrans;
853 __u64 throttled;
854 __u64 flows_plimit;
855 __u64 pkts_too_long;
856 __u64 allocation_errors;
857 __s64 time_next_delayed_flow;
858 __u32 flows;
859 __u32 inactive_flows;
860 __u32 throttled_flows;
861 __u32 unthrottle_latency_ns;
862 __u64 ce_mark;
863 __u64 horizon_drops;
864 __u64 horizon_caps;
865 __u64 fastpath_packets;
866 __u64 band_drops[FQ_BANDS];
867 __u32 band_pkt_count[FQ_BANDS];
868 __u32 pad;
869};
870
871
872
873enum {
874 TCA_HHF_UNSPEC,
875 TCA_HHF_BACKLOG_LIMIT,
876 TCA_HHF_QUANTUM,
877 TCA_HHF_HH_FLOWS_LIMIT,
878 TCA_HHF_RESET_TIMEOUT,
879 TCA_HHF_ADMIT_BYTES,
880 TCA_HHF_EVICT_TIMEOUT,
881 TCA_HHF_NON_HH_WEIGHT,
882 __TCA_HHF_MAX
883};
884
885#define TCA_HHF_MAX (__TCA_HHF_MAX - 1)
886
887struct tc_hhf_xstats {
888 __u32 drop_overlimit;
889
890
891 __u32 hh_overlimit;
892 __u32 hh_tot_count;
893 __u32 hh_cur_count;
894};
895
896
897enum {
898 TCA_PIE_UNSPEC,
899 TCA_PIE_TARGET,
900 TCA_PIE_LIMIT,
901 TCA_PIE_TUPDATE,
902 TCA_PIE_ALPHA,
903 TCA_PIE_BETA,
904 TCA_PIE_ECN,
905 TCA_PIE_BYTEMODE,
906 TCA_PIE_DQ_RATE_ESTIMATOR,
907 __TCA_PIE_MAX
908};
909#define TCA_PIE_MAX (__TCA_PIE_MAX - 1)
910
911struct tc_pie_xstats {
912 __u64 prob;
913 __u32 delay;
914 __u32 avg_dq_rate;
915
916
917 __u32 dq_rate_estimating;
918 __u32 packets_in;
919 __u32 dropped;
920 __u32 overlimit;
921
922
923 __u32 maxq;
924 __u32 ecn_mark;
925};
926
927
928enum {
929 TCA_FQ_PIE_UNSPEC,
930 TCA_FQ_PIE_LIMIT,
931 TCA_FQ_PIE_FLOWS,
932 TCA_FQ_PIE_TARGET,
933 TCA_FQ_PIE_TUPDATE,
934 TCA_FQ_PIE_ALPHA,
935 TCA_FQ_PIE_BETA,
936 TCA_FQ_PIE_QUANTUM,
937 TCA_FQ_PIE_MEMORY_LIMIT,
938 TCA_FQ_PIE_ECN_PROB,
939 TCA_FQ_PIE_ECN,
940 TCA_FQ_PIE_BYTEMODE,
941 TCA_FQ_PIE_DQ_RATE_ESTIMATOR,
942 __TCA_FQ_PIE_MAX
943};
944#define TCA_FQ_PIE_MAX (__TCA_FQ_PIE_MAX - 1)
945
946struct tc_fq_pie_xstats {
947 __u32 packets_in;
948 __u32 dropped;
949 __u32 overlimit;
950 __u32 overmemory;
951 __u32 ecn_mark;
952 __u32 new_flow_count;
953 __u32 new_flows_len;
954 __u32 old_flows_len;
955 __u32 memory_usage;
956};
957
958
959struct tc_cbs_qopt {
960 __u8 offload;
961 __u8 _pad[3];
962 __s32 hicredit;
963 __s32 locredit;
964 __s32 idleslope;
965 __s32 sendslope;
966};
967
968enum {
969 TCA_CBS_UNSPEC,
970 TCA_CBS_PARMS,
971 __TCA_CBS_MAX,
972};
973
974#define TCA_CBS_MAX (__TCA_CBS_MAX - 1)
975
976
977
978struct tc_etf_qopt {
979 __s32 delta;
980 __s32 clockid;
981 __u32 flags;
982#define TC_ETF_DEADLINE_MODE_ON _BITUL(0)
983#define TC_ETF_OFFLOAD_ON _BITUL(1)
984#define TC_ETF_SKIP_SOCK_CHECK _BITUL(2)
985};
986
987enum {
988 TCA_ETF_UNSPEC,
989 TCA_ETF_PARMS,
990 __TCA_ETF_MAX,
991};
992
993#define TCA_ETF_MAX (__TCA_ETF_MAX - 1)
994
995
996
997enum {
998 TCA_CAKE_UNSPEC,
999 TCA_CAKE_PAD,
1000 TCA_CAKE_BASE_RATE64,
1001 TCA_CAKE_DIFFSERV_MODE,
1002 TCA_CAKE_ATM,
1003 TCA_CAKE_FLOW_MODE,
1004 TCA_CAKE_OVERHEAD,
1005 TCA_CAKE_RTT,
1006 TCA_CAKE_TARGET,
1007 TCA_CAKE_AUTORATE,
1008 TCA_CAKE_MEMORY,
1009 TCA_CAKE_NAT,
1010 TCA_CAKE_RAW,
1011 TCA_CAKE_WASH,
1012 TCA_CAKE_MPU,
1013 TCA_CAKE_INGRESS,
1014 TCA_CAKE_ACK_FILTER,
1015 TCA_CAKE_SPLIT_GSO,
1016 TCA_CAKE_FWMARK,
1017 __TCA_CAKE_MAX
1018};
1019#define TCA_CAKE_MAX (__TCA_CAKE_MAX - 1)
1020
1021enum {
1022 __TCA_CAKE_STATS_INVALID,
1023 TCA_CAKE_STATS_PAD,
1024 TCA_CAKE_STATS_CAPACITY_ESTIMATE64,
1025 TCA_CAKE_STATS_MEMORY_LIMIT,
1026 TCA_CAKE_STATS_MEMORY_USED,
1027 TCA_CAKE_STATS_AVG_NETOFF,
1028 TCA_CAKE_STATS_MIN_NETLEN,
1029 TCA_CAKE_STATS_MAX_NETLEN,
1030 TCA_CAKE_STATS_MIN_ADJLEN,
1031 TCA_CAKE_STATS_MAX_ADJLEN,
1032 TCA_CAKE_STATS_TIN_STATS,
1033 TCA_CAKE_STATS_DEFICIT,
1034 TCA_CAKE_STATS_COBALT_COUNT,
1035 TCA_CAKE_STATS_DROPPING,
1036 TCA_CAKE_STATS_DROP_NEXT_US,
1037 TCA_CAKE_STATS_P_DROP,
1038 TCA_CAKE_STATS_BLUE_TIMER_US,
1039 __TCA_CAKE_STATS_MAX
1040};
1041#define TCA_CAKE_STATS_MAX (__TCA_CAKE_STATS_MAX - 1)
1042
1043enum {
1044 __TCA_CAKE_TIN_STATS_INVALID,
1045 TCA_CAKE_TIN_STATS_PAD,
1046 TCA_CAKE_TIN_STATS_SENT_PACKETS,
1047 TCA_CAKE_TIN_STATS_SENT_BYTES64,
1048 TCA_CAKE_TIN_STATS_DROPPED_PACKETS,
1049 TCA_CAKE_TIN_STATS_DROPPED_BYTES64,
1050 TCA_CAKE_TIN_STATS_ACKS_DROPPED_PACKETS,
1051 TCA_CAKE_TIN_STATS_ACKS_DROPPED_BYTES64,
1052 TCA_CAKE_TIN_STATS_ECN_MARKED_PACKETS,
1053 TCA_CAKE_TIN_STATS_ECN_MARKED_BYTES64,
1054 TCA_CAKE_TIN_STATS_BACKLOG_PACKETS,
1055 TCA_CAKE_TIN_STATS_BACKLOG_BYTES,
1056 TCA_CAKE_TIN_STATS_THRESHOLD_RATE64,
1057 TCA_CAKE_TIN_STATS_TARGET_US,
1058 TCA_CAKE_TIN_STATS_INTERVAL_US,
1059 TCA_CAKE_TIN_STATS_WAY_INDIRECT_HITS,
1060 TCA_CAKE_TIN_STATS_WAY_MISSES,
1061 TCA_CAKE_TIN_STATS_WAY_COLLISIONS,
1062 TCA_CAKE_TIN_STATS_PEAK_DELAY_US,
1063 TCA_CAKE_TIN_STATS_AVG_DELAY_US,
1064 TCA_CAKE_TIN_STATS_BASE_DELAY_US,
1065 TCA_CAKE_TIN_STATS_SPARSE_FLOWS,
1066 TCA_CAKE_TIN_STATS_BULK_FLOWS,
1067 TCA_CAKE_TIN_STATS_UNRESPONSIVE_FLOWS,
1068 TCA_CAKE_TIN_STATS_MAX_SKBLEN,
1069 TCA_CAKE_TIN_STATS_FLOW_QUANTUM,
1070 __TCA_CAKE_TIN_STATS_MAX
1071};
1072#define TCA_CAKE_TIN_STATS_MAX (__TCA_CAKE_TIN_STATS_MAX - 1)
1073#define TC_CAKE_MAX_TINS (8)
1074
1075enum {
1076 CAKE_FLOW_NONE = 0,
1077 CAKE_FLOW_SRC_IP,
1078 CAKE_FLOW_DST_IP,
1079 CAKE_FLOW_HOSTS,
1080 CAKE_FLOW_FLOWS,
1081 CAKE_FLOW_DUAL_SRC,
1082 CAKE_FLOW_DUAL_DST,
1083 CAKE_FLOW_TRIPLE,
1084 CAKE_FLOW_MAX,
1085};
1086
1087enum {
1088 CAKE_DIFFSERV_DIFFSERV3 = 0,
1089 CAKE_DIFFSERV_DIFFSERV4,
1090 CAKE_DIFFSERV_DIFFSERV8,
1091 CAKE_DIFFSERV_BESTEFFORT,
1092 CAKE_DIFFSERV_PRECEDENCE,
1093 CAKE_DIFFSERV_MAX
1094};
1095
1096enum {
1097 CAKE_ACK_NONE = 0,
1098 CAKE_ACK_FILTER,
1099 CAKE_ACK_AGGRESSIVE,
1100 CAKE_ACK_MAX
1101};
1102
1103enum {
1104 CAKE_ATM_NONE = 0,
1105 CAKE_ATM_ATM,
1106 CAKE_ATM_PTM,
1107 CAKE_ATM_MAX
1108};
1109
1110
1111
1112enum {
1113 TC_TAPRIO_CMD_SET_GATES = 0x00,
1114 TC_TAPRIO_CMD_SET_AND_HOLD = 0x01,
1115 TC_TAPRIO_CMD_SET_AND_RELEASE = 0x02,
1116};
1117
1118enum {
1119 TCA_TAPRIO_SCHED_ENTRY_UNSPEC,
1120 TCA_TAPRIO_SCHED_ENTRY_INDEX,
1121 TCA_TAPRIO_SCHED_ENTRY_CMD,
1122 TCA_TAPRIO_SCHED_ENTRY_GATE_MASK,
1123 TCA_TAPRIO_SCHED_ENTRY_INTERVAL,
1124 __TCA_TAPRIO_SCHED_ENTRY_MAX,
1125};
1126#define TCA_TAPRIO_SCHED_ENTRY_MAX (__TCA_TAPRIO_SCHED_ENTRY_MAX - 1)
1127
1128
1129
1130
1131
1132
1133
1134
1135enum {
1136 TCA_TAPRIO_SCHED_UNSPEC,
1137 TCA_TAPRIO_SCHED_ENTRY,
1138 __TCA_TAPRIO_SCHED_MAX,
1139};
1140
1141#define TCA_TAPRIO_SCHED_MAX (__TCA_TAPRIO_SCHED_MAX - 1)
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153#define TCA_TAPRIO_ATTR_FLAG_TXTIME_ASSIST _BITUL(0)
1154#define TCA_TAPRIO_ATTR_FLAG_FULL_OFFLOAD _BITUL(1)
1155
1156enum {
1157 TCA_TAPRIO_TC_ENTRY_UNSPEC,
1158 TCA_TAPRIO_TC_ENTRY_INDEX,
1159 TCA_TAPRIO_TC_ENTRY_MAX_SDU,
1160 TCA_TAPRIO_TC_ENTRY_FP,
1161
1162
1163 __TCA_TAPRIO_TC_ENTRY_CNT,
1164 TCA_TAPRIO_TC_ENTRY_MAX = (__TCA_TAPRIO_TC_ENTRY_CNT - 1)
1165};
1166
1167enum {
1168 TCA_TAPRIO_OFFLOAD_STATS_PAD = 1,
1169 TCA_TAPRIO_OFFLOAD_STATS_WINDOW_DROPS,
1170 TCA_TAPRIO_OFFLOAD_STATS_TX_OVERRUNS,
1171
1172
1173 __TCA_TAPRIO_OFFLOAD_STATS_CNT,
1174 TCA_TAPRIO_OFFLOAD_STATS_MAX = (__TCA_TAPRIO_OFFLOAD_STATS_CNT - 1)
1175};
1176
1177enum {
1178 TCA_TAPRIO_ATTR_UNSPEC,
1179 TCA_TAPRIO_ATTR_PRIOMAP,
1180 TCA_TAPRIO_ATTR_SCHED_ENTRY_LIST,
1181 TCA_TAPRIO_ATTR_SCHED_BASE_TIME,
1182 TCA_TAPRIO_ATTR_SCHED_SINGLE_ENTRY,
1183 TCA_TAPRIO_ATTR_SCHED_CLOCKID,
1184 TCA_TAPRIO_PAD,
1185 TCA_TAPRIO_ATTR_PAD = TCA_TAPRIO_PAD,
1186 TCA_TAPRIO_ATTR_ADMIN_SCHED,
1187 TCA_TAPRIO_ATTR_SCHED_CYCLE_TIME,
1188 TCA_TAPRIO_ATTR_SCHED_CYCLE_TIME_EXTENSION,
1189 TCA_TAPRIO_ATTR_FLAGS,
1190 TCA_TAPRIO_ATTR_TXTIME_DELAY,
1191 TCA_TAPRIO_ATTR_TC_ENTRY,
1192 __TCA_TAPRIO_ATTR_MAX,
1193};
1194
1195#define TCA_TAPRIO_ATTR_MAX (__TCA_TAPRIO_ATTR_MAX - 1)
1196
1197
1198
1199#define TCQ_ETS_MAX_BANDS 16
1200
1201enum {
1202 TCA_ETS_UNSPEC,
1203 TCA_ETS_NBANDS,
1204 TCA_ETS_NSTRICT,
1205 TCA_ETS_QUANTA,
1206 TCA_ETS_QUANTA_BAND,
1207 TCA_ETS_PRIOMAP,
1208 TCA_ETS_PRIOMAP_BAND,
1209 __TCA_ETS_MAX,
1210};
1211
1212#define TCA_ETS_MAX (__TCA_ETS_MAX - 1)
1213
1214
1215enum tc_dualpi2_drop_overload {
1216 TC_DUALPI2_DROP_OVERLOAD_OVERFLOW = 0,
1217 TC_DUALPI2_DROP_OVERLOAD_DROP = 1,
1218 __TCA_DUALPI2_DROP_OVERLOAD_MAX,
1219};
1220#define TCA_DUALPI2_DROP_OVERLOAD_MAX (__TCA_DUALPI2_DROP_OVERLOAD_MAX - 1)
1221
1222enum tc_dualpi2_drop_early {
1223 TC_DUALPI2_DROP_EARLY_DROP_DEQUEUE = 0,
1224 TC_DUALPI2_DROP_EARLY_DROP_ENQUEUE = 1,
1225 __TCA_DUALPI2_DROP_EARLY_MAX,
1226};
1227#define TCA_DUALPI2_DROP_EARLY_MAX (__TCA_DUALPI2_DROP_EARLY_MAX - 1)
1228
1229enum tc_dualpi2_ecn_mask {
1230 TC_DUALPI2_ECN_MASK_L4S_ECT = 1,
1231 TC_DUALPI2_ECN_MASK_CLA_ECT = 2,
1232 TC_DUALPI2_ECN_MASK_ANY_ECT = 3,
1233 __TCA_DUALPI2_ECN_MASK_MAX,
1234};
1235#define TCA_DUALPI2_ECN_MASK_MAX (__TCA_DUALPI2_ECN_MASK_MAX - 1)
1236
1237enum tc_dualpi2_split_gso {
1238 TC_DUALPI2_SPLIT_GSO_NO_SPLIT_GSO = 0,
1239 TC_DUALPI2_SPLIT_GSO_SPLIT_GSO = 1,
1240 __TCA_DUALPI2_SPLIT_GSO_MAX,
1241};
1242#define TCA_DUALPI2_SPLIT_GSO_MAX (__TCA_DUALPI2_SPLIT_GSO_MAX - 1)
1243
1244enum {
1245 TCA_DUALPI2_UNSPEC,
1246 TCA_DUALPI2_LIMIT,
1247 TCA_DUALPI2_MEMORY_LIMIT,
1248 TCA_DUALPI2_TARGET,
1249 TCA_DUALPI2_TUPDATE,
1250 TCA_DUALPI2_ALPHA,
1251 TCA_DUALPI2_BETA,
1252 TCA_DUALPI2_STEP_THRESH_PKTS,
1253 TCA_DUALPI2_STEP_THRESH_US,
1254 TCA_DUALPI2_MIN_QLEN_STEP,
1255 TCA_DUALPI2_COUPLING,
1256 TCA_DUALPI2_DROP_OVERLOAD,
1257 TCA_DUALPI2_DROP_EARLY,
1258 TCA_DUALPI2_C_PROTECTION,
1259 TCA_DUALPI2_ECN_MASK,
1260 TCA_DUALPI2_SPLIT_GSO,
1261 TCA_DUALPI2_PAD,
1262 __TCA_DUALPI2_MAX
1263};
1264
1265#define TCA_DUALPI2_MAX (__TCA_DUALPI2_MAX - 1)
1266
1267struct tc_dualpi2_xstats {
1268 __u32 prob;
1269 __u32 delay_c;
1270 __u32 delay_l;
1271 __u32 packets_in_c;
1272 __u32 packets_in_l;
1273 __u32 maxq;
1274 __u32 ecn_mark;
1275 __u32 step_marks;
1276 __s32 credit;
1277 __u32 memory_used;
1278 __u32 max_memory_used;
1279 __u32 memory_limit;
1280};
1281
1282#endif
1283