LXR linux/arch/arm/mach-omap2/clock36xx.c

   1/*
   2 * OMAP36xx-specific clkops
   3 *
   4 * Copyright (C) 2010 Texas Instruments, Inc.
   5 * Copyright (C) 2010 Nokia Corporation
   6 *
   7 * Mike Turquette
   8 * Vijaykumar GN
   9 * Paul Walmsley
  10 *
  11 * Parts of this code are based on code written by
  12 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu,
  13 * Russell King
  14 *
  15 * This program is free software; you can redistribute it and/or modify
  16 * it under the terms of the GNU General Public License version 2 as
  17 * published by the Free Software Foundation.
  18 */
  19#undef DEBUG
  20
  21#include <linux/kernel.h>
  22#include <linux/clk.h>
  23#include <linux/clk-provider.h>
  24#include <linux/io.h>
  25
  26#include "clock.h"
  27#include "clock36xx.h"
  28#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
  29
  30/**
  31 * omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering
  32 *         from HSDivider PWRDN problem Implements Errata ID: i556.
  33 * @clk: DPLL output struct clk
  34 *
  35 * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
  36 * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
  37 * valueafter their respective PWRDN bits are set.  Any dummy write
  38 * (Any other value different from the Read value) to the
  39 * corresponding CM_CLKSEL register will refresh the dividers.
  40 */
  41int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
  42{
  43        struct clk_divider *parent;
  44        struct clk_hw *parent_hw;
  45        u32 dummy_v, orig_v;
  46        int ret;
  47
  48        /* Clear PWRDN bit of HSDIVIDER */
  49        ret = omap2_dflt_clk_enable(clk);
  50
  51        parent_hw = __clk_get_hw(__clk_get_parent(clk->clk));
  52        parent = to_clk_divider(parent_hw);
  53
  54        /* Restore the dividers */
  55        if (!ret) {
  56                orig_v = __raw_readl(parent->reg);
  57                dummy_v = orig_v;
  58
  59                /* Write any other value different from the Read value */
  60                dummy_v ^= (1 << parent->shift);
  61                __raw_writel(dummy_v, parent->reg);
  62
  63                /* Write the original divider */
  64                __raw_writel(orig_v, parent->reg);
  65        }
  66
  67        return ret;
  68}
  69